pci_bwx_bus_mem_chipdep.c revision 1.17.18.3
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.17.18.3 2004/09/21 13:12:01 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/cdefs.h> 86 __KERNEL_RCSID(1, "$NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.17.18.3 2004/09/21 13:12:01 skrll Exp $"); 87 88 #include <sys/extent.h> 89 90 #include <machine/bwx.h> 91 92 #define __C(A,B) __CONCAT(A,B) 93 #define __S(S) __STRING(S) 94 95 /* mapping/unmapping */ 96 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 97 bus_space_handle_t *, int)); 98 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 99 bus_size_t, int)); 100 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 101 bus_size_t, bus_size_t, bus_space_handle_t *)); 102 103 int __C(CHIP,_mem_translate) __P((void *, bus_addr_t, bus_size_t, 104 int, struct alpha_bus_space_translation *)); 105 int __C(CHIP,_mem_get_window) __P((void *, int, 106 struct alpha_bus_space_translation *)); 107 108 /* allocation/deallocation */ 109 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 110 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 111 bus_space_handle_t *)); 112 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 115 /* get kernel virtual address */ 116 void * __C(CHIP,_mem_vaddr) __P((void *, bus_space_handle_t)); 117 118 /* mmap for user */ 119 paddr_t __C(CHIP,_mem_mmap) __P((void *, bus_addr_t, off_t, int, int)); 120 121 /* barrier */ 122 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 123 bus_size_t, bus_size_t, int)); 124 125 /* read (single) */ 126 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 127 bus_size_t)); 128 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 129 bus_size_t)); 130 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 131 bus_size_t)); 132 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 133 bus_size_t)); 134 135 /* read multiple */ 136 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int8_t *, bus_size_t)); 138 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int16_t *, bus_size_t)); 140 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int32_t *, bus_size_t)); 142 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int64_t *, bus_size_t)); 144 145 /* read region */ 146 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int8_t *, bus_size_t)); 148 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 149 bus_size_t, u_int16_t *, bus_size_t)); 150 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int32_t *, bus_size_t)); 152 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 153 bus_size_t, u_int64_t *, bus_size_t)); 154 155 /* write (single) */ 156 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int8_t)); 158 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 159 bus_size_t, u_int16_t)); 160 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 161 bus_size_t, u_int32_t)); 162 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 163 bus_size_t, u_int64_t)); 164 165 /* write multiple */ 166 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int8_t *, bus_size_t)); 168 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 169 bus_size_t, const u_int16_t *, bus_size_t)); 170 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int32_t *, bus_size_t)); 172 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 173 bus_size_t, const u_int64_t *, bus_size_t)); 174 175 /* write region */ 176 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int8_t *, bus_size_t)); 178 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 179 bus_size_t, const u_int16_t *, bus_size_t)); 180 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 181 bus_size_t, const u_int32_t *, bus_size_t)); 182 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 183 bus_size_t, const u_int64_t *, bus_size_t)); 184 185 /* set multiple */ 186 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int8_t, bus_size_t)); 188 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 189 bus_size_t, u_int16_t, bus_size_t)); 190 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int32_t, bus_size_t)); 192 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 193 bus_size_t, u_int64_t, bus_size_t)); 194 195 /* set region */ 196 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int8_t, bus_size_t)); 198 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 199 bus_size_t, u_int16_t, bus_size_t)); 200 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 201 bus_size_t, u_int32_t, bus_size_t)); 202 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 203 bus_size_t, u_int64_t, bus_size_t)); 204 205 /* copy */ 206 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 208 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 209 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 210 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 211 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 212 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 213 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 214 215 #ifndef CHIP_MEM_EX_STORE 216 static long 217 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 218 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 219 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 220 #endif 221 222 void 223 __C(CHIP,_bus_mem_init)(t, v) 224 bus_space_tag_t t; 225 void *v; 226 { 227 struct extent *ex; 228 229 /* 230 * Initialize the bus space tag. 231 */ 232 233 /* cookie */ 234 t->abs_cookie = v; 235 236 /* mapping/unmapping */ 237 t->abs_map = __C(CHIP,_mem_map); 238 t->abs_unmap = __C(CHIP,_mem_unmap); 239 t->abs_subregion = __C(CHIP,_mem_subregion); 240 241 t->abs_translate = __C(CHIP,_mem_translate); 242 t->abs_get_window = __C(CHIP,_mem_get_window); 243 244 /* allocation/deallocation */ 245 t->abs_alloc = __C(CHIP,_mem_alloc); 246 t->abs_free = __C(CHIP,_mem_free); 247 248 /* get kernel virtual address */ 249 t->abs_vaddr = __C(CHIP,_mem_vaddr); 250 251 /* mmap for user */ 252 t->abs_mmap = __C(CHIP,_mem_mmap); 253 254 /* barrier */ 255 t->abs_barrier = __C(CHIP,_mem_barrier); 256 257 /* read (single) */ 258 t->abs_r_1 = __C(CHIP,_mem_read_1); 259 t->abs_r_2 = __C(CHIP,_mem_read_2); 260 t->abs_r_4 = __C(CHIP,_mem_read_4); 261 t->abs_r_8 = __C(CHIP,_mem_read_8); 262 263 /* read multiple */ 264 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 265 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 266 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 267 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 268 269 /* read region */ 270 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 271 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 272 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 273 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 274 275 /* write (single) */ 276 t->abs_w_1 = __C(CHIP,_mem_write_1); 277 t->abs_w_2 = __C(CHIP,_mem_write_2); 278 t->abs_w_4 = __C(CHIP,_mem_write_4); 279 t->abs_w_8 = __C(CHIP,_mem_write_8); 280 281 /* write multiple */ 282 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 283 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 284 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 285 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 286 287 /* write region */ 288 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 289 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 290 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 291 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 292 293 /* set multiple */ 294 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 295 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 296 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 297 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 298 299 /* set region */ 300 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 301 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 302 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 303 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 304 305 /* copy */ 306 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 307 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 308 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 309 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 310 311 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 312 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 313 EX_NOWAIT|EX_NOCOALESCE); 314 315 CHIP_MEM_EXTENT(v) = ex; 316 } 317 318 int 319 __C(CHIP,_mem_translate)(v, memaddr, memlen, flags, abst) 320 void *v; 321 bus_addr_t memaddr; 322 bus_size_t memlen; 323 int flags; 324 struct alpha_bus_space_translation *abst; 325 { 326 327 /* XXX */ 328 return (EOPNOTSUPP); 329 } 330 331 int 332 __C(CHIP,_mem_get_window)(v, window, abst) 333 void *v; 334 int window; 335 struct alpha_bus_space_translation *abst; 336 { 337 338 switch (window) { 339 case 0: 340 abst->abst_bus_start = 0; 341 abst->abst_bus_end = 0xffffffffUL; 342 abst->abst_sys_start = CHIP_MEM_SYS_START(v); 343 abst->abst_sys_end = CHIP_MEM_SYS_START(v) + abst->abst_bus_end; 344 abst->abst_addr_shift = 0; 345 abst->abst_size_shift = 0; 346 abst->abst_flags = ABST_DENSE|ABST_BWX; 347 break; 348 349 default: 350 panic(__S(__C(CHIP,_mem_get_window)) ": invalid window %d", 351 window); 352 } 353 354 return (0); 355 } 356 357 int 358 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 359 void *v; 360 bus_addr_t memaddr; 361 bus_size_t memsize; 362 int flags; 363 bus_space_handle_t *memhp; 364 int acct; 365 { 366 int error; 367 368 if (acct == 0) 369 goto mapit; 370 371 #ifdef EXTENT_DEBUG 372 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 373 memaddr + memsize - 1); 374 #endif 375 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 376 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 377 if (error) { 378 #ifdef EXTENT_DEBUG 379 printf("mem: allocation failed (%d)\n", error); 380 extent_print(CHIP_MEM_EXTENT(v)); 381 #endif 382 return (error); 383 } 384 385 mapit: 386 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 387 388 return (0); 389 } 390 391 void 392 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 393 void *v; 394 bus_space_handle_t memh; 395 bus_size_t memsize; 396 int acct; 397 { 398 bus_addr_t memaddr; 399 int error; 400 401 if (acct == 0) 402 return; 403 404 #ifdef EXTENT_DEBUG 405 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 406 #endif 407 408 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 409 410 #ifdef EXTENT_DEBUG 411 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 412 #endif 413 414 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 415 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 416 if (error) { 417 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 418 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 419 error); 420 #ifdef EXTENT_DEBUG 421 extent_print(CHIP_MEM_EXTENT(v)); 422 #endif 423 } 424 } 425 426 int 427 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 428 void *v; 429 bus_space_handle_t memh, *nmemh; 430 bus_size_t offset, size; 431 { 432 433 *nmemh = memh + offset; 434 return (0); 435 } 436 437 int 438 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 439 addrp, bshp) 440 void *v; 441 bus_addr_t rstart, rend, *addrp; 442 bus_size_t size, align, boundary; 443 int flags; 444 bus_space_handle_t *bshp; 445 { 446 bus_addr_t memaddr; 447 int error; 448 449 /* 450 * Do the requested allocation. 451 */ 452 #ifdef EXTENT_DEBUG 453 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 454 #endif 455 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 456 size, align, boundary, 457 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 458 &memaddr); 459 if (error) { 460 #ifdef EXTENT_DEBUG 461 printf("mem: allocation failed (%d)\n", error); 462 extent_print(CHIP_MEM_EXTENT(v)); 463 #endif 464 } 465 466 #ifdef EXTENT_DEBUG 467 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 468 #endif 469 470 *addrp = memaddr; 471 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 472 473 return (0); 474 } 475 476 void 477 __C(CHIP,_mem_free)(v, bsh, size) 478 void *v; 479 bus_space_handle_t bsh; 480 bus_size_t size; 481 { 482 483 /* Unmap does all we need to do. */ 484 __C(CHIP,_mem_unmap)(v, bsh, size, 1); 485 } 486 487 void * 488 __C(CHIP,_mem_vaddr)(v, bsh) 489 void *v; 490 bus_space_handle_t bsh; 491 { 492 493 return ((void *)bsh); 494 } 495 496 paddr_t 497 __C(CHIP,_mem_mmap)(v, addr, off, prot, flags) 498 void *v; 499 bus_addr_t addr; 500 off_t off; 501 int prot; 502 int flags; 503 { 504 505 return (alpha_btop(CHIP_MEM_SYS_START(v) + addr + off)); 506 } 507 508 inline void 509 __C(CHIP,_mem_barrier)(v, h, o, l, f) 510 void *v; 511 bus_space_handle_t h; 512 bus_size_t o, l; 513 int f; 514 { 515 516 if ((f & BUS_SPACE_BARRIER_READ) != 0) 517 alpha_mb(); 518 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 519 alpha_wmb(); 520 } 521 522 inline u_int8_t 523 __C(CHIP,_mem_read_1)(v, memh, off) 524 void *v; 525 bus_space_handle_t memh; 526 bus_size_t off; 527 { 528 bus_addr_t addr; 529 530 addr = memh + off; 531 alpha_mb(); 532 return (alpha_ldbu((u_int8_t *)addr)); 533 } 534 535 inline u_int16_t 536 __C(CHIP,_mem_read_2)(v, memh, off) 537 void *v; 538 bus_space_handle_t memh; 539 bus_size_t off; 540 { 541 bus_addr_t addr; 542 543 addr = memh + off; 544 #ifdef DIAGNOSTIC 545 if (addr & 1) 546 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 547 addr); 548 #endif 549 alpha_mb(); 550 return (alpha_ldwu((u_int16_t *)addr)); 551 } 552 553 inline u_int32_t 554 __C(CHIP,_mem_read_4)(v, memh, off) 555 void *v; 556 bus_space_handle_t memh; 557 bus_size_t off; 558 { 559 bus_addr_t addr; 560 561 addr = memh + off; 562 #ifdef DIAGNOSTIC 563 if (addr & 3) 564 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 565 addr); 566 #endif 567 alpha_mb(); 568 return (*(u_int32_t *)addr); 569 } 570 571 inline u_int64_t 572 __C(CHIP,_mem_read_8)(v, memh, off) 573 void *v; 574 bus_space_handle_t memh; 575 bus_size_t off; 576 { 577 578 alpha_mb(); 579 580 /* XXX XXX XXX */ 581 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 582 } 583 584 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 585 void \ 586 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 587 void *v; \ 588 bus_space_handle_t h; \ 589 bus_size_t o, c; \ 590 TYPE *a; \ 591 { \ 592 \ 593 while (c-- > 0) { \ 594 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 595 BUS_SPACE_BARRIER_READ); \ 596 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 597 } \ 598 } 599 CHIP_mem_read_multi_N(1,u_int8_t) 600 CHIP_mem_read_multi_N(2,u_int16_t) 601 CHIP_mem_read_multi_N(4,u_int32_t) 602 CHIP_mem_read_multi_N(8,u_int64_t) 603 604 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 605 void \ 606 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 607 void *v; \ 608 bus_space_handle_t h; \ 609 bus_size_t o, c; \ 610 TYPE *a; \ 611 { \ 612 \ 613 while (c-- > 0) { \ 614 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 615 o += sizeof *a; \ 616 } \ 617 } 618 CHIP_mem_read_region_N(1,u_int8_t) 619 CHIP_mem_read_region_N(2,u_int16_t) 620 CHIP_mem_read_region_N(4,u_int32_t) 621 CHIP_mem_read_region_N(8,u_int64_t) 622 623 inline void 624 __C(CHIP,_mem_write_1)(v, memh, off, val) 625 void *v; 626 bus_space_handle_t memh; 627 bus_size_t off; 628 u_int8_t val; 629 { 630 bus_addr_t addr; 631 632 addr = memh + off; 633 alpha_stb((u_int8_t *)addr, val); 634 alpha_mb(); 635 } 636 637 inline void 638 __C(CHIP,_mem_write_2)(v, memh, off, val) 639 void *v; 640 bus_space_handle_t memh; 641 bus_size_t off; 642 u_int16_t val; 643 { 644 bus_addr_t addr; 645 646 addr = memh + off; 647 #ifdef DIAGNOSTIC 648 if (addr & 1) 649 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 650 addr); 651 #endif 652 alpha_stw((u_int16_t *)addr, val); 653 alpha_mb(); 654 } 655 656 inline void 657 __C(CHIP,_mem_write_4)(v, memh, off, val) 658 void *v; 659 bus_space_handle_t memh; 660 bus_size_t off; 661 u_int32_t val; 662 { 663 bus_addr_t addr; 664 665 addr = memh + off; 666 #ifdef DIAGNOSTIC 667 if (addr & 3) 668 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 669 addr); 670 #endif 671 *(u_int32_t *)addr = val; 672 alpha_mb(); 673 } 674 675 inline void 676 __C(CHIP,_mem_write_8)(v, memh, off, val) 677 void *v; 678 bus_space_handle_t memh; 679 bus_size_t off; 680 u_int64_t val; 681 { 682 683 /* XXX XXX XXX */ 684 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 685 alpha_mb(); 686 } 687 688 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 689 void \ 690 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 691 void *v; \ 692 bus_space_handle_t h; \ 693 bus_size_t o, c; \ 694 const TYPE *a; \ 695 { \ 696 \ 697 while (c-- > 0) { \ 698 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 699 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 700 BUS_SPACE_BARRIER_WRITE); \ 701 } \ 702 } 703 CHIP_mem_write_multi_N(1,u_int8_t) 704 CHIP_mem_write_multi_N(2,u_int16_t) 705 CHIP_mem_write_multi_N(4,u_int32_t) 706 CHIP_mem_write_multi_N(8,u_int64_t) 707 708 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 709 void \ 710 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 711 void *v; \ 712 bus_space_handle_t h; \ 713 bus_size_t o, c; \ 714 const TYPE *a; \ 715 { \ 716 \ 717 while (c-- > 0) { \ 718 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 719 o += sizeof *a; \ 720 } \ 721 } 722 CHIP_mem_write_region_N(1,u_int8_t) 723 CHIP_mem_write_region_N(2,u_int16_t) 724 CHIP_mem_write_region_N(4,u_int32_t) 725 CHIP_mem_write_region_N(8,u_int64_t) 726 727 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 728 void \ 729 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 730 void *v; \ 731 bus_space_handle_t h; \ 732 bus_size_t o, c; \ 733 TYPE val; \ 734 { \ 735 \ 736 while (c-- > 0) { \ 737 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 738 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 739 BUS_SPACE_BARRIER_WRITE); \ 740 } \ 741 } 742 CHIP_mem_set_multi_N(1,u_int8_t) 743 CHIP_mem_set_multi_N(2,u_int16_t) 744 CHIP_mem_set_multi_N(4,u_int32_t) 745 CHIP_mem_set_multi_N(8,u_int64_t) 746 747 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 748 void \ 749 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 750 void *v; \ 751 bus_space_handle_t h; \ 752 bus_size_t o, c; \ 753 TYPE val; \ 754 { \ 755 \ 756 while (c-- > 0) { \ 757 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 758 o += sizeof val; \ 759 } \ 760 } 761 CHIP_mem_set_region_N(1,u_int8_t) 762 CHIP_mem_set_region_N(2,u_int16_t) 763 CHIP_mem_set_region_N(4,u_int32_t) 764 CHIP_mem_set_region_N(8,u_int64_t) 765 766 #define CHIP_mem_copy_region_N(BYTES) \ 767 void \ 768 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 769 void *v; \ 770 bus_space_handle_t h1, h2; \ 771 bus_size_t o1, o2, c; \ 772 { \ 773 bus_size_t o; \ 774 \ 775 if ((h1 + o1) >= (h2 + o2)) { \ 776 /* src after dest: copy forward */ \ 777 for (o = 0; c != 0; c--, o += BYTES) { \ 778 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 779 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 780 } \ 781 } else { \ 782 /* dest after src: copy backwards */ \ 783 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 784 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 785 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 786 } \ 787 } \ 788 } 789 CHIP_mem_copy_region_N(1) 790 CHIP_mem_copy_region_N(2) 791 CHIP_mem_copy_region_N(4) 792 CHIP_mem_copy_region_N(8) 793
Indexes created Wed Oct 29 09:09:48 GMT 2025