pci_bwx_bus_mem_chipdep.c revision 1.2
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.2 1998/06/06 22:28:16 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *)); 93 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t)); 95 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 /* allocation/deallocation */ 99 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 100 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 101 bus_space_handle_t *)); 102 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 103 bus_size_t)); 104 105 /* barrier */ 106 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 107 bus_size_t, bus_size_t, int)); 108 109 /* read (single) */ 110 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* read multiple */ 120 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t *, bus_size_t)); 122 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t *, bus_size_t)); 124 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t *, bus_size_t)); 126 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t *, bus_size_t)); 128 129 /* read region */ 130 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* write (single) */ 140 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t)); 142 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t)); 144 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t)); 146 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t)); 148 149 /* write multiple */ 150 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 151 bus_size_t, const u_int8_t *, bus_size_t)); 152 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int16_t *, bus_size_t)); 154 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int32_t *, bus_size_t)); 156 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int64_t *, bus_size_t)); 158 159 /* write region */ 160 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* set multiple */ 170 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, u_int8_t, bus_size_t)); 172 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int16_t, bus_size_t)); 174 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int32_t, bus_size_t)); 176 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int64_t, bus_size_t)); 178 179 /* set region */ 180 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* copy */ 190 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 192 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 199 #ifndef CHIP_MEM_EX_STORE 200 static long 201 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 202 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 203 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 204 #endif 205 206 void 207 __C(CHIP,_bus_mem_init)(t, v) 208 bus_space_tag_t t; 209 void *v; 210 { 211 struct extent *ex; 212 213 /* 214 * Initialize the bus space tag. 215 */ 216 217 /* cookie */ 218 t->abs_cookie = v; 219 220 /* mapping/unmapping */ 221 t->abs_map = __C(CHIP,_mem_map); 222 t->abs_unmap = __C(CHIP,_mem_unmap); 223 t->abs_subregion = __C(CHIP,_mem_subregion); 224 225 /* allocation/deallocation */ 226 t->abs_alloc = __C(CHIP,_mem_alloc); 227 t->abs_free = __C(CHIP,_mem_free); 228 229 /* barrier */ 230 t->abs_barrier = __C(CHIP,_mem_barrier); 231 232 /* read (single) */ 233 t->abs_r_1 = __C(CHIP,_mem_read_1); 234 t->abs_r_2 = __C(CHIP,_mem_read_2); 235 t->abs_r_4 = __C(CHIP,_mem_read_4); 236 t->abs_r_8 = __C(CHIP,_mem_read_8); 237 238 /* read multiple */ 239 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 240 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 241 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 242 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 243 244 /* read region */ 245 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 246 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 247 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 248 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 249 250 /* write (single) */ 251 t->abs_w_1 = __C(CHIP,_mem_write_1); 252 t->abs_w_2 = __C(CHIP,_mem_write_2); 253 t->abs_w_4 = __C(CHIP,_mem_write_4); 254 t->abs_w_8 = __C(CHIP,_mem_write_8); 255 256 /* write multiple */ 257 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 258 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 259 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 260 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 261 262 /* write region */ 263 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 264 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 265 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 266 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 267 268 /* set multiple */ 269 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 270 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 271 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 272 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 273 274 /* set region */ 275 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 276 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 277 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 278 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 279 280 /* copy */ 281 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 282 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 283 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 284 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 285 286 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 287 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 288 EX_NOWAIT|EX_NOCOALESCE); 289 290 CHIP_MEM_EXTENT(v) = ex; 291 } 292 293 int 294 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp) 295 void *v; 296 bus_addr_t memaddr; 297 bus_size_t memsize; 298 int flags; 299 bus_space_handle_t *memhp; 300 { 301 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 302 int linear = flags & BUS_SPACE_MAP_LINEAR; 303 int error; 304 305 /* Requests for linear uncacheable space can't be satisfied. */ 306 if (linear && !cacheable) 307 return (EOPNOTSUPP); 308 309 #ifdef EXTENT_DEBUG 310 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 311 memaddr + memsize - 1); 312 #endif 313 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 314 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 315 if (error) { 316 #ifdef EXTENT_DEBUG 317 printf("mem: allocation failed (%d)\n", error); 318 extent_print(CHIP_MEM_EXTENT(v)); 319 #endif 320 return (error); 321 } 322 323 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 324 325 return (0); 326 } 327 328 void 329 __C(CHIP,_mem_unmap)(v, memh, memsize) 330 void *v; 331 bus_space_handle_t memh; 332 bus_size_t memsize; 333 { 334 bus_addr_t memaddr; 335 int error; 336 337 #ifdef EXTENT_DEBUG 338 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 339 #endif 340 341 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 342 343 #ifdef EXTENT_DEBUG 344 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 345 #endif 346 347 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 348 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 349 if (error) { 350 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 351 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 352 error); 353 #ifdef EXTENT_DEBUG 354 extent_print(CHIP_MEM_EXTENT(v)); 355 #endif 356 } 357 } 358 359 int 360 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 361 void *v; 362 bus_space_handle_t memh, *nmemh; 363 bus_size_t offset, size; 364 { 365 366 *nmemh = memh + offset; 367 return (0); 368 } 369 370 int 371 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 372 addrp, bshp) 373 void *v; 374 bus_addr_t rstart, rend, *addrp; 375 bus_size_t size, align, boundary; 376 int flags; 377 bus_space_handle_t *bshp; 378 { 379 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 380 int linear = flags & BUS_SPACE_MAP_LINEAR; 381 bus_addr_t memaddr; 382 int error; 383 384 /* Requests for linear uncacheable space can't be satisfied. */ 385 if (linear && !cacheable) 386 return (EOPNOTSUPP); 387 388 /* 389 * Do the requested allocation. 390 */ 391 #ifdef EXTENT_DEBUG 392 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 393 #endif 394 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 395 size, align, boundary, 396 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 397 &memaddr); 398 if (error) { 399 #ifdef EXTENT_DEBUG 400 printf("mem: allocation failed (%d)\n", error); 401 extent_print(CHIP_MEM_EXTENT(v)); 402 #endif 403 } 404 405 #ifdef EXTENT_DEBUG 406 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 407 #endif 408 409 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 410 411 return (0); 412 } 413 414 void 415 __C(CHIP,_mem_free)(v, bsh, size) 416 void *v; 417 bus_space_handle_t bsh; 418 bus_size_t size; 419 { 420 421 /* Unmap does all we need to do. */ 422 __C(CHIP,_mem_unmap)(v, bsh, size); 423 } 424 425 inline void 426 __C(CHIP,_mem_barrier)(v, h, o, l, f) 427 void *v; 428 bus_space_handle_t h; 429 bus_size_t o, l; 430 int f; 431 { 432 433 if ((f & BUS_SPACE_BARRIER_READ) != 0) 434 alpha_mb(); 435 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 436 alpha_wmb(); 437 } 438 439 inline u_int8_t 440 __C(CHIP,_mem_read_1)(v, memh, off) 441 void *v; 442 bus_space_handle_t memh; 443 bus_size_t off; 444 { 445 bus_addr_t addr; 446 447 addr = memh + off; 448 alpha_mb(); 449 return (alpha_ldbu((u_int8_t *)addr)); 450 } 451 452 inline u_int16_t 453 __C(CHIP,_mem_read_2)(v, memh, off) 454 void *v; 455 bus_space_handle_t memh; 456 bus_size_t off; 457 { 458 bus_addr_t addr; 459 460 addr = memh + off; 461 #ifdef DIAGNOSTIC 462 if (addr & 1) 463 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 464 addr); 465 #endif 466 alpha_mb(); 467 return (alpha_ldwu((u_int16_t *)addr)); 468 } 469 470 inline u_int32_t 471 __C(CHIP,_mem_read_4)(v, memh, off) 472 void *v; 473 bus_space_handle_t memh; 474 bus_size_t off; 475 { 476 bus_addr_t addr; 477 478 addr = memh + off; 479 #ifdef DIAGNOSTIC 480 if (addr & 3) 481 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 482 addr); 483 #endif 484 alpha_mb(); 485 return (*(u_int32_t *)addr); 486 } 487 488 inline u_int64_t 489 __C(CHIP,_mem_read_8)(v, memh, off) 490 void *v; 491 bus_space_handle_t memh; 492 bus_size_t off; 493 { 494 495 alpha_mb(); 496 497 /* XXX XXX XXX */ 498 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 499 } 500 501 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 502 void \ 503 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 504 void *v; \ 505 bus_space_handle_t h; \ 506 bus_size_t o, c; \ 507 TYPE *a; \ 508 { \ 509 \ 510 while (c-- > 0) { \ 511 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 512 BUS_BARRIER_READ); \ 513 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 514 } \ 515 } 516 CHIP_mem_read_multi_N(1,u_int8_t) 517 CHIP_mem_read_multi_N(2,u_int16_t) 518 CHIP_mem_read_multi_N(4,u_int32_t) 519 CHIP_mem_read_multi_N(8,u_int64_t) 520 521 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 522 void \ 523 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 524 void *v; \ 525 bus_space_handle_t h; \ 526 bus_size_t o, c; \ 527 TYPE *a; \ 528 { \ 529 \ 530 while (c-- > 0) { \ 531 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 532 o += sizeof *a; \ 533 } \ 534 } 535 CHIP_mem_read_region_N(1,u_int8_t) 536 CHIP_mem_read_region_N(2,u_int16_t) 537 CHIP_mem_read_region_N(4,u_int32_t) 538 CHIP_mem_read_region_N(8,u_int64_t) 539 540 inline void 541 __C(CHIP,_mem_write_1)(v, memh, off, val) 542 void *v; 543 bus_space_handle_t memh; 544 bus_size_t off; 545 u_int8_t val; 546 { 547 bus_addr_t addr; 548 549 addr = memh + off; 550 alpha_stb((u_int8_t *)addr, val); 551 alpha_mb(); 552 } 553 554 inline void 555 __C(CHIP,_mem_write_2)(v, memh, off, val) 556 void *v; 557 bus_space_handle_t memh; 558 bus_size_t off; 559 u_int16_t val; 560 { 561 bus_addr_t addr; 562 563 addr = memh + off; 564 #ifdef DIAGNOSTIC 565 if (addr & 1) 566 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 567 addr); 568 #endif 569 alpha_stw((u_int16_t *)addr, val); 570 alpha_mb(); 571 } 572 573 inline void 574 __C(CHIP,_mem_write_4)(v, memh, off, val) 575 void *v; 576 bus_space_handle_t memh; 577 bus_size_t off; 578 u_int32_t val; 579 { 580 bus_addr_t addr; 581 582 addr = memh + off; 583 #ifdef DIAGNOSTIC 584 if (addr & 3) 585 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 586 addr); 587 #endif 588 *(u_int32_t *)addr = val; 589 alpha_mb(); 590 } 591 592 inline void 593 __C(CHIP,_mem_write_8)(v, memh, off, val) 594 void *v; 595 bus_space_handle_t memh; 596 bus_size_t off; 597 u_int64_t val; 598 { 599 600 /* XXX XXX XXX */ 601 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 602 alpha_mb(); 603 } 604 605 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 606 void \ 607 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 608 void *v; \ 609 bus_space_handle_t h; \ 610 bus_size_t o, c; \ 611 const TYPE *a; \ 612 { \ 613 \ 614 while (c-- > 0) { \ 615 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 616 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 617 BUS_BARRIER_WRITE); \ 618 } \ 619 } 620 CHIP_mem_write_multi_N(1,u_int8_t) 621 CHIP_mem_write_multi_N(2,u_int16_t) 622 CHIP_mem_write_multi_N(4,u_int32_t) 623 CHIP_mem_write_multi_N(8,u_int64_t) 624 625 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 626 void \ 627 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 628 void *v; \ 629 bus_space_handle_t h; \ 630 bus_size_t o, c; \ 631 const TYPE *a; \ 632 { \ 633 \ 634 while (c-- > 0) { \ 635 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 636 o += sizeof *a; \ 637 } \ 638 } 639 CHIP_mem_write_region_N(1,u_int8_t) 640 CHIP_mem_write_region_N(2,u_int16_t) 641 CHIP_mem_write_region_N(4,u_int32_t) 642 CHIP_mem_write_region_N(8,u_int64_t) 643 644 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 645 void \ 646 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 647 void *v; \ 648 bus_space_handle_t h; \ 649 bus_size_t o, c; \ 650 TYPE val; \ 651 { \ 652 \ 653 while (c-- > 0) { \ 654 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 655 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 656 BUS_BARRIER_WRITE); \ 657 } \ 658 } 659 CHIP_mem_set_multi_N(1,u_int8_t) 660 CHIP_mem_set_multi_N(2,u_int16_t) 661 CHIP_mem_set_multi_N(4,u_int32_t) 662 CHIP_mem_set_multi_N(8,u_int64_t) 663 664 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 665 void \ 666 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 667 void *v; \ 668 bus_space_handle_t h; \ 669 bus_size_t o, c; \ 670 TYPE val; \ 671 { \ 672 \ 673 while (c-- > 0) { \ 674 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 675 o += sizeof val; \ 676 } \ 677 } 678 CHIP_mem_set_region_N(1,u_int8_t) 679 CHIP_mem_set_region_N(2,u_int16_t) 680 CHIP_mem_set_region_N(4,u_int32_t) 681 CHIP_mem_set_region_N(8,u_int64_t) 682 683 #define CHIP_mem_copy_region_N(BYTES) \ 684 void \ 685 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 686 void *v; \ 687 bus_space_handle_t h1, h2; \ 688 bus_size_t o1, o2, c; \ 689 { \ 690 bus_size_t o; \ 691 \ 692 if ((h1 + o1) >= (h2 + o2)) { \ 693 /* src after dest: copy forward */ \ 694 for (o = 0; c != 0; c--, o += BYTES) { \ 695 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 696 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 697 } \ 698 } else { \ 699 /* dest after src: copy backwards */ \ 700 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 701 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 702 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 703 } \ 704 } \ 705 } 706 CHIP_mem_copy_region_N(1) 707 CHIP_mem_copy_region_N(2) 708 CHIP_mem_copy_region_N(4) 709 CHIP_mem_copy_region_N(8) 710
Indexes created Tue Oct 28 12:10:06 GMT 2025