pci_bwx_bus_mem_chipdep.c revision 1.4
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.4 1998/07/31 04:37:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *, int)); 93 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t, int)); 95 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 /* allocation/deallocation */ 99 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 100 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 101 bus_space_handle_t *)); 102 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 103 bus_size_t)); 104 105 /* barrier */ 106 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 107 bus_size_t, bus_size_t, int)); 108 109 /* read (single) */ 110 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* read multiple */ 120 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t *, bus_size_t)); 122 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t *, bus_size_t)); 124 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t *, bus_size_t)); 126 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t *, bus_size_t)); 128 129 /* read region */ 130 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* write (single) */ 140 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t)); 142 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t)); 144 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t)); 146 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t)); 148 149 /* write multiple */ 150 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 151 bus_size_t, const u_int8_t *, bus_size_t)); 152 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int16_t *, bus_size_t)); 154 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int32_t *, bus_size_t)); 156 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int64_t *, bus_size_t)); 158 159 /* write region */ 160 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* set multiple */ 170 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, u_int8_t, bus_size_t)); 172 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int16_t, bus_size_t)); 174 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int32_t, bus_size_t)); 176 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int64_t, bus_size_t)); 178 179 /* set region */ 180 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* copy */ 190 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 192 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 199 #ifndef CHIP_MEM_EX_STORE 200 static long 201 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 202 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 203 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 204 #endif 205 206 void 207 __C(CHIP,_bus_mem_init)(t, v) 208 bus_space_tag_t t; 209 void *v; 210 { 211 struct extent *ex; 212 213 /* 214 * Initialize the bus space tag. 215 */ 216 217 /* cookie */ 218 t->abs_cookie = v; 219 220 /* mapping/unmapping */ 221 t->abs_map = __C(CHIP,_mem_map); 222 t->abs_unmap = __C(CHIP,_mem_unmap); 223 t->abs_subregion = __C(CHIP,_mem_subregion); 224 225 /* allocation/deallocation */ 226 t->abs_alloc = __C(CHIP,_mem_alloc); 227 t->abs_free = __C(CHIP,_mem_free); 228 229 /* barrier */ 230 t->abs_barrier = __C(CHIP,_mem_barrier); 231 232 /* read (single) */ 233 t->abs_r_1 = __C(CHIP,_mem_read_1); 234 t->abs_r_2 = __C(CHIP,_mem_read_2); 235 t->abs_r_4 = __C(CHIP,_mem_read_4); 236 t->abs_r_8 = __C(CHIP,_mem_read_8); 237 238 /* read multiple */ 239 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 240 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 241 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 242 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 243 244 /* read region */ 245 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 246 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 247 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 248 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 249 250 /* write (single) */ 251 t->abs_w_1 = __C(CHIP,_mem_write_1); 252 t->abs_w_2 = __C(CHIP,_mem_write_2); 253 t->abs_w_4 = __C(CHIP,_mem_write_4); 254 t->abs_w_8 = __C(CHIP,_mem_write_8); 255 256 /* write multiple */ 257 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 258 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 259 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 260 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 261 262 /* write region */ 263 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 264 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 265 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 266 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 267 268 /* set multiple */ 269 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 270 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 271 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 272 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 273 274 /* set region */ 275 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 276 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 277 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 278 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 279 280 /* copy */ 281 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 282 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 283 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 284 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 285 286 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 287 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 288 EX_NOWAIT|EX_NOCOALESCE); 289 290 CHIP_MEM_EXTENT(v) = ex; 291 } 292 293 int 294 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 295 void *v; 296 bus_addr_t memaddr; 297 bus_size_t memsize; 298 int flags; 299 bus_space_handle_t *memhp; 300 int acct; 301 { 302 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 303 int linear = flags & BUS_SPACE_MAP_LINEAR; 304 int error; 305 306 /* Requests for linear uncacheable space can't be satisfied. */ 307 if (linear && !cacheable) 308 return (EOPNOTSUPP); 309 310 if (acct == 0) 311 goto mapit; 312 313 #ifdef EXTENT_DEBUG 314 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 315 memaddr + memsize - 1); 316 #endif 317 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 318 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 319 if (error) { 320 #ifdef EXTENT_DEBUG 321 printf("mem: allocation failed (%d)\n", error); 322 extent_print(CHIP_MEM_EXTENT(v)); 323 #endif 324 return (error); 325 } 326 327 mapit: 328 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 329 330 return (0); 331 } 332 333 void 334 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 335 void *v; 336 bus_space_handle_t memh; 337 bus_size_t memsize; 338 int acct; 339 { 340 bus_addr_t memaddr; 341 int error; 342 343 if (acct == 0) 344 return; 345 346 #ifdef EXTENT_DEBUG 347 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 348 #endif 349 350 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 351 352 #ifdef EXTENT_DEBUG 353 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 354 #endif 355 356 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 357 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 358 if (error) { 359 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 360 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 361 error); 362 #ifdef EXTENT_DEBUG 363 extent_print(CHIP_MEM_EXTENT(v)); 364 #endif 365 } 366 } 367 368 int 369 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 370 void *v; 371 bus_space_handle_t memh, *nmemh; 372 bus_size_t offset, size; 373 { 374 375 *nmemh = memh + offset; 376 return (0); 377 } 378 379 int 380 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 381 addrp, bshp) 382 void *v; 383 bus_addr_t rstart, rend, *addrp; 384 bus_size_t size, align, boundary; 385 int flags; 386 bus_space_handle_t *bshp; 387 { 388 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 389 int linear = flags & BUS_SPACE_MAP_LINEAR; 390 bus_addr_t memaddr; 391 int error; 392 393 /* Requests for linear uncacheable space can't be satisfied. */ 394 if (linear && !cacheable) 395 return (EOPNOTSUPP); 396 397 /* 398 * Do the requested allocation. 399 */ 400 #ifdef EXTENT_DEBUG 401 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 402 #endif 403 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 404 size, align, boundary, 405 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 406 &memaddr); 407 if (error) { 408 #ifdef EXTENT_DEBUG 409 printf("mem: allocation failed (%d)\n", error); 410 extent_print(CHIP_MEM_EXTENT(v)); 411 #endif 412 } 413 414 #ifdef EXTENT_DEBUG 415 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 416 #endif 417 418 *addrp = memaddr; 419 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 420 421 return (0); 422 } 423 424 void 425 __C(CHIP,_mem_free)(v, bsh, size) 426 void *v; 427 bus_space_handle_t bsh; 428 bus_size_t size; 429 { 430 431 /* Unmap does all we need to do. */ 432 __C(CHIP,_mem_unmap)(v, bsh, size, 1); 433 } 434 435 inline void 436 __C(CHIP,_mem_barrier)(v, h, o, l, f) 437 void *v; 438 bus_space_handle_t h; 439 bus_size_t o, l; 440 int f; 441 { 442 443 if ((f & BUS_SPACE_BARRIER_READ) != 0) 444 alpha_mb(); 445 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 446 alpha_wmb(); 447 } 448 449 inline u_int8_t 450 __C(CHIP,_mem_read_1)(v, memh, off) 451 void *v; 452 bus_space_handle_t memh; 453 bus_size_t off; 454 { 455 bus_addr_t addr; 456 457 addr = memh + off; 458 alpha_mb(); 459 return (alpha_ldbu((u_int8_t *)addr)); 460 } 461 462 inline u_int16_t 463 __C(CHIP,_mem_read_2)(v, memh, off) 464 void *v; 465 bus_space_handle_t memh; 466 bus_size_t off; 467 { 468 bus_addr_t addr; 469 470 addr = memh + off; 471 #ifdef DIAGNOSTIC 472 if (addr & 1) 473 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 474 addr); 475 #endif 476 alpha_mb(); 477 return (alpha_ldwu((u_int16_t *)addr)); 478 } 479 480 inline u_int32_t 481 __C(CHIP,_mem_read_4)(v, memh, off) 482 void *v; 483 bus_space_handle_t memh; 484 bus_size_t off; 485 { 486 bus_addr_t addr; 487 488 addr = memh + off; 489 #ifdef DIAGNOSTIC 490 if (addr & 3) 491 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 492 addr); 493 #endif 494 alpha_mb(); 495 return (*(u_int32_t *)addr); 496 } 497 498 inline u_int64_t 499 __C(CHIP,_mem_read_8)(v, memh, off) 500 void *v; 501 bus_space_handle_t memh; 502 bus_size_t off; 503 { 504 505 alpha_mb(); 506 507 /* XXX XXX XXX */ 508 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 509 } 510 511 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 512 void \ 513 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 514 void *v; \ 515 bus_space_handle_t h; \ 516 bus_size_t o, c; \ 517 TYPE *a; \ 518 { \ 519 \ 520 while (c-- > 0) { \ 521 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 522 BUS_BARRIER_READ); \ 523 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 524 } \ 525 } 526 CHIP_mem_read_multi_N(1,u_int8_t) 527 CHIP_mem_read_multi_N(2,u_int16_t) 528 CHIP_mem_read_multi_N(4,u_int32_t) 529 CHIP_mem_read_multi_N(8,u_int64_t) 530 531 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 532 void \ 533 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 534 void *v; \ 535 bus_space_handle_t h; \ 536 bus_size_t o, c; \ 537 TYPE *a; \ 538 { \ 539 \ 540 while (c-- > 0) { \ 541 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 542 o += sizeof *a; \ 543 } \ 544 } 545 CHIP_mem_read_region_N(1,u_int8_t) 546 CHIP_mem_read_region_N(2,u_int16_t) 547 CHIP_mem_read_region_N(4,u_int32_t) 548 CHIP_mem_read_region_N(8,u_int64_t) 549 550 inline void 551 __C(CHIP,_mem_write_1)(v, memh, off, val) 552 void *v; 553 bus_space_handle_t memh; 554 bus_size_t off; 555 u_int8_t val; 556 { 557 bus_addr_t addr; 558 559 addr = memh + off; 560 alpha_stb((u_int8_t *)addr, val); 561 alpha_mb(); 562 } 563 564 inline void 565 __C(CHIP,_mem_write_2)(v, memh, off, val) 566 void *v; 567 bus_space_handle_t memh; 568 bus_size_t off; 569 u_int16_t val; 570 { 571 bus_addr_t addr; 572 573 addr = memh + off; 574 #ifdef DIAGNOSTIC 575 if (addr & 1) 576 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 577 addr); 578 #endif 579 alpha_stw((u_int16_t *)addr, val); 580 alpha_mb(); 581 } 582 583 inline void 584 __C(CHIP,_mem_write_4)(v, memh, off, val) 585 void *v; 586 bus_space_handle_t memh; 587 bus_size_t off; 588 u_int32_t val; 589 { 590 bus_addr_t addr; 591 592 addr = memh + off; 593 #ifdef DIAGNOSTIC 594 if (addr & 3) 595 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 596 addr); 597 #endif 598 *(u_int32_t *)addr = val; 599 alpha_mb(); 600 } 601 602 inline void 603 __C(CHIP,_mem_write_8)(v, memh, off, val) 604 void *v; 605 bus_space_handle_t memh; 606 bus_size_t off; 607 u_int64_t val; 608 { 609 610 /* XXX XXX XXX */ 611 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 612 alpha_mb(); 613 } 614 615 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 616 void \ 617 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 618 void *v; \ 619 bus_space_handle_t h; \ 620 bus_size_t o, c; \ 621 const TYPE *a; \ 622 { \ 623 \ 624 while (c-- > 0) { \ 625 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 626 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 627 BUS_BARRIER_WRITE); \ 628 } \ 629 } 630 CHIP_mem_write_multi_N(1,u_int8_t) 631 CHIP_mem_write_multi_N(2,u_int16_t) 632 CHIP_mem_write_multi_N(4,u_int32_t) 633 CHIP_mem_write_multi_N(8,u_int64_t) 634 635 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 636 void \ 637 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 638 void *v; \ 639 bus_space_handle_t h; \ 640 bus_size_t o, c; \ 641 const TYPE *a; \ 642 { \ 643 \ 644 while (c-- > 0) { \ 645 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 646 o += sizeof *a; \ 647 } \ 648 } 649 CHIP_mem_write_region_N(1,u_int8_t) 650 CHIP_mem_write_region_N(2,u_int16_t) 651 CHIP_mem_write_region_N(4,u_int32_t) 652 CHIP_mem_write_region_N(8,u_int64_t) 653 654 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 655 void \ 656 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 657 void *v; \ 658 bus_space_handle_t h; \ 659 bus_size_t o, c; \ 660 TYPE val; \ 661 { \ 662 \ 663 while (c-- > 0) { \ 664 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 665 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 666 BUS_BARRIER_WRITE); \ 667 } \ 668 } 669 CHIP_mem_set_multi_N(1,u_int8_t) 670 CHIP_mem_set_multi_N(2,u_int16_t) 671 CHIP_mem_set_multi_N(4,u_int32_t) 672 CHIP_mem_set_multi_N(8,u_int64_t) 673 674 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 675 void \ 676 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 677 void *v; \ 678 bus_space_handle_t h; \ 679 bus_size_t o, c; \ 680 TYPE val; \ 681 { \ 682 \ 683 while (c-- > 0) { \ 684 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 685 o += sizeof val; \ 686 } \ 687 } 688 CHIP_mem_set_region_N(1,u_int8_t) 689 CHIP_mem_set_region_N(2,u_int16_t) 690 CHIP_mem_set_region_N(4,u_int32_t) 691 CHIP_mem_set_region_N(8,u_int64_t) 692 693 #define CHIP_mem_copy_region_N(BYTES) \ 694 void \ 695 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 696 void *v; \ 697 bus_space_handle_t h1, h2; \ 698 bus_size_t o1, o2, c; \ 699 { \ 700 bus_size_t o; \ 701 \ 702 if ((h1 + o1) >= (h2 + o2)) { \ 703 /* src after dest: copy forward */ \ 704 for (o = 0; c != 0; c--, o += BYTES) { \ 705 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 706 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 707 } \ 708 } else { \ 709 /* dest after src: copy backwards */ \ 710 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 711 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 712 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 713 } \ 714 } \ 715 } 716 CHIP_mem_copy_region_N(1) 717 CHIP_mem_copy_region_N(2) 718 CHIP_mem_copy_region_N(4) 719 CHIP_mem_copy_region_N(8) 720
Indexes created Tue Oct 28 12:10:06 GMT 2025