pci_bwx_bus_mem_chipdep.c revision 1.6
1 /* $NetBSD: pci_bwx_bus_mem_chipdep.c,v 1.6 1999/12/02 19:44:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_MEM_BASE Mem space base to use. 74 * CHIP_MEM_EX_STORE 75 * If defined, device-provided static storage area 76 * for the memory space extent. If this is 77 * defined, CHIP_MEM_EX_STORE_SIZE must also be 78 * defined. If this is not defined, a static area 79 * will be declared. 80 * CHIP_MEM_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #include <machine/bwx.h> 88 89 #define __C(A,B) __CONCAT(A,B) 90 #define __S(S) __STRING(S) 91 92 /* mapping/unmapping */ 93 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 94 bus_space_handle_t *, int)); 95 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 96 bus_size_t, int)); 97 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 98 bus_size_t, bus_size_t, bus_space_handle_t *)); 99 100 /* allocation/deallocation */ 101 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 102 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 103 bus_space_handle_t *)); 104 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 105 bus_size_t)); 106 107 /* barrier */ 108 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 109 bus_size_t, bus_size_t, int)); 110 111 /* read (single) */ 112 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 119 bus_size_t)); 120 121 /* read multiple */ 122 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int8_t *, bus_size_t)); 124 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int16_t *, bus_size_t)); 126 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int32_t *, bus_size_t)); 128 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 129 bus_size_t, u_int64_t *, bus_size_t)); 130 131 /* read region */ 132 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int8_t *, bus_size_t)); 134 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int16_t *, bus_size_t)); 136 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int32_t *, bus_size_t)); 138 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int64_t *, bus_size_t)); 140 141 /* write (single) */ 142 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int8_t)); 144 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int16_t)); 146 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int32_t)); 148 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 149 bus_size_t, u_int64_t)); 150 151 /* write multiple */ 152 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int8_t *, bus_size_t)); 154 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int16_t *, bus_size_t)); 156 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int32_t *, bus_size_t)); 158 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 159 bus_size_t, const u_int64_t *, bus_size_t)); 160 161 /* write region */ 162 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int8_t *, bus_size_t)); 164 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int16_t *, bus_size_t)); 166 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int32_t *, bus_size_t)); 168 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 169 bus_size_t, const u_int64_t *, bus_size_t)); 170 171 /* set multiple */ 172 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int8_t, bus_size_t)); 174 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int16_t, bus_size_t)); 176 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int32_t, bus_size_t)); 178 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 179 bus_size_t, u_int64_t, bus_size_t)); 180 181 /* set region */ 182 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int8_t, bus_size_t)); 184 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int16_t, bus_size_t)); 186 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int32_t, bus_size_t)); 188 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 189 bus_size_t, u_int64_t, bus_size_t)); 190 191 /* copy */ 192 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 199 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 200 201 #ifndef CHIP_MEM_EX_STORE 202 static long 203 __C(CHIP,_mem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 204 #define CHIP_MEM_EX_STORE(v) (__C(CHIP,_mem_ex_storage)) 205 #define CHIP_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_mem_ex_storage)) 206 #endif 207 208 void 209 __C(CHIP,_bus_mem_init)(t, v) 210 bus_space_tag_t t; 211 void *v; 212 { 213 struct extent *ex; 214 215 /* 216 * Initialize the bus space tag. 217 */ 218 219 /* cookie */ 220 t->abs_cookie = v; 221 222 /* mapping/unmapping */ 223 t->abs_map = __C(CHIP,_mem_map); 224 t->abs_unmap = __C(CHIP,_mem_unmap); 225 t->abs_subregion = __C(CHIP,_mem_subregion); 226 227 /* allocation/deallocation */ 228 t->abs_alloc = __C(CHIP,_mem_alloc); 229 t->abs_free = __C(CHIP,_mem_free); 230 231 /* barrier */ 232 t->abs_barrier = __C(CHIP,_mem_barrier); 233 234 /* read (single) */ 235 t->abs_r_1 = __C(CHIP,_mem_read_1); 236 t->abs_r_2 = __C(CHIP,_mem_read_2); 237 t->abs_r_4 = __C(CHIP,_mem_read_4); 238 t->abs_r_8 = __C(CHIP,_mem_read_8); 239 240 /* read multiple */ 241 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 242 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 243 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 244 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 245 246 /* read region */ 247 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 248 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 249 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 250 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 251 252 /* write (single) */ 253 t->abs_w_1 = __C(CHIP,_mem_write_1); 254 t->abs_w_2 = __C(CHIP,_mem_write_2); 255 t->abs_w_4 = __C(CHIP,_mem_write_4); 256 t->abs_w_8 = __C(CHIP,_mem_write_8); 257 258 /* write multiple */ 259 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 260 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 261 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 262 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 263 264 /* write region */ 265 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 266 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 267 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 268 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 269 270 /* set multiple */ 271 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 272 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 273 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 274 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 275 276 /* set region */ 277 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 278 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 279 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 280 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 281 282 /* copy */ 283 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 284 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 285 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 286 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 287 288 ex = extent_create(__S(__C(CHIP,_bus_mem)), 0x0UL, 0xffffffffUL, 289 M_DEVBUF, (caddr_t)CHIP_MEM_EX_STORE(v), CHIP_MEM_EX_STORE_SIZE(v), 290 EX_NOWAIT|EX_NOCOALESCE); 291 292 CHIP_MEM_EXTENT(v) = ex; 293 } 294 295 int 296 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 297 void *v; 298 bus_addr_t memaddr; 299 bus_size_t memsize; 300 int flags; 301 bus_space_handle_t *memhp; 302 int acct; 303 { 304 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 305 int linear = flags & BUS_SPACE_MAP_LINEAR; 306 int error; 307 308 /* Requests for linear uncacheable space can't be satisfied. */ 309 if (linear && !cacheable) 310 return (EOPNOTSUPP); 311 312 if (acct == 0) 313 goto mapit; 314 315 #ifdef EXTENT_DEBUG 316 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 317 memaddr + memsize - 1); 318 #endif 319 error = extent_alloc_region(CHIP_MEM_EXTENT(v), memaddr, memsize, 320 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 321 if (error) { 322 #ifdef EXTENT_DEBUG 323 printf("mem: allocation failed (%d)\n", error); 324 extent_print(CHIP_MEM_EXTENT(v)); 325 #endif 326 return (error); 327 } 328 329 mapit: 330 *memhp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 331 332 return (0); 333 } 334 335 void 336 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 337 void *v; 338 bus_space_handle_t memh; 339 bus_size_t memsize; 340 int acct; 341 { 342 bus_addr_t memaddr; 343 int error; 344 345 if (acct == 0) 346 return; 347 348 #ifdef EXTENT_DEBUG 349 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 350 #endif 351 352 memaddr = memh - ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)); 353 354 #ifdef EXTENT_DEBUG 355 printf("mem: freeing 0x%lx to 0x%lx\n", memaddr, memaddr + memsize - 1); 356 #endif 357 358 error = extent_free(CHIP_MEM_EXTENT(v), memaddr, memsize, 359 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 360 if (error) { 361 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 362 __S(__C(CHIP,_mem_unmap)), memaddr, memaddr + memsize - 1, 363 error); 364 #ifdef EXTENT_DEBUG 365 extent_print(CHIP_MEM_EXTENT(v)); 366 #endif 367 } 368 } 369 370 int 371 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 372 void *v; 373 bus_space_handle_t memh, *nmemh; 374 bus_size_t offset, size; 375 { 376 377 *nmemh = memh + offset; 378 return (0); 379 } 380 381 int 382 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 383 addrp, bshp) 384 void *v; 385 bus_addr_t rstart, rend, *addrp; 386 bus_size_t size, align, boundary; 387 int flags; 388 bus_space_handle_t *bshp; 389 { 390 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 391 int linear = flags & BUS_SPACE_MAP_LINEAR; 392 bus_addr_t memaddr; 393 int error; 394 395 /* Requests for linear uncacheable space can't be satisfied. */ 396 if (linear && !cacheable) 397 return (EOPNOTSUPP); 398 399 /* 400 * Do the requested allocation. 401 */ 402 #ifdef EXTENT_DEBUG 403 printf("mem: allocating from 0x%lx to 0x%lx\n", rstart, rend); 404 #endif 405 error = extent_alloc_subregion(CHIP_MEM_EXTENT(v), rstart, rend, 406 size, align, boundary, 407 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 408 &memaddr); 409 if (error) { 410 #ifdef EXTENT_DEBUG 411 printf("mem: allocation failed (%d)\n", error); 412 extent_print(CHIP_MEM_EXTENT(v)); 413 #endif 414 } 415 416 #ifdef EXTENT_DEBUG 417 printf("mem: allocated 0x%lx to 0x%lx\n", memaddr, memaddr + size - 1); 418 #endif 419 420 *addrp = memaddr; 421 *bshp = ALPHA_PHYS_TO_K0SEG(CHIP_MEM_SYS_START(v)) + memaddr; 422 423 return (0); 424 } 425 426 void 427 __C(CHIP,_mem_free)(v, bsh, size) 428 void *v; 429 bus_space_handle_t bsh; 430 bus_size_t size; 431 { 432 433 /* Unmap does all we need to do. */ 434 __C(CHIP,_mem_unmap)(v, bsh, size, 1); 435 } 436 437 inline void 438 __C(CHIP,_mem_barrier)(v, h, o, l, f) 439 void *v; 440 bus_space_handle_t h; 441 bus_size_t o, l; 442 int f; 443 { 444 445 if ((f & BUS_SPACE_BARRIER_READ) != 0) 446 alpha_mb(); 447 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 448 alpha_wmb(); 449 } 450 451 inline u_int8_t 452 __C(CHIP,_mem_read_1)(v, memh, off) 453 void *v; 454 bus_space_handle_t memh; 455 bus_size_t off; 456 { 457 bus_addr_t addr; 458 459 addr = memh + off; 460 alpha_mb(); 461 return (alpha_ldbu((u_int8_t *)addr)); 462 } 463 464 inline u_int16_t 465 __C(CHIP,_mem_read_2)(v, memh, off) 466 void *v; 467 bus_space_handle_t memh; 468 bus_size_t off; 469 { 470 bus_addr_t addr; 471 472 addr = memh + off; 473 #ifdef DIAGNOSTIC 474 if (addr & 1) 475 panic(__S(__C(CHIP,_mem_read_2)) ": addr 0x%lx not aligned", 476 addr); 477 #endif 478 alpha_mb(); 479 return (alpha_ldwu((u_int16_t *)addr)); 480 } 481 482 inline u_int32_t 483 __C(CHIP,_mem_read_4)(v, memh, off) 484 void *v; 485 bus_space_handle_t memh; 486 bus_size_t off; 487 { 488 bus_addr_t addr; 489 490 addr = memh + off; 491 #ifdef DIAGNOSTIC 492 if (addr & 3) 493 panic(__S(__C(CHIP,_mem_read_4)) ": addr 0x%lx not aligned", 494 addr); 495 #endif 496 alpha_mb(); 497 return (*(u_int32_t *)addr); 498 } 499 500 inline u_int64_t 501 __C(CHIP,_mem_read_8)(v, memh, off) 502 void *v; 503 bus_space_handle_t memh; 504 bus_size_t off; 505 { 506 507 alpha_mb(); 508 509 /* XXX XXX XXX */ 510 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 511 } 512 513 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 514 void \ 515 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 516 void *v; \ 517 bus_space_handle_t h; \ 518 bus_size_t o, c; \ 519 TYPE *a; \ 520 { \ 521 \ 522 while (c-- > 0) { \ 523 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 524 BUS_SPACE_BARRIER_READ); \ 525 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 526 } \ 527 } 528 CHIP_mem_read_multi_N(1,u_int8_t) 529 CHIP_mem_read_multi_N(2,u_int16_t) 530 CHIP_mem_read_multi_N(4,u_int32_t) 531 CHIP_mem_read_multi_N(8,u_int64_t) 532 533 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 534 void \ 535 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 536 void *v; \ 537 bus_space_handle_t h; \ 538 bus_size_t o, c; \ 539 TYPE *a; \ 540 { \ 541 \ 542 while (c-- > 0) { \ 543 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 544 o += sizeof *a; \ 545 } \ 546 } 547 CHIP_mem_read_region_N(1,u_int8_t) 548 CHIP_mem_read_region_N(2,u_int16_t) 549 CHIP_mem_read_region_N(4,u_int32_t) 550 CHIP_mem_read_region_N(8,u_int64_t) 551 552 inline void 553 __C(CHIP,_mem_write_1)(v, memh, off, val) 554 void *v; 555 bus_space_handle_t memh; 556 bus_size_t off; 557 u_int8_t val; 558 { 559 bus_addr_t addr; 560 561 addr = memh + off; 562 alpha_stb((u_int8_t *)addr, val); 563 alpha_mb(); 564 } 565 566 inline void 567 __C(CHIP,_mem_write_2)(v, memh, off, val) 568 void *v; 569 bus_space_handle_t memh; 570 bus_size_t off; 571 u_int16_t val; 572 { 573 bus_addr_t addr; 574 575 addr = memh + off; 576 #ifdef DIAGNOSTIC 577 if (addr & 1) 578 panic(__S(__C(CHIP,_mem_write_2)) ": addr 0x%lx not aligned", 579 addr); 580 #endif 581 alpha_stw((u_int16_t *)addr, val); 582 alpha_mb(); 583 } 584 585 inline void 586 __C(CHIP,_mem_write_4)(v, memh, off, val) 587 void *v; 588 bus_space_handle_t memh; 589 bus_size_t off; 590 u_int32_t val; 591 { 592 bus_addr_t addr; 593 594 addr = memh + off; 595 #ifdef DIAGNOSTIC 596 if (addr & 3) 597 panic(__S(__C(CHIP,_mem_write_4)) ": addr 0x%lx not aligned", 598 addr); 599 #endif 600 *(u_int32_t *)addr = val; 601 alpha_mb(); 602 } 603 604 inline void 605 __C(CHIP,_mem_write_8)(v, memh, off, val) 606 void *v; 607 bus_space_handle_t memh; 608 bus_size_t off; 609 u_int64_t val; 610 { 611 612 /* XXX XXX XXX */ 613 panic("%s not implemented", __S(__C(CHIP,_mem_write_8))); 614 alpha_mb(); 615 } 616 617 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 618 void \ 619 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 620 void *v; \ 621 bus_space_handle_t h; \ 622 bus_size_t o, c; \ 623 const TYPE *a; \ 624 { \ 625 \ 626 while (c-- > 0) { \ 627 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 628 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 629 BUS_SPACE_BARRIER_WRITE); \ 630 } \ 631 } 632 CHIP_mem_write_multi_N(1,u_int8_t) 633 CHIP_mem_write_multi_N(2,u_int16_t) 634 CHIP_mem_write_multi_N(4,u_int32_t) 635 CHIP_mem_write_multi_N(8,u_int64_t) 636 637 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 638 void \ 639 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 640 void *v; \ 641 bus_space_handle_t h; \ 642 bus_size_t o, c; \ 643 const TYPE *a; \ 644 { \ 645 \ 646 while (c-- > 0) { \ 647 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 648 o += sizeof *a; \ 649 } \ 650 } 651 CHIP_mem_write_region_N(1,u_int8_t) 652 CHIP_mem_write_region_N(2,u_int16_t) 653 CHIP_mem_write_region_N(4,u_int32_t) 654 CHIP_mem_write_region_N(8,u_int64_t) 655 656 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 657 void \ 658 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 659 void *v; \ 660 bus_space_handle_t h; \ 661 bus_size_t o, c; \ 662 TYPE val; \ 663 { \ 664 \ 665 while (c-- > 0) { \ 666 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 667 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 668 BUS_SPACE_BARRIER_WRITE); \ 669 } \ 670 } 671 CHIP_mem_set_multi_N(1,u_int8_t) 672 CHIP_mem_set_multi_N(2,u_int16_t) 673 CHIP_mem_set_multi_N(4,u_int32_t) 674 CHIP_mem_set_multi_N(8,u_int64_t) 675 676 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 677 void \ 678 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 679 void *v; \ 680 bus_space_handle_t h; \ 681 bus_size_t o, c; \ 682 TYPE val; \ 683 { \ 684 \ 685 while (c-- > 0) { \ 686 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 687 o += sizeof val; \ 688 } \ 689 } 690 CHIP_mem_set_region_N(1,u_int8_t) 691 CHIP_mem_set_region_N(2,u_int16_t) 692 CHIP_mem_set_region_N(4,u_int32_t) 693 CHIP_mem_set_region_N(8,u_int64_t) 694 695 #define CHIP_mem_copy_region_N(BYTES) \ 696 void \ 697 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 698 void *v; \ 699 bus_space_handle_t h1, h2; \ 700 bus_size_t o1, o2, c; \ 701 { \ 702 bus_size_t o; \ 703 \ 704 if ((h1 + o1) >= (h2 + o2)) { \ 705 /* src after dest: copy forward */ \ 706 for (o = 0; c != 0; c--, o += BYTES) { \ 707 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 708 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 709 } \ 710 } else { \ 711 /* dest after src: copy backwards */ \ 712 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 713 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 714 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 715 } \ 716 } \ 717 } 718 CHIP_mem_copy_region_N(1) 719 CHIP_mem_copy_region_N(2) 720 CHIP_mem_copy_region_N(4) 721 CHIP_mem_copy_region_N(8) 722
Indexes created Tue Oct 28 12:10:06 GMT 2025