pci_eb66.c revision 1.28
1 /* $NetBSD: pci_eb66.c,v 1.28 2021/07/04 22:36:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb66.c,v 1.28 2021/07/04 22:36:43 thorpej Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/rpb.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 79 #include <alpha/pci/lcareg.h> 80 #include <alpha/pci/lcavar.h> 81 82 #include "sio.h" 83 #if NSIO 84 #include <alpha/pci/siovar.h> 85 #endif 86 87 #define EB66_MAX_IRQ 32 88 #define PCI_STRAY_MAX 5 89 90 static bus_space_tag_t eb66_intrgate_iot; 91 static bus_space_handle_t eb66_intrgate_ioh; 92 93 /* See pci_eb66_intr.s */ 94 extern void eb66_intr_enable(pci_chipset_tag_t pc, int irq); 95 extern void eb66_intr_disable(pci_chipset_tag_t pc, int irq); 96 97 static void 98 pci_eb66_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 99 pci_chipset_tag_t pc) 100 { 101 int i; 102 103 pc->pc_intr_v = core; 104 pc->pc_intr_map = alpha_pci_generic_intr_map; 105 pc->pc_intr_string = alpha_pci_generic_intr_string; 106 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 107 pc->pc_intr_establish = alpha_pci_generic_intr_establish; 108 pc->pc_intr_disestablish = alpha_pci_generic_intr_disestablish; 109 110 /* Not supported on the EB66. */ 111 pc->pc_pciide_compat_intr_establish = NULL; 112 113 eb66_intrgate_iot = iot; 114 if (bus_space_map(eb66_intrgate_iot, 0x804, 3, 0, 115 &eb66_intrgate_ioh) != 0) 116 panic("pci_eb66_pickintr: couldn't map interrupt PLD"); 117 118 pc->pc_intr_desc = "eb66"; 119 pc->pc_vecbase = 0x900; 120 pc->pc_nirq = EB66_MAX_IRQ; 121 122 pc->pc_intr_enable = eb66_intr_enable; 123 pc->pc_intr_disable = eb66_intr_disable; 124 125 for (i = 0; i < EB66_MAX_IRQ; i++) { 126 eb66_intr_disable(pc, i); 127 } 128 129 alpha_pci_intr_alloc(pc, PCI_STRAY_MAX); 130 131 #if NSIO 132 sio_intr_setup(pc, iot); 133 #endif 134 } 135 ALPHA_PCI_INTR_INIT(ST_EB66, pci_eb66_pickintr) 136 137 #if 0 /* THIS DOES NOT WORK! see pci_eb66_intr.S. */ 138 uint8_t eb66_intr_mask[3] = { 0xff, 0xff, 0xff }; 139 140 void 141 eb66_intr_enable(pci_chipset_tag_t pc, __unused, int irq) 142 { 143 int byte = (irq / 8), bit = (irq % 8); 144 145 #if 1 146 printf("eb66_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 147 #endif 148 eb66_intr_mask[byte] &= ~(1 << bit); 149 150 bus_space_write_1(eb66_intrgate_iot, eb66_intrgate_ioh, byte, 151 eb66_intr_mask[byte]); 152 } 153 154 void 155 eb66_intr_disable(pci_chipset_tag_t pc, __unused, int irq) 156 { 157 int byte = (irq / 8), bit = (irq % 8); 158 159 #if 1 160 printf("eb66_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 161 #endif 162 eb66_intr_mask[byte] |= (1 << bit); 163 164 bus_space_write_1(eb66_intrgate_iot, eb66_intrgate_ioh, byte, 165 eb66_intr_mask[byte]); 166 } 167 #endif 168
Indexes created Tue Sep 30 11:09:46 GMT 2025