pci_eb66.c revision 1.7
1 /* $NetBSD: pci_eb66.c,v 1.7 2000/06/05 21:47:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb66.c,v 1.7 2000/06/05 21:47:26 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 87 #include <alpha/pci/lcareg.h> 88 #include <alpha/pci/lcavar.h> 89 90 #include <alpha/pci/pci_eb66.h> 91 92 #include "sio.h" 93 #if NSIO 94 #include <alpha/pci/siovar.h> 95 #endif 96 97 int dec_eb66_intr_map __P((void *, pcitag_t, int, int, 98 pci_intr_handle_t *)); 99 const char *dec_eb66_intr_string __P((void *, pci_intr_handle_t)); 100 const struct evcnt *dec_eb66_intr_evcnt __P((void *, pci_intr_handle_t)); 101 void *dec_eb66_intr_establish __P((void *, pci_intr_handle_t, 102 int, int (*func)(void *), void *)); 103 void dec_eb66_intr_disestablish __P((void *, void *)); 104 105 #define EB66_MAX_IRQ 32 106 #define PCI_STRAY_MAX 5 107 108 struct alpha_shared_intr *eb66_pci_intr; 109 110 bus_space_tag_t eb66_intrgate_iot; 111 bus_space_handle_t eb66_intrgate_ioh; 112 113 void eb66_iointr __P((void *framep, unsigned long vec)); 114 extern void eb66_intr_enable __P((int irq)); /* pci_eb66_intr.S */ 115 extern void eb66_intr_disable __P((int irq)); /* pci_eb66_intr.S */ 116 117 void 118 pci_eb66_pickintr(lcp) 119 struct lca_config *lcp; 120 { 121 bus_space_tag_t iot = &lcp->lc_iot; 122 pci_chipset_tag_t pc = &lcp->lc_pc; 123 char *cp; 124 int i; 125 126 pc->pc_intr_v = lcp; 127 pc->pc_intr_map = dec_eb66_intr_map; 128 pc->pc_intr_string = dec_eb66_intr_string; 129 pc->pc_intr_evcnt = dec_eb66_intr_evcnt; 130 pc->pc_intr_establish = dec_eb66_intr_establish; 131 pc->pc_intr_disestablish = dec_eb66_intr_disestablish; 132 133 /* Not supported on the EB66. */ 134 pc->pc_pciide_compat_intr_establish = NULL; 135 136 eb66_intrgate_iot = iot; 137 if (bus_space_map(eb66_intrgate_iot, 0x804, 3, 0, 138 &eb66_intrgate_ioh) != 0) 139 panic("pci_eb66_pickintr: couldn't map interrupt PLD"); 140 for (i = 0; i < EB66_MAX_IRQ; i++) 141 eb66_intr_disable(i); 142 143 eb66_pci_intr = alpha_shared_intr_alloc(EB66_MAX_IRQ, 8); 144 for (i = 0; i < EB66_MAX_IRQ; i++) { 145 alpha_shared_intr_set_maxstrays(eb66_pci_intr, i, 146 PCI_STRAY_MAX); 147 148 cp = alpha_shared_intr_string(eb66_pci_intr, i); 149 sprintf(cp, "irq %d", i); 150 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 151 eb66_pci_intr, i), EVCNT_TYPE_INTR, NULL, 152 "eb66", cp); 153 } 154 155 #if NSIO 156 sio_intr_setup(pc, iot); 157 #endif 158 159 set_iointr(eb66_iointr); 160 } 161 162 int 163 dec_eb66_intr_map(lcv, bustag, buspin, line, ihp) 164 void *lcv; 165 pcitag_t bustag; 166 int buspin, line; 167 pci_intr_handle_t *ihp; 168 { 169 struct lca_config *lcp = lcv; 170 pci_chipset_tag_t pc = &lcp->lc_pc; 171 int bus, device, function; 172 173 if (buspin == 0) { 174 /* No IRQ used. */ 175 return 1; 176 } 177 if (buspin > 4) { 178 printf("dec_eb66_intr_map: bad interrupt pin %d\n", buspin); 179 return 1; 180 } 181 182 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 183 184 /* 185 * The console places the interrupt mapping in the "line" value. 186 * A value of (char)-1 indicates there is no mapping. 187 */ 188 if (line == 0xff) { 189 printf("dec_eb66_intr_map: no mapping for %d/%d/%d\n", 190 bus, device, function); 191 return (1); 192 } 193 194 if (line >= EB66_MAX_IRQ) 195 panic("dec_eb66_intr_map: eb66 irq too large (%d)\n", 196 line); 197 198 *ihp = line; 199 return (0); 200 } 201 202 const char * 203 dec_eb66_intr_string(lcv, ih) 204 void *lcv; 205 pci_intr_handle_t ih; 206 { 207 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 208 209 if (ih >= EB66_MAX_IRQ) 210 panic("dec_eb66_intr_string: bogus eb66 IRQ 0x%lx\n", ih); 211 sprintf(irqstr, "eb66 irq %ld", ih); 212 return (irqstr); 213 } 214 215 const struct evcnt * 216 dec_eb66_intr_evcnt(lcv, ih) 217 void *lcv; 218 pci_intr_handle_t ih; 219 { 220 221 if (ih >= EB66_MAX_IRQ) 222 panic("dec_eb66_intr_string: bogus eb66 IRQ 0x%lx\n", ih); 223 return (alpha_shared_intr_evcnt(eb66_pci_intr, ih)); 224 } 225 226 void * 227 dec_eb66_intr_establish(lcv, ih, level, func, arg) 228 void *lcv, *arg; 229 pci_intr_handle_t ih; 230 int level; 231 int (*func) __P((void *)); 232 { 233 void *cookie; 234 235 if (ih >= EB66_MAX_IRQ) 236 panic("dec_eb66_intr_establish: bogus eb66 IRQ 0x%lx\n", ih); 237 238 cookie = alpha_shared_intr_establish(eb66_pci_intr, ih, IST_LEVEL, 239 level, func, arg, "eb66 irq"); 240 241 if (cookie != NULL && alpha_shared_intr_isactive(eb66_pci_intr, ih)) 242 eb66_intr_enable(ih); 243 return (cookie); 244 } 245 246 void 247 dec_eb66_intr_disestablish(lcv, cookie) 248 void *lcv, *cookie; 249 { 250 struct alpha_shared_intrhand *ih = cookie; 251 unsigned int irq = ih->ih_num; 252 int s; 253 254 s = splhigh(); 255 256 alpha_shared_intr_disestablish(eb66_pci_intr, cookie, 257 "eb66 irq"); 258 if (alpha_shared_intr_isactive(eb66_pci_intr, irq) == 0) { 259 eb66_intr_disable(irq); 260 alpha_shared_intr_set_dfltsharetype(eb66_pci_intr, irq, 261 IST_NONE); 262 } 263 264 splx(s); 265 } 266 267 void 268 eb66_iointr(framep, vec) 269 void *framep; 270 unsigned long vec; 271 { 272 int irq; 273 274 if (vec >= 0x900) { 275 if (vec >= 0x900 + (EB66_MAX_IRQ << 4)) 276 panic("eb66_iointr: vec 0x%lx out of range\n", vec); 277 irq = (vec - 0x900) >> 4; 278 279 if (!alpha_shared_intr_dispatch(eb66_pci_intr, irq)) { 280 alpha_shared_intr_stray(eb66_pci_intr, irq, 281 "eb66 irq"); 282 if (ALPHA_SHARED_INTR_DISABLE(eb66_pci_intr, irq)) 283 eb66_intr_disable(irq); 284 } 285 return; 286 } 287 #if NSIO 288 if (vec >= 0x800) { 289 sio_iointr(framep, vec); 290 return; 291 } 292 #endif 293 panic("eb66_iointr: weird vec 0x%lx\n", vec); 294 } 295 296 #if 0 /* THIS DOES NOT WORK! see pci_eb66_intr.S. */ 297 u_int8_t eb66_intr_mask[3] = { 0xff, 0xff, 0xff }; 298 299 void 300 eb66_intr_enable(irq) 301 int irq; 302 { 303 int byte = (irq / 8), bit = (irq % 8); 304 305 #if 1 306 printf("eb66_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 307 #endif 308 eb66_intr_mask[byte] &= ~(1 << bit); 309 310 bus_space_write_1(eb66_intrgate_iot, eb66_intrgate_ioh, byte, 311 eb66_intr_mask[byte]); 312 } 313 314 void 315 eb66_intr_disable(irq) 316 int irq; 317 { 318 int byte = (irq / 8), bit = (irq % 8); 319 320 #if 1 321 printf("eb66_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 322 #endif 323 eb66_intr_mask[byte] |= (1 << bit); 324 325 bus_space_write_1(eb66_intrgate_iot, eb66_intrgate_ioh, byte, 326 eb66_intr_mask[byte]); 327 } 328 #endif 329
Indexes created Sun Sep 28 16:09:52 GMT 2025