pci_kn8ae.c revision 1.1 1 1.1 cgd /* $NetBSD: pci_kn8ae.c,v 1.1 1997/03/12 19:20:06 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.1 cgd * Copyright (c) 1997
5 1.1 cgd * Matthew Jacob
6 1.1 cgd * NASA AMES Research Center.
7 1.1 cgd * All rights reserved.
8 1.1 cgd *
9 1.1 cgd * Redistribution and use in source and binary forms, with or without
10 1.1 cgd * modification, are permitted provided that the following conditions
11 1.1 cgd * are met:
12 1.1 cgd * 1. Redistributions of source code must retain the above copyright
13 1.1 cgd * notice immediately at the beginning of the file, without modification,
14 1.1 cgd * this list of conditions, and the following disclaimer.
15 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 cgd * notice, this list of conditions and the following disclaimer in the
17 1.1 cgd * documentation and/or other materials provided with the distribution.
18 1.1 cgd * 3. The name of the author may not be used to endorse or promote products
19 1.1 cgd * derived from this software without specific prior written permission.
20 1.1 cgd *
21 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 1.1 cgd * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 1.1 cgd * SUCH DAMAGE.
32 1.1 cgd */
33 1.1 cgd
34 1.1 cgd #include <sys/types.h>
35 1.1 cgd #include <sys/param.h>
36 1.1 cgd #include <sys/time.h>
37 1.1 cgd #include <sys/systm.h>
38 1.1 cgd #include <sys/errno.h>
39 1.1 cgd #include <sys/malloc.h>
40 1.1 cgd #include <sys/device.h>
41 1.1 cgd #include <sys/syslog.h>
42 1.1 cgd
43 1.1 cgd #include <vm/vm.h>
44 1.1 cgd
45 1.1 cgd #include <machine/autoconf.h>
46 1.1 cgd
47 1.1 cgd #include <dev/pci/pcireg.h>
48 1.1 cgd #include <dev/pci/pcivar.h>
49 1.1 cgd
50 1.1 cgd #include <alpha/pci/dwlpxreg.h>
51 1.1 cgd #include <alpha/pci/dwlpxvar.h>
52 1.1 cgd #include <alpha/pci/pci_kn8ae.h>
53 1.1 cgd
54 1.1 cgd #ifndef EVCNT_COUNTERS
55 1.1 cgd #include <machine/intrcnt.h>
56 1.1 cgd #endif
57 1.1 cgd
58 1.1 cgd int dec_kn8ae_intr_map __P((void *, pcitag_t, int, int,
59 1.1 cgd pci_intr_handle_t *));
60 1.1 cgd const char *dec_kn8ae_intr_string __P((void *, pci_intr_handle_t));
61 1.1 cgd void *dec_kn8ae_intr_establish __P((void *, pci_intr_handle_t,
62 1.1 cgd int, int (*func)(void *), void *));
63 1.1 cgd void dec_kn8ae_intr_disestablish __P((void *, void *));
64 1.1 cgd
65 1.1 cgd #define NIONODE 5
66 1.1 cgd #define NHOSE 4
67 1.1 cgd struct vectab {
68 1.1 cgd int (*func) __P((void *));
69 1.1 cgd void *arg;
70 1.1 cgd } vectab[NIONODE][NHOSE][DWLPX_MAXDEV];
71 1.1 cgd static u_int32_t imaskcache[NIONODE][NHOSE][NHPC];
72 1.1 cgd
73 1.1 cgd #ifdef EVCNT_COUNTERS
74 1.1 cgd struct evcnt kn8ae_intr_evcnt;
75 1.1 cgd #endif
76 1.1 cgd
77 1.1 cgd int kn8ae_spurious __P((void *));
78 1.1 cgd void kn8ae_iointr __P((void *framep, unsigned long vec));
79 1.1 cgd void kn8ae_enadis_intr __P((pci_intr_handle_t, int));
80 1.1 cgd void kn8ae_enable_intr __P((pci_intr_handle_t irq));
81 1.1 cgd void kn8ae_disable_intr __P((pci_intr_handle_t irq));
82 1.1 cgd
83 1.1 cgd void
84 1.1 cgd pci_kn8ae_pickintr(ccp, first)
85 1.1 cgd struct dwlpx_config *ccp;
86 1.1 cgd int first;
87 1.1 cgd {
88 1.1 cgd int io, hose, dev;
89 1.1 cgd pci_chipset_tag_t pc = &ccp->cc_pc;
90 1.1 cgd
91 1.1 cgd pc->pc_intr_v = ccp;
92 1.1 cgd pc->pc_intr_map = dec_kn8ae_intr_map;
93 1.1 cgd pc->pc_intr_string = dec_kn8ae_intr_string;
94 1.1 cgd pc->pc_intr_establish = dec_kn8ae_intr_establish;
95 1.1 cgd pc->pc_intr_disestablish = dec_kn8ae_intr_disestablish;
96 1.1 cgd
97 1.1 cgd if (!first) {
98 1.1 cgd return;
99 1.1 cgd }
100 1.1 cgd
101 1.1 cgd for (io = 0; io < NIONODE; io++) {
102 1.1 cgd for (hose = 0; hose < NHOSE; hose++) {
103 1.1 cgd for (dev = 0; dev < DWLPX_MAXDEV; dev++) {
104 1.1 cgd vectab[io][hose][dev].func = kn8ae_spurious;
105 1.1 cgd vectab[io][hose][dev].arg = (void *)
106 1.1 cgd (u_int64_t) DWLPX_MVEC(io, hose, dev);
107 1.1 cgd }
108 1.1 cgd }
109 1.1 cgd }
110 1.1 cgd for (io = 0; io < NIONODE; io++) {
111 1.1 cgd for (hose = 0; hose < NHOSE; hose++) {
112 1.1 cgd for (dev = 0; dev < NHPC; dev++) {
113 1.1 cgd imaskcache[io][hose][dev] = DWLPX_IMASK_DFLT;
114 1.1 cgd }
115 1.1 cgd }
116 1.1 cgd }
117 1.1 cgd set_iointr(kn8ae_iointr);
118 1.1 cgd }
119 1.1 cgd
120 1.1 cgd int
121 1.1 cgd dec_kn8ae_intr_map(ccv, bustag, buspin, line, ihp)
122 1.1 cgd void *ccv;
123 1.1 cgd pcitag_t bustag;
124 1.1 cgd int buspin, line;
125 1.1 cgd pci_intr_handle_t *ihp;
126 1.1 cgd {
127 1.1 cgd int device, ionode, hose;
128 1.1 cgd struct dwlpx_config *ccp = ccv;
129 1.1 cgd pci_chipset_tag_t pc = &ccp->cc_pc;
130 1.1 cgd
131 1.1 cgd if (buspin == 0) {
132 1.1 cgd /* No IRQ used. */
133 1.1 cgd return 1;
134 1.1 cgd }
135 1.1 cgd if (buspin > 4) {
136 1.1 cgd printf("pci_map_int: bad interrupt pin %d\n", buspin);
137 1.1 cgd return 1;
138 1.1 cgd }
139 1.1 cgd pci_decompose_tag(pc, bustag, NULL, &device, NULL);
140 1.1 cgd ionode = ccp->cc_sc->dwlpx_node - 4;
141 1.1 cgd hose = ccp->cc_sc->dwlpx_hosenum;
142 1.1 cgd
143 1.1 cgd /*
144 1.1 cgd * handle layout:
145 1.1 cgd * bits 0..15 DWLPX_MVEC(ionode, hose, device)
146 1.1 cgd * bits 16-24 buspin (1..N)
147 1.1 cgd * bits 24-31 IPL
148 1.1 cgd */
149 1.1 cgd *ihp = DWLPX_MVEC(ionode, hose, device) | (buspin << 16) | (14 << 24);
150 1.1 cgd return (0);
151 1.1 cgd }
152 1.1 cgd
153 1.1 cgd const char *
154 1.1 cgd dec_kn8ae_intr_string(ccv, ih)
155 1.1 cgd void *ccv;
156 1.1 cgd pci_intr_handle_t ih;
157 1.1 cgd {
158 1.1 cgd static char irqstr[64];
159 1.1 cgd sprintf(irqstr, "kn8ae irq %d vector 0x%x PCI Interrupt Pin %c",
160 1.1 cgd (ih >> 24), ih & 0xffff, (((ih >> 16) & 0x7) - 1) + 'A');
161 1.1 cgd return (irqstr);
162 1.1 cgd }
163 1.1 cgd
164 1.1 cgd void *
165 1.1 cgd dec_kn8ae_intr_establish(ccv, ih, level, func, arg)
166 1.1 cgd void *ccv;
167 1.1 cgd pci_intr_handle_t ih;
168 1.1 cgd int level;
169 1.1 cgd int (*func) __P((void *));
170 1.1 cgd void *arg;
171 1.1 cgd {
172 1.1 cgd struct dwlpx_config *ccp = ccv;
173 1.1 cgd void *cookie = NULL;
174 1.1 cgd int ionode, hose, device, s;
175 1.1 cgd struct vectab *vp;
176 1.1 cgd
177 1.1 cgd ionode = ccp->cc_sc->dwlpx_node - 4;
178 1.1 cgd hose = ccp->cc_sc->dwlpx_hosenum;
179 1.1 cgd device = DWLPX_MVEC_PCISLOT(ih);
180 1.1 cgd
181 1.1 cgd if (ionode < 0 || ionode >= NIONODE) {
182 1.1 cgd panic("dec_kn8ae_intr_establish: bad ionode %d\n", ionode);
183 1.1 cgd }
184 1.1 cgd if (hose < 0 || hose >= NHOSE) {
185 1.1 cgd panic("dec_kn8ae_intr_establish: bad hose %d\n", hose);
186 1.1 cgd }
187 1.1 cgd if (device < 0 || device >= DWLPX_MAXDEV) {
188 1.1 cgd panic("dec_kn8ae_intr_establish: bad device %d\n", device);
189 1.1 cgd }
190 1.1 cgd
191 1.1 cgd vp = &vectab[ionode][hose][device];
192 1.1 cgd if (vp->func != kn8ae_spurious) {
193 1.1 cgd printf("dec_kn8ae_intr_establish: vector 0x%x already used\n",
194 1.1 cgd ih & 0xffff);
195 1.1 cgd return (cookie);
196 1.1 cgd }
197 1.1 cgd
198 1.1 cgd s = splhigh();
199 1.1 cgd vp->func = func;
200 1.1 cgd vp->arg = arg;
201 1.1 cgd (void) splx(s);
202 1.1 cgd kn8ae_enable_intr(ih);
203 1.1 cgd cookie = (void *) (u_int64_t) DWLPX_MVEC(ionode, hose, device);
204 1.1 cgd return (cookie);
205 1.1 cgd }
206 1.1 cgd
207 1.1 cgd void
208 1.1 cgd dec_kn8ae_intr_disestablish(ccv, cookie)
209 1.1 cgd void *ccv, *cookie;
210 1.1 cgd {
211 1.1 cgd int ionode, hose, device, s;
212 1.1 cgd struct vectab *vp;
213 1.1 cgd
214 1.1 cgd ionode = DWLPX_MVEC_IONODE(cookie);
215 1.1 cgd hose = DWLPX_MVEC_HOSE(cookie);
216 1.1 cgd device = DWLPX_MVEC_PCISLOT(cookie);
217 1.1 cgd if (ionode < 0 || ionode >= NIONODE || hose < 0 || hose >= NHOSE ||
218 1.1 cgd device < 0 || device >= DWLPX_MAXDEV) {
219 1.1 cgd return;
220 1.1 cgd }
221 1.1 cgd vp = &vectab[ionode][hose][device];
222 1.1 cgd s = splhigh();
223 1.1 cgd vp->func = kn8ae_spurious;
224 1.1 cgd vp->arg = cookie;
225 1.1 cgd (void) splx(s);
226 1.1 cgd }
227 1.1 cgd
228 1.1 cgd void
229 1.1 cgd kn8ae_iointr(framep, vec)
230 1.1 cgd void *framep;
231 1.1 cgd unsigned long vec;
232 1.1 cgd {
233 1.1 cgd struct vectab *vp;
234 1.1 cgd int ionode, hose, device;
235 1.1 cgd if ((vec & DWLPX_VEC_MARK) == 0) {
236 1.1 cgd panic("kn8ae_iointr: vec 0x%x\n", vec);
237 1.1 cgd }
238 1.1 cgd #ifdef EVCNT_COUNTERS
239 1.1 cgd kn8ae_intr_evcnt.ev_count++;
240 1.1 cgd #else
241 1.1 cgd ; /* XXX */
242 1.1 cgd #endif
243 1.1 cgd ionode = DWLPX_MVEC_IONODE(vec);
244 1.1 cgd hose = DWLPX_MVEC_HOSE(vec);
245 1.1 cgd device = DWLPX_MVEC_PCISLOT(vec);
246 1.1 cgd
247 1.1 cgd if (ionode < 0 || ionode >= NIONODE || hose < 0 || hose >= NHOSE ||
248 1.1 cgd device < 0 || device >= DWLPX_MAXDEV) {
249 1.1 cgd panic("kn8ae_iointr: malformed vector 0x%x\n", vec);
250 1.1 cgd }
251 1.1 cgd vp = &vectab[ionode][hose][device];
252 1.1 cgd if ((*vp->func)(vp->arg) == 0) {
253 1.1 cgd printf("kn8ae_iointr: TLSB Node %d Hose %d Slot %d - "
254 1.1 cgd " unclaimed interrupt\n", ionode + 4, hose, device);
255 1.1 cgd }
256 1.1 cgd }
257 1.1 cgd
258 1.1 cgd int
259 1.1 cgd kn8ae_spurious(arg)
260 1.1 cgd void *arg;
261 1.1 cgd {
262 1.1 cgd int ionode, hose, device;
263 1.1 cgd ionode = DWLPX_MVEC_IONODE(arg);
264 1.1 cgd hose = DWLPX_MVEC_HOSE(arg);
265 1.1 cgd device = DWLPX_MVEC_PCISLOT(arg);
266 1.1 cgd printf("Spurious Interrupt from TLSB Node %d Hose %d Slot %d\n",
267 1.1 cgd ionode + 4, hose, device);
268 1.1 cgd return (-1);
269 1.1 cgd }
270 1.1 cgd
271 1.1 cgd
272 1.1 cgd void
273 1.1 cgd kn8ae_enadis_intr(irq, onoff)
274 1.1 cgd pci_intr_handle_t irq;
275 1.1 cgd int onoff;
276 1.1 cgd {
277 1.1 cgd unsigned long paddr;
278 1.1 cgd u_int32_t val;
279 1.1 cgd int ionode, hose, device, hpc, busp, s;
280 1.1 cgd
281 1.1 cgd ionode = DWLPX_MVEC_IONODE(irq);
282 1.1 cgd hose = DWLPX_MVEC_HOSE(irq);
283 1.1 cgd device = DWLPX_MVEC_PCISLOT(irq);
284 1.1 cgd busp = 1 << (((irq >> 16) & 0xff) - 1);
285 1.1 cgd paddr = (1LL << 39);
286 1.1 cgd paddr |= (unsigned long) ionode << 36;
287 1.1 cgd paddr |= (unsigned long) hose << 34;
288 1.1 cgd if (device < 4) {
289 1.1 cgd hpc = 0;
290 1.1 cgd } else if (device < 8) {
291 1.1 cgd hpc = 1;
292 1.1 cgd device -= 4;
293 1.1 cgd } else {
294 1.1 cgd hpc = 2;
295 1.1 cgd device -= 8;
296 1.1 cgd }
297 1.1 cgd busp <<= (device << 2);
298 1.1 cgd val = imaskcache[ionode][hose][hpc];
299 1.1 cgd if (onoff)
300 1.1 cgd val |= busp;
301 1.1 cgd else
302 1.1 cgd val &= ~busp;
303 1.1 cgd imaskcache[ionode][hose][hpc] = val;
304 1.1 cgd #if 0
305 1.1 cgd printf("kn8ae_%s_intr: irq %lx imsk 0x%x hpc %d TLSB node %d hose %d\n",
306 1.1 cgd onoff? "enable" : "disable", irq, val, hpc, ionode + 4, hose);
307 1.1 cgd #endif
308 1.1 cgd s = splhigh();
309 1.1 cgd REGVAL(PCIA_IMASK(hpc) + paddr) = val;
310 1.1 cgd alpha_mb();
311 1.1 cgd (void) splx(s);
312 1.1 cgd }
313 1.1 cgd
314 1.1 cgd void
315 1.1 cgd kn8ae_enable_intr(irq)
316 1.1 cgd pci_intr_handle_t irq;
317 1.1 cgd {
318 1.1 cgd kn8ae_enadis_intr(irq, 1);
319 1.1 cgd }
320 1.1 cgd
321 1.1 cgd void
322 1.1 cgd kn8ae_disable_intr(irq)
323 1.1 cgd pci_intr_handle_t irq;
324 1.1 cgd {
325 1.1 cgd kn8ae_enadis_intr(irq, 0);
326 1.1 cgd }
327