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pci_machdep.c revision 1.1
      1  1.1  cgd /*	$NetBSD: pci_machdep.c,v 1.1 1995/06/28 01:25:56 cgd Exp $	*/
      2  1.1  cgd 
      3  1.1  cgd /*
      4  1.1  cgd  * Copyright (c) 1994 Charles Hannum.  All rights reserved.
      5  1.1  cgd  *
      6  1.1  cgd  * Redistribution and use in source and binary forms, with or without
      7  1.1  cgd  * modification, are permitted provided that the following conditions
      8  1.1  cgd  * are met:
      9  1.1  cgd  * 1. Redistributions of source code must retain the above copyright
     10  1.1  cgd  *    notice, this list of conditions and the following disclaimer.
     11  1.1  cgd  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.1  cgd  *    notice, this list of conditions and the following disclaimer in the
     13  1.1  cgd  *    documentation and/or other materials provided with the distribution.
     14  1.1  cgd  * 3. All advertising materials mentioning features or use of this software
     15  1.1  cgd  *    must display the following acknowledgement:
     16  1.1  cgd  *	This product includes software developed by Charles Hannum.
     17  1.1  cgd  * 4. The name of the author may not be used to endorse or promote products
     18  1.1  cgd  *    derived from this software without specific prior written permission.
     19  1.1  cgd  *
     20  1.1  cgd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  1.1  cgd  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  1.1  cgd  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  1.1  cgd  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  1.1  cgd  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  1.1  cgd  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  1.1  cgd  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  1.1  cgd  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  1.1  cgd  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  1.1  cgd  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  1.1  cgd  */
     31  1.1  cgd 
     32  1.1  cgd /*
     33  1.1  cgd  * Machine-specific functions for PCI autoconfiguration.
     34  1.1  cgd  */
     35  1.1  cgd 
     36  1.1  cgd #include <sys/types.h>
     37  1.1  cgd #include <sys/param.h>
     38  1.1  cgd #include <sys/time.h>
     39  1.1  cgd #include <sys/systm.h>
     40  1.1  cgd #include <sys/errno.h>
     41  1.1  cgd #include <sys/device.h>
     42  1.1  cgd 
     43  1.1  cgd #include <vm/vm.h>
     44  1.1  cgd 
     45  1.1  cgd #include <dev/isa/isavar.h>
     46  1.1  cgd #include <dev/pci/pcivar.h>
     47  1.1  cgd #include <dev/pci/pcireg.h>
     48  1.1  cgd #include <alpha/pci/pci_chipset.h>
     49  1.1  cgd 
     50  1.1  cgd int pcimatch __P((struct device *, void *, void *));
     51  1.1  cgd void pciattach __P((struct device *, struct device *, void *));
     52  1.1  cgd 
     53  1.1  cgd struct cfdriver pcicd = {
     54  1.1  cgd 	NULL, "pci", pcimatch, pciattach, DV_DULL, sizeof(struct device)
     55  1.1  cgd };
     56  1.1  cgd 
     57  1.1  cgd int
     58  1.1  cgd pcimatch(parent, match, aux)
     59  1.1  cgd 	struct device *parent;
     60  1.1  cgd 	void *match, *aux;
     61  1.1  cgd {
     62  1.1  cgd 
     63  1.1  cgd 	return 1;
     64  1.1  cgd }
     65  1.1  cgd 
     66  1.1  cgd void
     67  1.1  cgd pciattach(parent, self, aux)
     68  1.1  cgd 	struct device *parent, *self;
     69  1.1  cgd 	void *aux;
     70  1.1  cgd {
     71  1.1  cgd 
     72  1.1  cgd 	printf("\n");
     73  1.1  cgd 	(*pci_cs_fcns->cs_setup)();
     74  1.1  cgd 	(*pci_cfg_fcns->cfg_attach)(parent, self, aux);
     75  1.1  cgd }
     76  1.1  cgd 
     77  1.1  cgd pcitag_t
     78  1.1  cgd pci_make_tag(bus, device, function)
     79  1.1  cgd 	int bus, device, function;
     80  1.1  cgd {
     81  1.1  cgd 
     82  1.1  cgd 	return (*pci_cs_fcns->cs_make_tag)(bus, device, function);
     83  1.1  cgd }
     84  1.1  cgd 
     85  1.1  cgd pcireg_t
     86  1.1  cgd pci_conf_read(tag, offset)
     87  1.1  cgd 	pcitag_t tag;
     88  1.1  cgd 	int offset;					/* XXX */
     89  1.1  cgd {
     90  1.1  cgd 
     91  1.1  cgd 	return (*pci_cs_fcns->cs_conf_read)(tag, offset);
     92  1.1  cgd }
     93  1.1  cgd 
     94  1.1  cgd void
     95  1.1  cgd pci_conf_write(tag, offset, data)
     96  1.1  cgd 	pcitag_t tag;
     97  1.1  cgd 	int offset;					/* XXX */
     98  1.1  cgd 	pcireg_t data;
     99  1.1  cgd {
    100  1.1  cgd 
    101  1.1  cgd 	(*pci_cs_fcns->cs_conf_write)(tag, offset, data);
    102  1.1  cgd }
    103  1.1  cgd 
    104  1.1  cgd int
    105  1.1  cgd pci_map_io(tag, reg, iobasep)
    106  1.1  cgd 	pcitag_t tag;
    107  1.1  cgd 	int reg;
    108  1.1  cgd 	int *iobasep;
    109  1.1  cgd {
    110  1.1  cgd 
    111  1.1  cgd 	/*
    112  1.1  cgd 	 * XXX should be a chipset-dependent function, but...
    113  1.1  cgd 	 * what would it do, and what would use it?
    114  1.1  cgd 	 */
    115  1.1  cgd 	panic("pci_map_io: not implemented");
    116  1.1  cgd }
    117  1.1  cgd 
    118  1.1  cgd int
    119  1.1  cgd pci_map_mem(tag, reg, vap, pap)
    120  1.1  cgd 	pcitag_t tag;
    121  1.1  cgd 	int reg;
    122  1.1  cgd 	vm_offset_t *vap, *pap;
    123  1.1  cgd {
    124  1.1  cgd 
    125  1.1  cgd 	return (*pci_cs_fcns->cs_map_mem)(tag, reg, vap, pap);
    126  1.1  cgd }
    127  1.1  cgd 
    128  1.1  cgd int
    129  1.1  cgd pcidma_map(addr, size, mappings)
    130  1.1  cgd 	caddr_t addr;
    131  1.1  cgd 	vm_size_t size;
    132  1.1  cgd 	vm_offset_t *mappings;
    133  1.1  cgd {
    134  1.1  cgd 
    135  1.1  cgd 	return (*pci_cs_fcns->cs_pcidma_map)(addr, size, mappings);
    136  1.1  cgd }
    137  1.1  cgd 
    138  1.1  cgd void
    139  1.1  cgd pcidma_unmap(addr, size, nmappings, mappings)
    140  1.1  cgd 	caddr_t addr;
    141  1.1  cgd 	vm_size_t size;
    142  1.1  cgd 	int nmappings;
    143  1.1  cgd 	vm_offset_t *mappings;
    144  1.1  cgd {
    145  1.1  cgd 
    146  1.1  cgd 	(*pci_cs_fcns->cs_pcidma_unmap)(addr, size, nmappings, mappings);
    147  1.1  cgd }
    148  1.1  cgd 
    149  1.1  cgd void *
    150  1.1  cgd pci_map_int(tag, level, func, arg)
    151  1.1  cgd 	pcitag_t tag;
    152  1.1  cgd 	pci_intrlevel level;
    153  1.1  cgd 	int (*func) __P((void *));
    154  1.1  cgd 	void *arg;
    155  1.1  cgd {
    156  1.1  cgd 	pcireg_t data;
    157  1.1  cgd 	int pin;
    158  1.1  cgd 
    159  1.1  cgd 	data = pci_conf_read(tag, PCI_INTERRUPT_REG);
    160  1.1  cgd 
    161  1.1  cgd 	pin = PCI_INTERRUPT_PIN(data);
    162  1.1  cgd 
    163  1.1  cgd 	if (pin == 0) {
    164  1.1  cgd 		/* No IRQ used. */
    165  1.1  cgd 		return 0;
    166  1.1  cgd 	}
    167  1.1  cgd 
    168  1.1  cgd 	if (pin > 4) {
    169  1.1  cgd 		printf("pci_map_int: bad interrupt pin %d\n", pin);
    170  1.1  cgd 		return NULL;
    171  1.1  cgd 	}
    172  1.1  cgd 
    173  1.1  cgd 	return (*pci_cfg_fcns->cfg_map_int)(tag, level, func, arg, pin);
    174  1.1  cgd }
    175  1.1  cgd 
    176  1.1  cgd isa_intrlevel
    177  1.1  cgd pcilevel_to_isa(level)
    178  1.1  cgd 	pci_intrlevel level;
    179  1.1  cgd {
    180  1.1  cgd 
    181  1.1  cgd 	switch (level) {
    182  1.1  cgd 	case PCI_IPL_NONE:
    183  1.1  cgd 		return (ISA_IPL_NONE);
    184  1.1  cgd 
    185  1.1  cgd 	case PCI_IPL_BIO:
    186  1.1  cgd 		return (ISA_IPL_BIO);
    187  1.1  cgd 
    188  1.1  cgd 	case PCI_IPL_NET:
    189  1.1  cgd 		return (ISA_IPL_NET);
    190  1.1  cgd 
    191  1.1  cgd 	case PCI_IPL_TTY:
    192  1.1  cgd 		return (ISA_IPL_TTY);
    193  1.1  cgd 
    194  1.1  cgd 	case PCI_IPL_CLOCK:
    195  1.1  cgd 		return (ISA_IPL_CLOCK);
    196  1.1  cgd 
    197  1.1  cgd 	default:
    198  1.1  cgd 		panic("pcilevel_to_isa: unknown level %d\n", level);
    199  1.1  cgd 	}
    200  1.1  cgd }
    201