pci_machdep.c revision 1.26
1 /* $NetBSD: pci_machdep.c,v 1.26 2020/09/25 03:40:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 34 * All rights reserved. 35 * 36 * Author: Chris G. Demetriou 37 * 38 * Permission to use, copy, modify and distribute this software and 39 * its documentation is hereby granted, provided that both the copyright 40 * notice and this permission notice appear in all copies of the 41 * software, derivative works or modified versions, and any portions 42 * thereof, and that both notices appear in supporting documentation. 43 * 44 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 45 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 46 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 47 * 48 * Carnegie Mellon requests users of this software to return to 49 * 50 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 51 * School of Computer Science 52 * Carnegie Mellon University 53 * Pittsburgh PA 15213-3890 54 * 55 * any improvements or extensions that they make and grant Carnegie the 56 * rights to redistribute these changes. 57 */ 58 59 /* 60 * Machine-specific functions for PCI autoconfiguration. 61 */ 62 63 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 64 65 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.26 2020/09/25 03:40:11 thorpej Exp $"); 66 67 #include <sys/types.h> 68 #include <sys/param.h> 69 #include <sys/time.h> 70 #include <sys/systm.h> 71 #include <sys/errno.h> 72 #include <sys/device.h> 73 #include <sys/cpu.h> 74 75 #include <dev/isa/isavar.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include "vga_pci.h" 81 #if NVGA_PCI 82 #include <dev/ic/mc6845reg.h> 83 #include <dev/ic/pcdisplayvar.h> 84 #include <dev/pci/vga_pcivar.h> 85 #endif 86 87 #include "tga.h" 88 #if NTGA 89 #include <dev/pci/tgavar.h> 90 #endif 91 92 #include <machine/rpb.h> 93 94 void 95 pci_display_console(bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc, int bus, int device, int function) 96 { 97 #if NVGA_PCI || NTGA 98 pcitag_t tag; 99 pcireg_t id; 100 int match, nmatch; 101 #endif 102 #if NVGA_PCI 103 pcireg_t class; 104 #endif 105 int (*fn)(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, 106 int, int, int); 107 108 #if NVGA_PCI || NTGA 109 tag = pci_make_tag(pc, bus, device, function); 110 id = pci_conf_read(pc, tag, PCI_ID_REG); 111 if (id == 0 || id == 0xffffffff) 112 panic("pci_display_console: no device at %d/%d/%d", 113 bus, device, function); 114 # if NVGA_PCI 115 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 116 # endif 117 118 match = 0; 119 #endif 120 fn = NULL; 121 122 #if NVGA_PCI 123 nmatch = DEVICE_IS_VGA_PCI(class, id); 124 if (nmatch > match) { 125 match = nmatch; 126 fn = vga_pci_cnattach; 127 } 128 #endif 129 #if NTGA 130 nmatch = DEVICE_IS_TGA(class, id); 131 if (nmatch > match) 132 nmatch = tga_cnmatch(iot, memt, pc, tag); 133 if (nmatch > match) { 134 match = nmatch; 135 fn = tga_cnattach; 136 } 137 #endif 138 139 if (fn != NULL) 140 (*fn)(iot, memt, pc, bus, device, function); 141 else 142 panic("pci_display_console: unconfigured device at %d/%d/%d", 143 bus, device, function); 144 } 145 146 void 147 device_pci_register(device_t dev, void *aux) 148 { 149 struct pci_attach_args *pa = aux; 150 struct ctb *ctb; 151 prop_dictionary_t dict; 152 153 /* set properties for PCI framebuffers */ 154 ctb = (struct ctb *)(((char *)hwrpb) + hwrpb->rpb_ctb_off); 155 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 156 ctb->ctb_term_type == CTB_GRAPHICS) { 157 /* XXX should consider multiple displays? */ 158 dict = device_properties(dev); 159 prop_dictionary_set_bool(dict, "is_console", true); 160 } 161 } 162 163 int 164 alpha_pci_generic_intr_map(const struct pci_attach_args * const pa, 165 pci_intr_handle_t * const ihp) 166 { 167 pcitag_t const bustag = pa->pa_intrtag; 168 int const buspin = pa->pa_intrpin; 169 int const line = pa->pa_intrline; 170 pci_chipset_tag_t const pc = pa->pa_pc; 171 int bus, device, function; 172 173 if (buspin == 0) { 174 /* No IRQ used. */ 175 return 1; 176 } 177 if (buspin < 0 || buspin > 4) { 178 printf("%s: bad interrupt pin %d\n", __func__, buspin); 179 return 1; 180 } 181 182 pci_decompose_tag(pc, bustag, &bus, &device, &function); 183 184 /* 185 * The console firmware places the interrupt mapping in the "line" 186 * value. A valaue of (char)-1 indicates there is no mapping. 187 */ 188 if (line == 0xff) { 189 printf("%s: no mapping for %d/%d/%d\n", __func__, 190 bus, device, function); 191 return 1; 192 } 193 194 if (line < 0 || line >= pc->pc_nirq) { 195 printf("%s: bad line %d for %d/%d/%d\n", __func__, 196 line, bus, device, function); 197 return 1; 198 } 199 200 alpha_pci_intr_handle_init(ihp, line, 0); 201 return 0; 202 } 203 204 const char * 205 alpha_pci_generic_intr_string(pci_chipset_tag_t const pc, 206 pci_intr_handle_t const ih, char * const buf, size_t const len) 207 { 208 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 209 210 KASSERT(irq < pc->pc_nirq); 211 212 snprintf(buf, len, "%s %u", pc->pc_intr_desc, irq); 213 return buf; 214 } 215 216 const struct evcnt * 217 alpha_pci_generic_intr_evcnt(pci_chipset_tag_t const pc, 218 pci_intr_handle_t const ih) 219 { 220 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 221 222 KASSERT(irq < pc->pc_nirq); 223 224 return alpha_shared_intr_evcnt(pc->pc_shared_intrs, irq); 225 } 226 227 void * 228 alpha_pci_generic_intr_establish(pci_chipset_tag_t const pc, 229 pci_intr_handle_t const ih, int const level, 230 int (*func)(void *), void *arg) 231 { 232 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 233 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 234 void *cookie; 235 236 KASSERT(irq < pc->pc_nirq); 237 238 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, 239 irq, IST_LEVEL, level, flags, func, arg, pc->pc_intr_desc); 240 241 if (cookie == NULL) 242 return NULL; 243 244 mutex_enter(&cpu_lock); 245 246 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, 247 pc->pc_intr_desc)) { 248 mutex_exit(&cpu_lock); 249 alpha_shared_intr_free_intrhand(cookie); 250 return NULL; 251 } 252 253 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 254 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 255 alpha_pci_generic_iointr, pc); 256 pc->pc_intr_enable(pc, irq); 257 } 258 259 mutex_exit(&cpu_lock); 260 261 return cookie; 262 } 263 264 void 265 alpha_pci_generic_intr_disestablish(pci_chipset_tag_t const pc, 266 void * const cookie) 267 { 268 struct alpha_shared_intrhand * const ih = cookie; 269 const u_int irq = ih->ih_num; 270 271 mutex_enter(&cpu_lock); 272 273 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 274 pc->pc_intr_disable(pc, irq); 275 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 276 irq, IST_NONE); 277 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 278 } 279 280 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, pc->pc_intr_desc); 281 282 mutex_exit(&cpu_lock); 283 284 alpha_shared_intr_free_intrhand(cookie); 285 } 286 287 void 288 alpha_pci_generic_iointr(void * const arg, unsigned long const vec) 289 { 290 pci_chipset_tag_t const pc = arg; 291 const u_int irq = SCB_VECTOIDX(vec - pc->pc_vecbase); 292 293 if (!alpha_shared_intr_dispatch(pc->pc_shared_intrs, irq)) { 294 alpha_shared_intr_stray(pc->pc_shared_intrs, irq, 295 pc->pc_intr_desc); 296 if (ALPHA_SHARED_INTR_DISABLE(pc->pc_shared_intrs, irq)) { 297 pc->pc_intr_disable(pc, irq); 298 } 299 } else { 300 alpha_shared_intr_reset_strays(pc->pc_shared_intrs, irq); 301 } 302 } 303 304 #define ALPHA_PCI_INTR_HANDLE_IRQ __BITS(0,31) 305 #define ALPHA_PCI_INTR_HANDLE_FLAGS __BITS(32,63) 306 307 void 308 alpha_pci_intr_handle_init(pci_intr_handle_t * const ihp, u_int const irq, 309 u_int const flags) 310 { 311 ihp->value = __SHIFTIN(irq, ALPHA_PCI_INTR_HANDLE_IRQ) | 312 __SHIFTIN(flags, ALPHA_PCI_INTR_HANDLE_FLAGS); 313 } 314 315 void 316 alpha_pci_intr_handle_set_irq(pci_intr_handle_t * const ihp, u_int const irq) 317 { 318 ihp->value = (ihp->value & ALPHA_PCI_INTR_HANDLE_FLAGS) | 319 __SHIFTIN(irq, ALPHA_PCI_INTR_HANDLE_IRQ); 320 } 321 322 u_int 323 alpha_pci_intr_handle_get_irq(const pci_intr_handle_t * const ihp) 324 { 325 return __SHIFTOUT(ihp->value, ALPHA_PCI_INTR_HANDLE_IRQ); 326 } 327 328 void 329 alpha_pci_intr_handle_set_flags(pci_intr_handle_t * const ihp, 330 u_int const flags) 331 { 332 ihp->value = (ihp->value & ALPHA_PCI_INTR_HANDLE_IRQ) | 333 __SHIFTIN(flags, ALPHA_PCI_INTR_HANDLE_FLAGS); 334 } 335 336 u_int 337 alpha_pci_intr_handle_get_flags(const pci_intr_handle_t * const ihp) 338 { 339 return __SHIFTOUT(ihp->value, ALPHA_PCI_INTR_HANDLE_FLAGS); 340 } 341 342 /* 343 * MI PCI back-end entry points. 344 */ 345 346 void 347 pci_attach_hook(device_t const parent, device_t const self, 348 struct pcibus_attach_args * const pba) 349 { 350 pci_chipset_tag_t const pc = pba->pba_pc; 351 352 KASSERT(pc->pc_attach_hook != NULL); 353 pc->pc_attach_hook(parent, self, pba); 354 } 355 356 int 357 pci_bus_maxdevs(pci_chipset_tag_t const pc, int const busno) 358 { 359 KASSERT(pc->pc_bus_maxdevs != NULL); 360 return pc->pc_bus_maxdevs(pc->pc_conf_v, busno); 361 } 362 363 pcitag_t 364 pci_make_tag(pci_chipset_tag_t const pc, int const bus, int const dev, 365 int const func) 366 { 367 KASSERT(pc->pc_make_tag != NULL); 368 return pc->pc_make_tag(pc->pc_conf_v, bus, dev, func); 369 } 370 371 void 372 pci_decompose_tag(pci_chipset_tag_t const pc, pcitag_t const tag, 373 int * const busp, int * const devp, int * const funcp) 374 { 375 KASSERT(pc->pc_decompose_tag != NULL); 376 pc->pc_decompose_tag(pc->pc_conf_v, tag, busp, devp, funcp); 377 } 378 379 pcireg_t 380 pci_conf_read(pci_chipset_tag_t const pc, pcitag_t const tag, int const reg) 381 { 382 KASSERT(pc->pc_conf_read != NULL); 383 return pc->pc_conf_read(pc->pc_conf_v, tag, reg); 384 } 385 386 void 387 pci_conf_write(pci_chipset_tag_t const pc, pcitag_t const tag, int const reg, 388 pcireg_t const val) 389 { 390 KASSERT(pc->pc_conf_write != NULL); 391 pc->pc_conf_write(pc->pc_conf_v, tag, reg, val); 392 } 393 394 int 395 pci_intr_map(const struct pci_attach_args * const pa, 396 pci_intr_handle_t * const ihp) 397 { 398 pci_chipset_tag_t const pc = pa->pa_pc; 399 400 KASSERT(pc->pc_intr_map != NULL); 401 return pc->pc_intr_map(pa, ihp); 402 } 403 404 const char * 405 pci_intr_string(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 406 char * const buf, size_t const len) 407 { 408 KASSERT(pc->pc_intr_string != NULL); 409 return pc->pc_intr_string(pc, ih, buf, len); 410 } 411 412 const struct evcnt * 413 pci_intr_evcnt(pci_chipset_tag_t const pc, pci_intr_handle_t const ih) 414 { 415 KASSERT(pc->pc_intr_evcnt != NULL); 416 return pc->pc_intr_evcnt(pc, ih); 417 } 418 419 void * 420 pci_intr_establish(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 421 int const ipl, int (*func)(void *), void *arg) 422 { 423 KASSERT(pc->pc_intr_establish != NULL); 424 return pc->pc_intr_establish(pc, ih, ipl, func, arg); 425 } 426 427 void 428 pci_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 429 { 430 KASSERT(pc->pc_intr_disestablish != NULL); 431 pc->pc_intr_disestablish(pc, cookie); 432 } 433 434 int 435 pci_intr_setattr(pci_chipset_tag_t const pc __unused, 436 pci_intr_handle_t * const ihp, int const attr, uint64_t const data) 437 { 438 u_int flags = alpha_pci_intr_handle_get_flags(ihp); 439 440 switch (attr) { 441 case PCI_INTR_MPSAFE: 442 if (data) 443 flags |= ALPHA_INTR_MPSAFE; 444 else 445 flags &= ~ALPHA_INTR_MPSAFE; 446 break; 447 448 default: 449 return ENODEV; 450 } 451 452 alpha_pci_intr_handle_set_flags(ihp, flags); 453 return 0; 454 } 455
Indexes created Tue Sep 30 07:10:03 GMT 2025