pci_swiz_bus_io_chipdep.c revision 1.1
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.1 1996/04/12 04:34:59 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #define __C(A,B) __CONCAT(A,B) 40 41 int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, 42 bus_io_handle_t *)); 43 void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, 44 bus_io_size_t)); 45 u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, 46 bus_io_size_t)); 47 u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, 48 bus_io_size_t)); 49 u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, 50 bus_io_size_t)); 51 u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, 52 bus_io_size_t)); 53 void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, 54 bus_io_size_t, u_int8_t)); 55 void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, 56 bus_io_size_t, u_int16_t)); 57 void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, 58 bus_io_size_t, u_int32_t)); 59 void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, 60 bus_io_size_t, u_int64_t)); 61 62 void 63 __C(CHIP,_bus_io_init)(bc, iov) 64 bus_chipset_tag_t bc; 65 void *iov; 66 { 67 68 bc->bc_i_v = iov; 69 70 bc->bc_i_map = __C(CHIP,_io_map); 71 bc->bc_i_unmap = __C(CHIP,_io_unmap); 72 73 bc->bc_ir1 = __C(CHIP,_io_read_1); 74 bc->bc_ir2 = __C(CHIP,_io_read_2); 75 bc->bc_ir4 = __C(CHIP,_io_read_4); 76 bc->bc_ir8 = __C(CHIP,_io_read_8); 77 78 bc->bc_iw1 = __C(CHIP,_io_write_1); 79 bc->bc_iw2 = __C(CHIP,_io_write_2); 80 bc->bc_iw4 = __C(CHIP,_io_write_4); 81 bc->bc_iw8 = __C(CHIP,_io_write_8); 82 } 83 84 int 85 __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) 86 void *v; 87 bus_io_addr_t ioaddr; 88 bus_io_size_t iosize; 89 bus_io_handle_t *iohp; 90 { 91 92 *iohp = (phystok0seg(CHIP_IO_BASE) >> 5) + ioaddr; 93 return (0); 94 } 95 96 void 97 __C(CHIP,_io_unmap)(v, ioh, iosize) 98 void *v; 99 bus_io_handle_t ioh; 100 bus_io_size_t iosize; 101 { 102 103 /* XXX nothing to do. */ 104 } 105 106 u_int8_t 107 __C(CHIP,_io_read_1)(v, ioh, off) 108 void *v; 109 bus_io_handle_t ioh; 110 bus_io_size_t off; 111 { 112 register bus_io_handle_t tmpioh; 113 register u_int32_t *port, val; 114 register u_int8_t rval; 115 register int offset; 116 117 wbflush(); 118 119 tmpioh = ioh + off; 120 offset = tmpioh & 3; 121 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 122 val = *port; 123 rval = ((val) >> (8 * offset)) & 0xff; 124 125 return rval; 126 } 127 128 u_int16_t 129 __C(CHIP,_io_read_2)(v, ioh, off) 130 void *v; 131 bus_io_handle_t ioh; 132 bus_io_size_t off; 133 { 134 register bus_io_handle_t tmpioh; 135 register u_int32_t *port, val; 136 register u_int16_t rval; 137 register int offset; 138 139 wbflush(); 140 141 tmpioh = ioh + off; 142 offset = tmpioh & 3; 143 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 144 val = *port; 145 rval = ((val) >> (8 * offset)) & 0xffff; 146 147 return rval; 148 } 149 150 u_int32_t 151 __C(CHIP,_io_read_4)(v, ioh, off) 152 void *v; 153 bus_io_handle_t ioh; 154 bus_io_size_t off; 155 { 156 register bus_io_handle_t tmpioh; 157 register u_int32_t *port, val; 158 register u_int32_t rval; 159 register int offset; 160 161 wbflush(); 162 163 tmpioh = ioh + off; 164 offset = tmpioh & 3; 165 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 166 val = *port; 167 #if 0 168 rval = ((val) >> (8 * offset)) & 0xffffffff; 169 #else 170 rval = val; 171 #endif 172 173 return rval; 174 } 175 176 u_int64_t 177 __C(CHIP,_io_read_8)(v, ioh, off) 178 void *v; 179 bus_io_handle_t ioh; 180 bus_io_size_t off; 181 { 182 183 /* XXX XXX XXX */ 184 panic("%s not implemented\n", __STRING(__C(CHIP,_io_read_8))); 185 } 186 187 void 188 __C(CHIP,_io_write_1)(v, ioh, off, val) 189 void *v; 190 bus_io_handle_t ioh; 191 bus_io_size_t off; 192 u_int8_t val; 193 { 194 register bus_io_handle_t tmpioh; 195 register u_int32_t *port, nval; 196 register int offset; 197 198 tmpioh = ioh + off; 199 offset = tmpioh & 3; 200 nval = val << (8 * offset); 201 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 202 *port = nval; 203 wbflush(); 204 } 205 206 void 207 __C(CHIP,_io_write_2)(v, ioh, off, val) 208 void *v; 209 bus_io_handle_t ioh; 210 bus_io_size_t off; 211 u_int16_t val; 212 { 213 register bus_io_handle_t tmpioh; 214 register u_int32_t *port, nval; 215 register int offset; 216 217 tmpioh = ioh + off; 218 offset = tmpioh & 3; 219 nval = val << (8 * offset); 220 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 221 *port = nval; 222 wbflush(); 223 } 224 225 void 226 __C(CHIP,_io_write_4)(v, ioh, off, val) 227 void *v; 228 bus_io_handle_t ioh; 229 bus_io_size_t off; 230 u_int32_t val; 231 { 232 register bus_io_handle_t tmpioh; 233 register u_int32_t *port, nval; 234 register int offset; 235 236 tmpioh = ioh + off; 237 offset = tmpioh & 3; 238 nval = val /*<< (8 * offset)*/; 239 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 240 *port = nval; 241 wbflush(); 242 } 243 244 void 245 __C(CHIP,_io_write_8)(v, ioh, off, val) 246 void *v; 247 bus_io_handle_t ioh; 248 bus_io_size_t off; 249 u_int64_t val; 250 { 251 252 /* XXX XXX XXX */ 253 panic("%s not implemented\n", __STRING(__C(CHIP,_io_write_8))); 254 wbflush(); 255 } 256
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