pci_swiz_bus_io_chipdep.c revision 1.12
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.12 1996/12/02 06:46:52 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #include <sys/extent.h> 40 41 #define __C(A,B) __CONCAT(A,B) 42 #define __S(S) __STRING(S) 43 44 /* mapping/unmapping */ 45 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 46 bus_space_handle_t *)); 47 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 48 bus_size_t)); 49 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 50 bus_size_t, bus_size_t, bus_space_handle_t *)); 51 52 /* allocation/deallocation */ 53 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 54 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 59 /* read (single) */ 60 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 61 bus_size_t)); 62 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 63 bus_size_t)); 64 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 65 bus_size_t)); 66 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 67 bus_size_t)); 68 69 /* read multiple */ 70 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 71 bus_size_t, u_int8_t *, bus_size_t)); 72 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 73 bus_size_t, u_int16_t *, bus_size_t)); 74 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 75 bus_size_t, u_int32_t *, bus_size_t)); 76 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 77 bus_size_t, u_int64_t *, bus_size_t)); 78 79 /* read region */ 80 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 81 bus_size_t, u_int8_t *, bus_size_t)); 82 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 83 bus_size_t, u_int16_t *, bus_size_t)); 84 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 85 bus_size_t, u_int32_t *, bus_size_t)); 86 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 87 bus_size_t, u_int64_t *, bus_size_t)); 88 89 /* write (single) */ 90 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 91 bus_size_t, u_int8_t)); 92 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 93 bus_size_t, u_int16_t)); 94 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 95 bus_size_t, u_int32_t)); 96 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 97 bus_size_t, u_int64_t)); 98 99 /* write multiple */ 100 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 101 bus_size_t, const u_int8_t *, bus_size_t)); 102 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 103 bus_size_t, const u_int16_t *, bus_size_t)); 104 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 105 bus_size_t, const u_int32_t *, bus_size_t)); 106 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 107 bus_size_t, const u_int64_t *, bus_size_t)); 108 109 /* write region */ 110 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 111 bus_size_t, const u_int8_t *, bus_size_t)); 112 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 113 bus_size_t, const u_int16_t *, bus_size_t)); 114 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 115 bus_size_t, const u_int32_t *, bus_size_t)); 116 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 117 bus_size_t, const u_int64_t *, bus_size_t)); 118 119 /* set multiple */ 120 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t, bus_size_t)); 122 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t, bus_size_t)); 124 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t, bus_size_t)); 126 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t, bus_size_t)); 128 129 /* set region */ 130 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t, bus_size_t)); 132 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t, bus_size_t)); 134 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t, bus_size_t)); 136 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t, bus_size_t)); 138 139 /* barrier */ 140 void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 141 bus_size_t, bus_size_t, int)); 142 143 static long 144 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 145 146 static struct alpha_bus_space __C(CHIP,_io_space) = { 147 /* cookie */ 148 NULL, 149 150 /* mapping/unmapping */ 151 __C(CHIP,_io_map), 152 __C(CHIP,_io_unmap), 153 __C(CHIP,_io_subregion), 154 155 /* allocation/deallocation */ 156 __C(CHIP,_io_alloc), 157 __C(CHIP,_io_free), 158 159 /* read (single) */ 160 __C(CHIP,_io_read_1), 161 __C(CHIP,_io_read_2), 162 __C(CHIP,_io_read_4), 163 __C(CHIP,_io_read_8), 164 165 /* read multiple */ 166 __C(CHIP,_io_read_multi_1), 167 __C(CHIP,_io_read_multi_2), 168 __C(CHIP,_io_read_multi_4), 169 __C(CHIP,_io_read_multi_8), 170 171 /* read region */ 172 __C(CHIP,_io_read_region_1), 173 __C(CHIP,_io_read_region_2), 174 __C(CHIP,_io_read_region_4), 175 __C(CHIP,_io_read_region_8), 176 177 /* write (single) */ 178 __C(CHIP,_io_write_1), 179 __C(CHIP,_io_write_2), 180 __C(CHIP,_io_write_4), 181 __C(CHIP,_io_write_8), 182 183 /* write multiple */ 184 __C(CHIP,_io_write_multi_1), 185 __C(CHIP,_io_write_multi_2), 186 __C(CHIP,_io_write_multi_4), 187 __C(CHIP,_io_write_multi_8), 188 189 /* write region */ 190 __C(CHIP,_io_write_region_1), 191 __C(CHIP,_io_write_region_2), 192 __C(CHIP,_io_write_region_4), 193 __C(CHIP,_io_write_region_8), 194 195 /* set multiple */ 196 __C(CHIP,_io_set_multi_1), 197 __C(CHIP,_io_set_multi_2), 198 __C(CHIP,_io_set_multi_4), 199 __C(CHIP,_io_set_multi_8), 200 201 /* set region */ 202 __C(CHIP,_io_set_region_1), 203 __C(CHIP,_io_set_region_2), 204 __C(CHIP,_io_set_region_4), 205 __C(CHIP,_io_set_region_8), 206 207 /* copy */ 208 /* XXX IMPLEMENT */ 209 210 /* barrier */ 211 __C(CHIP,_io_barrier), 212 }; 213 214 bus_space_tag_t 215 __C(CHIP,_bus_io_init)(v) 216 void *v; 217 { 218 bus_space_tag_t t = &__C(CHIP,_io_space); 219 struct extent *ex; 220 221 t->abs_cookie = v; 222 223 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 224 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 225 M_DEVBUF, (caddr_t)__C(CHIP,_io_ex_storage), 226 sizeof(__C(CHIP,_io_ex_storage)), EX_NOWAIT); 227 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 228 229 #ifdef CHIP_IO_W1_BUS_START 230 #ifdef EXTENT_DEBUG 231 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 232 CHIP_IO_W1_BUS_END(v)); 233 #endif 234 extent_free(ex, CHIP_IO_W1_BUS_START(v), 235 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 236 #endif 237 #ifdef CHIP_IO_W2_BUS_START 238 #ifdef EXTENT_DEBUG 239 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 240 CHIP_IO_W2_BUS_END(v)); 241 #endif 242 extent_free(ex, CHIP_IO_W2_BUS_START(v), 243 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 244 #endif 245 246 #ifdef EXTENT_DEBUG 247 extent_print(ex); 248 #endif 249 CHIP_IO_EXTENT(v) = ex; 250 251 return (t); 252 } 253 254 int 255 __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) 256 void *v; 257 bus_addr_t ioaddr; 258 bus_size_t iosize; 259 int cacheable; 260 bus_space_handle_t *iohp; 261 { 262 int error; 263 264 #ifdef EXTENT_DEBUG 265 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 266 #endif 267 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 268 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 269 if (error) { 270 #ifdef EXTENT_DEBUG 271 printf("io: allocation failed (%d)\n", error); 272 extent_print(CHIP_IO_EXTENT(v)); 273 #endif 274 return (error); 275 } 276 277 #ifdef CHIP_IO_W1_BUS_START 278 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 279 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 280 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 281 (ioaddr - CHIP_IO_W1_BUS_START(v)); 282 } else 283 #endif 284 #ifdef CHIP_IO_W2_BUS_START 285 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 286 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 287 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 288 (ioaddr - CHIP_IO_W2_BUS_START(v)); 289 } else 290 #endif 291 { 292 printf("\n"); 293 #ifdef CHIP_IO_W1_BUS_START 294 printf("%s: window[1]=0x%lx-0x%lx\n", 295 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 296 CHIP_IO_W1_BUS_END(v)); 297 #endif 298 #ifdef CHIP_IO_W2_BUS_START 299 printf("%s: window[2]=0x%lx-0x%lx\n", 300 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 301 CHIP_IO_W2_BUS_END(v)); 302 #endif 303 panic("%s: don't know how to map %lx", 304 __S(__C(CHIP,_io_map)), ioaddr); 305 } 306 307 return (0); 308 } 309 310 void 311 __C(CHIP,_io_unmap)(v, ioh, iosize) 312 void *v; 313 bus_space_handle_t ioh; 314 bus_size_t iosize; 315 { 316 bus_addr_t ioaddr; 317 int error; 318 319 #ifdef EXTENT_DEBUG 320 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 321 #endif 322 323 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 324 325 #ifdef CHIP_IO_W1_BUS_START 326 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 327 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 328 ioaddr = CHIP_IO_W1_BUS_START(v) + 329 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 330 } else 331 #endif 332 #ifdef CHIP_IO_W2_BUS_START 333 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 334 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 335 ioaddr = CHIP_IO_W2_BUS_START(v) + 336 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 337 } else 338 #endif 339 { 340 printf("\n"); 341 #ifdef CHIP_IO_W1_BUS_START 342 printf("%s: sys window[1]=0x%lx-0x%lx\n", 343 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 344 CHIP_IO_W1_SYS_END(v)); 345 #endif 346 #ifdef CHIP_IO_W2_BUS_START 347 printf("%s: sys window[2]=0x%lx-0x%lx\n", 348 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 349 CHIP_IO_W2_SYS_END(v)); 350 #endif 351 panic("%s: don't know how to unmap %lx", 352 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 353 } 354 355 #ifdef EXTENT_DEBUG 356 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 357 #endif 358 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 359 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 360 if (error) { 361 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 362 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 363 error); 364 #ifdef EXTENT_DEBUG 365 extent_print(CHIP_IO_EXTENT(v)); 366 #endif 367 } 368 } 369 370 int 371 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 372 void *v; 373 bus_space_handle_t ioh, *nioh; 374 bus_size_t offset, size; 375 { 376 377 *nioh = ioh + offset; 378 return (0); 379 } 380 381 int 382 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, 383 addrp, bshp) 384 void *v; 385 bus_addr_t rstart, rend, *addrp; 386 bus_size_t size, align, boundary; 387 int cacheable; 388 bus_space_handle_t *bshp; 389 { 390 391 /* XXX XXX XXX XXX XXX XXX */ 392 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 393 } 394 395 void 396 __C(CHIP,_io_free)(v, bsh, size) 397 void *v; 398 bus_space_handle_t bsh; 399 bus_size_t size; 400 { 401 402 /* XXX XXX XXX XXX XXX XXX */ 403 panic("%s not implemented", __S(__C(CHIP,_io_free))); 404 } 405 406 inline u_int8_t 407 __C(CHIP,_io_read_1)(v, ioh, off) 408 void *v; 409 bus_space_handle_t ioh; 410 bus_size_t off; 411 { 412 register bus_space_handle_t tmpioh; 413 register u_int32_t *port, val; 414 register u_int8_t rval; 415 register int offset; 416 417 alpha_mb(); 418 419 tmpioh = ioh + off; 420 offset = tmpioh & 3; 421 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 422 val = *port; 423 rval = ((val) >> (8 * offset)) & 0xff; 424 425 return rval; 426 } 427 428 inline u_int16_t 429 __C(CHIP,_io_read_2)(v, ioh, off) 430 void *v; 431 bus_space_handle_t ioh; 432 bus_size_t off; 433 { 434 register bus_space_handle_t tmpioh; 435 register u_int32_t *port, val; 436 register u_int16_t rval; 437 register int offset; 438 439 alpha_mb(); 440 441 tmpioh = ioh + off; 442 offset = tmpioh & 3; 443 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 444 val = *port; 445 rval = ((val) >> (8 * offset)) & 0xffff; 446 447 return rval; 448 } 449 450 inline u_int32_t 451 __C(CHIP,_io_read_4)(v, ioh, off) 452 void *v; 453 bus_space_handle_t ioh; 454 bus_size_t off; 455 { 456 register bus_space_handle_t tmpioh; 457 register u_int32_t *port, val; 458 register u_int32_t rval; 459 register int offset; 460 461 alpha_mb(); 462 463 tmpioh = ioh + off; 464 offset = tmpioh & 3; 465 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 466 val = *port; 467 #if 0 468 rval = ((val) >> (8 * offset)) & 0xffffffff; 469 #else 470 rval = val; 471 #endif 472 473 return rval; 474 } 475 476 inline u_int64_t 477 __C(CHIP,_io_read_8)(v, ioh, off) 478 void *v; 479 bus_space_handle_t ioh; 480 bus_size_t off; 481 { 482 483 /* XXX XXX XXX */ 484 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 485 } 486 487 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 488 void \ 489 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 490 void *v; \ 491 bus_space_handle_t h; \ 492 bus_size_t o, c; \ 493 TYPE *a; \ 494 { \ 495 \ 496 while (c-- > 0) { \ 497 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 498 BUS_BARRIER_READ); \ 499 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 500 } \ 501 } 502 CHIP_io_read_multi_N(1,u_int8_t) 503 CHIP_io_read_multi_N(2,u_int16_t) 504 CHIP_io_read_multi_N(4,u_int32_t) 505 CHIP_io_read_multi_N(8,u_int64_t) 506 507 #define CHIP_io_read_region_N(BYTES,TYPE) \ 508 void \ 509 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 510 void *v; \ 511 bus_space_handle_t h; \ 512 bus_size_t o, c; \ 513 TYPE *a; \ 514 { \ 515 \ 516 while (c-- > 0) { \ 517 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 518 o += sizeof *a; \ 519 } \ 520 } 521 CHIP_io_read_region_N(1,u_int8_t) 522 CHIP_io_read_region_N(2,u_int16_t) 523 CHIP_io_read_region_N(4,u_int32_t) 524 CHIP_io_read_region_N(8,u_int64_t) 525 526 inline void 527 __C(CHIP,_io_write_1)(v, ioh, off, val) 528 void *v; 529 bus_space_handle_t ioh; 530 bus_size_t off; 531 u_int8_t val; 532 { 533 register bus_space_handle_t tmpioh; 534 register u_int32_t *port, nval; 535 register int offset; 536 537 tmpioh = ioh + off; 538 offset = tmpioh & 3; 539 nval = val << (8 * offset); 540 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 541 *port = nval; 542 alpha_mb(); 543 } 544 545 inline void 546 __C(CHIP,_io_write_2)(v, ioh, off, val) 547 void *v; 548 bus_space_handle_t ioh; 549 bus_size_t off; 550 u_int16_t val; 551 { 552 register bus_space_handle_t tmpioh; 553 register u_int32_t *port, nval; 554 register int offset; 555 556 tmpioh = ioh + off; 557 offset = tmpioh & 3; 558 nval = val << (8 * offset); 559 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 560 *port = nval; 561 alpha_mb(); 562 } 563 564 inline void 565 __C(CHIP,_io_write_4)(v, ioh, off, val) 566 void *v; 567 bus_space_handle_t ioh; 568 bus_size_t off; 569 u_int32_t val; 570 { 571 register bus_space_handle_t tmpioh; 572 register u_int32_t *port, nval; 573 register int offset; 574 575 tmpioh = ioh + off; 576 offset = tmpioh & 3; 577 nval = val /*<< (8 * offset)*/; 578 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 579 *port = nval; 580 alpha_mb(); 581 } 582 583 inline void 584 __C(CHIP,_io_write_8)(v, ioh, off, val) 585 void *v; 586 bus_space_handle_t ioh; 587 bus_size_t off; 588 u_int64_t val; 589 { 590 591 /* XXX XXX XXX */ 592 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 593 alpha_mb(); 594 } 595 596 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 597 void \ 598 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 599 void *v; \ 600 bus_space_handle_t h; \ 601 bus_size_t o, c; \ 602 const TYPE *a; \ 603 { \ 604 \ 605 while (c-- > 0) { \ 606 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 607 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 608 BUS_BARRIER_WRITE); \ 609 } \ 610 } 611 CHIP_io_write_multi_N(1,u_int8_t) 612 CHIP_io_write_multi_N(2,u_int16_t) 613 CHIP_io_write_multi_N(4,u_int32_t) 614 CHIP_io_write_multi_N(8,u_int64_t) 615 616 #define CHIP_io_write_region_N(BYTES,TYPE) \ 617 void \ 618 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 619 void *v; \ 620 bus_space_handle_t h; \ 621 bus_size_t o, c; \ 622 const TYPE *a; \ 623 { \ 624 \ 625 while (c-- > 0) { \ 626 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 627 o += sizeof *a; \ 628 } \ 629 } 630 CHIP_io_write_region_N(1,u_int8_t) 631 CHIP_io_write_region_N(2,u_int16_t) 632 CHIP_io_write_region_N(4,u_int32_t) 633 CHIP_io_write_region_N(8,u_int64_t) 634 635 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 636 void \ 637 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 638 void *v; \ 639 bus_space_handle_t h; \ 640 bus_size_t o, c; \ 641 TYPE val; \ 642 { \ 643 \ 644 while (c-- > 0) { \ 645 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 646 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 647 BUS_BARRIER_WRITE); \ 648 } \ 649 } 650 CHIP_io_set_multi_N(1,u_int8_t) 651 CHIP_io_set_multi_N(2,u_int16_t) 652 CHIP_io_set_multi_N(4,u_int32_t) 653 CHIP_io_set_multi_N(8,u_int64_t) 654 655 #define CHIP_io_set_region_N(BYTES,TYPE) \ 656 void \ 657 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 658 void *v; \ 659 bus_space_handle_t h; \ 660 bus_size_t o, c; \ 661 TYPE val; \ 662 { \ 663 \ 664 while (c-- > 0) { \ 665 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 666 o += sizeof val; \ 667 } \ 668 } 669 CHIP_io_set_region_N(1,u_int8_t) 670 CHIP_io_set_region_N(2,u_int16_t) 671 CHIP_io_set_region_N(4,u_int32_t) 672 CHIP_io_set_region_N(8,u_int64_t) 673 674 void 675 __C(CHIP,_io_barrier)(v, h, o, l, f) 676 void *v; 677 bus_space_handle_t h; 678 bus_size_t o, l; 679 int f; 680 { 681 682 if ((f & BUS_BARRIER_READ) != 0) 683 alpha_mb(); 684 else if ((f & BUS_BARRIER_WRITE) != 0) 685 alpha_wmb(); 686 } 687
Indexes created Tue Oct 14 15:09:51 GMT 2025