pci_swiz_bus_io_chipdep.c revision 1.13
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.13 1996/12/02 07:07:21 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #include <sys/extent.h> 40 41 #define __C(A,B) __CONCAT(A,B) 42 #define __S(S) __STRING(S) 43 44 /* mapping/unmapping */ 45 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 46 bus_space_handle_t *)); 47 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 48 bus_size_t)); 49 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 50 bus_size_t, bus_size_t, bus_space_handle_t *)); 51 52 /* allocation/deallocation */ 53 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 54 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 59 /* barrier */ 60 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 61 bus_size_t, bus_size_t, int)); 62 63 /* read (single) */ 64 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 65 bus_size_t)); 66 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 67 bus_size_t)); 68 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 69 bus_size_t)); 70 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 71 bus_size_t)); 72 73 /* read multiple */ 74 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 75 bus_size_t, u_int8_t *, bus_size_t)); 76 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 77 bus_size_t, u_int16_t *, bus_size_t)); 78 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 79 bus_size_t, u_int32_t *, bus_size_t)); 80 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 81 bus_size_t, u_int64_t *, bus_size_t)); 82 83 /* read region */ 84 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 85 bus_size_t, u_int8_t *, bus_size_t)); 86 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 87 bus_size_t, u_int16_t *, bus_size_t)); 88 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 89 bus_size_t, u_int32_t *, bus_size_t)); 90 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 91 bus_size_t, u_int64_t *, bus_size_t)); 92 93 /* write (single) */ 94 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 95 bus_size_t, u_int8_t)); 96 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 97 bus_size_t, u_int16_t)); 98 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 99 bus_size_t, u_int32_t)); 100 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 101 bus_size_t, u_int64_t)); 102 103 /* write multiple */ 104 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 105 bus_size_t, const u_int8_t *, bus_size_t)); 106 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 107 bus_size_t, const u_int16_t *, bus_size_t)); 108 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 109 bus_size_t, const u_int32_t *, bus_size_t)); 110 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 111 bus_size_t, const u_int64_t *, bus_size_t)); 112 113 /* write region */ 114 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 115 bus_size_t, const u_int8_t *, bus_size_t)); 116 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 117 bus_size_t, const u_int16_t *, bus_size_t)); 118 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 119 bus_size_t, const u_int32_t *, bus_size_t)); 120 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 121 bus_size_t, const u_int64_t *, bus_size_t)); 122 123 /* set multiple */ 124 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int8_t, bus_size_t)); 126 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int16_t, bus_size_t)); 128 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 129 bus_size_t, u_int32_t, bus_size_t)); 130 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int64_t, bus_size_t)); 132 133 /* set region */ 134 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int8_t, bus_size_t)); 136 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int16_t, bus_size_t)); 138 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int32_t, bus_size_t)); 140 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int64_t, bus_size_t)); 142 143 static long 144 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 145 146 static struct alpha_bus_space __C(CHIP,_io_space) = { 147 /* cookie */ 148 NULL, 149 150 /* mapping/unmapping */ 151 __C(CHIP,_io_map), 152 __C(CHIP,_io_unmap), 153 __C(CHIP,_io_subregion), 154 155 /* allocation/deallocation */ 156 __C(CHIP,_io_alloc), 157 __C(CHIP,_io_free), 158 159 /* barrier */ 160 __C(CHIP,_io_barrier), 161 162 /* read (single) */ 163 __C(CHIP,_io_read_1), 164 __C(CHIP,_io_read_2), 165 __C(CHIP,_io_read_4), 166 __C(CHIP,_io_read_8), 167 168 /* read multiple */ 169 __C(CHIP,_io_read_multi_1), 170 __C(CHIP,_io_read_multi_2), 171 __C(CHIP,_io_read_multi_4), 172 __C(CHIP,_io_read_multi_8), 173 174 /* read region */ 175 __C(CHIP,_io_read_region_1), 176 __C(CHIP,_io_read_region_2), 177 __C(CHIP,_io_read_region_4), 178 __C(CHIP,_io_read_region_8), 179 180 /* write (single) */ 181 __C(CHIP,_io_write_1), 182 __C(CHIP,_io_write_2), 183 __C(CHIP,_io_write_4), 184 __C(CHIP,_io_write_8), 185 186 /* write multiple */ 187 __C(CHIP,_io_write_multi_1), 188 __C(CHIP,_io_write_multi_2), 189 __C(CHIP,_io_write_multi_4), 190 __C(CHIP,_io_write_multi_8), 191 192 /* write region */ 193 __C(CHIP,_io_write_region_1), 194 __C(CHIP,_io_write_region_2), 195 __C(CHIP,_io_write_region_4), 196 __C(CHIP,_io_write_region_8), 197 198 /* set multiple */ 199 __C(CHIP,_io_set_multi_1), 200 __C(CHIP,_io_set_multi_2), 201 __C(CHIP,_io_set_multi_4), 202 __C(CHIP,_io_set_multi_8), 203 204 /* set region */ 205 __C(CHIP,_io_set_region_1), 206 __C(CHIP,_io_set_region_2), 207 __C(CHIP,_io_set_region_4), 208 __C(CHIP,_io_set_region_8), 209 210 /* copy */ 211 /* XXX IMPLEMENT */ 212 }; 213 214 bus_space_tag_t 215 __C(CHIP,_bus_io_init)(v) 216 void *v; 217 { 218 bus_space_tag_t t = &__C(CHIP,_io_space); 219 struct extent *ex; 220 221 t->abs_cookie = v; 222 223 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 224 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 225 M_DEVBUF, (caddr_t)__C(CHIP,_io_ex_storage), 226 sizeof(__C(CHIP,_io_ex_storage)), EX_NOWAIT); 227 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 228 229 #ifdef CHIP_IO_W1_BUS_START 230 #ifdef EXTENT_DEBUG 231 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 232 CHIP_IO_W1_BUS_END(v)); 233 #endif 234 extent_free(ex, CHIP_IO_W1_BUS_START(v), 235 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 236 #endif 237 #ifdef CHIP_IO_W2_BUS_START 238 #ifdef EXTENT_DEBUG 239 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 240 CHIP_IO_W2_BUS_END(v)); 241 #endif 242 extent_free(ex, CHIP_IO_W2_BUS_START(v), 243 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 244 #endif 245 246 #ifdef EXTENT_DEBUG 247 extent_print(ex); 248 #endif 249 CHIP_IO_EXTENT(v) = ex; 250 251 return (t); 252 } 253 254 int 255 __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) 256 void *v; 257 bus_addr_t ioaddr; 258 bus_size_t iosize; 259 int cacheable; 260 bus_space_handle_t *iohp; 261 { 262 int error; 263 264 #ifdef EXTENT_DEBUG 265 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 266 #endif 267 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 268 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 269 if (error) { 270 #ifdef EXTENT_DEBUG 271 printf("io: allocation failed (%d)\n", error); 272 extent_print(CHIP_IO_EXTENT(v)); 273 #endif 274 return (error); 275 } 276 277 #ifdef CHIP_IO_W1_BUS_START 278 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 279 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 280 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 281 (ioaddr - CHIP_IO_W1_BUS_START(v)); 282 } else 283 #endif 284 #ifdef CHIP_IO_W2_BUS_START 285 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 286 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 287 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 288 (ioaddr - CHIP_IO_W2_BUS_START(v)); 289 } else 290 #endif 291 { 292 printf("\n"); 293 #ifdef CHIP_IO_W1_BUS_START 294 printf("%s: window[1]=0x%lx-0x%lx\n", 295 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 296 CHIP_IO_W1_BUS_END(v)); 297 #endif 298 #ifdef CHIP_IO_W2_BUS_START 299 printf("%s: window[2]=0x%lx-0x%lx\n", 300 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 301 CHIP_IO_W2_BUS_END(v)); 302 #endif 303 panic("%s: don't know how to map %lx", 304 __S(__C(CHIP,_io_map)), ioaddr); 305 } 306 307 return (0); 308 } 309 310 void 311 __C(CHIP,_io_unmap)(v, ioh, iosize) 312 void *v; 313 bus_space_handle_t ioh; 314 bus_size_t iosize; 315 { 316 bus_addr_t ioaddr; 317 int error; 318 319 #ifdef EXTENT_DEBUG 320 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 321 #endif 322 323 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 324 325 #ifdef CHIP_IO_W1_BUS_START 326 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 327 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 328 ioaddr = CHIP_IO_W1_BUS_START(v) + 329 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 330 } else 331 #endif 332 #ifdef CHIP_IO_W2_BUS_START 333 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 334 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 335 ioaddr = CHIP_IO_W2_BUS_START(v) + 336 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 337 } else 338 #endif 339 { 340 printf("\n"); 341 #ifdef CHIP_IO_W1_BUS_START 342 printf("%s: sys window[1]=0x%lx-0x%lx\n", 343 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 344 CHIP_IO_W1_SYS_END(v)); 345 #endif 346 #ifdef CHIP_IO_W2_BUS_START 347 printf("%s: sys window[2]=0x%lx-0x%lx\n", 348 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 349 CHIP_IO_W2_SYS_END(v)); 350 #endif 351 panic("%s: don't know how to unmap %lx", 352 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 353 } 354 355 #ifdef EXTENT_DEBUG 356 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 357 #endif 358 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 359 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 360 if (error) { 361 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 362 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 363 error); 364 #ifdef EXTENT_DEBUG 365 extent_print(CHIP_IO_EXTENT(v)); 366 #endif 367 } 368 } 369 370 int 371 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 372 void *v; 373 bus_space_handle_t ioh, *nioh; 374 bus_size_t offset, size; 375 { 376 377 *nioh = ioh + offset; 378 return (0); 379 } 380 381 int 382 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, 383 addrp, bshp) 384 void *v; 385 bus_addr_t rstart, rend, *addrp; 386 bus_size_t size, align, boundary; 387 int cacheable; 388 bus_space_handle_t *bshp; 389 { 390 391 /* XXX XXX XXX XXX XXX XXX */ 392 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 393 } 394 395 void 396 __C(CHIP,_io_free)(v, bsh, size) 397 void *v; 398 bus_space_handle_t bsh; 399 bus_size_t size; 400 { 401 402 /* XXX XXX XXX XXX XXX XXX */ 403 panic("%s not implemented", __S(__C(CHIP,_io_free))); 404 } 405 406 inline void 407 __C(CHIP,_io_barrier)(v, h, o, l, f) 408 void *v; 409 bus_space_handle_t h; 410 bus_size_t o, l; 411 int f; 412 { 413 414 if ((f & BUS_BARRIER_READ) != 0) 415 alpha_mb(); 416 else if ((f & BUS_BARRIER_WRITE) != 0) 417 alpha_wmb(); 418 } 419 420 inline u_int8_t 421 __C(CHIP,_io_read_1)(v, ioh, off) 422 void *v; 423 bus_space_handle_t ioh; 424 bus_size_t off; 425 { 426 register bus_space_handle_t tmpioh; 427 register u_int32_t *port, val; 428 register u_int8_t rval; 429 register int offset; 430 431 alpha_mb(); 432 433 tmpioh = ioh + off; 434 offset = tmpioh & 3; 435 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 436 val = *port; 437 rval = ((val) >> (8 * offset)) & 0xff; 438 439 return rval; 440 } 441 442 inline u_int16_t 443 __C(CHIP,_io_read_2)(v, ioh, off) 444 void *v; 445 bus_space_handle_t ioh; 446 bus_size_t off; 447 { 448 register bus_space_handle_t tmpioh; 449 register u_int32_t *port, val; 450 register u_int16_t rval; 451 register int offset; 452 453 alpha_mb(); 454 455 tmpioh = ioh + off; 456 offset = tmpioh & 3; 457 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 458 val = *port; 459 rval = ((val) >> (8 * offset)) & 0xffff; 460 461 return rval; 462 } 463 464 inline u_int32_t 465 __C(CHIP,_io_read_4)(v, ioh, off) 466 void *v; 467 bus_space_handle_t ioh; 468 bus_size_t off; 469 { 470 register bus_space_handle_t tmpioh; 471 register u_int32_t *port, val; 472 register u_int32_t rval; 473 register int offset; 474 475 alpha_mb(); 476 477 tmpioh = ioh + off; 478 offset = tmpioh & 3; 479 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 480 val = *port; 481 #if 0 482 rval = ((val) >> (8 * offset)) & 0xffffffff; 483 #else 484 rval = val; 485 #endif 486 487 return rval; 488 } 489 490 inline u_int64_t 491 __C(CHIP,_io_read_8)(v, ioh, off) 492 void *v; 493 bus_space_handle_t ioh; 494 bus_size_t off; 495 { 496 497 /* XXX XXX XXX */ 498 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 499 } 500 501 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 502 void \ 503 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 504 void *v; \ 505 bus_space_handle_t h; \ 506 bus_size_t o, c; \ 507 TYPE *a; \ 508 { \ 509 \ 510 while (c-- > 0) { \ 511 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 512 BUS_BARRIER_READ); \ 513 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 514 } \ 515 } 516 CHIP_io_read_multi_N(1,u_int8_t) 517 CHIP_io_read_multi_N(2,u_int16_t) 518 CHIP_io_read_multi_N(4,u_int32_t) 519 CHIP_io_read_multi_N(8,u_int64_t) 520 521 #define CHIP_io_read_region_N(BYTES,TYPE) \ 522 void \ 523 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 524 void *v; \ 525 bus_space_handle_t h; \ 526 bus_size_t o, c; \ 527 TYPE *a; \ 528 { \ 529 \ 530 while (c-- > 0) { \ 531 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 532 o += sizeof *a; \ 533 } \ 534 } 535 CHIP_io_read_region_N(1,u_int8_t) 536 CHIP_io_read_region_N(2,u_int16_t) 537 CHIP_io_read_region_N(4,u_int32_t) 538 CHIP_io_read_region_N(8,u_int64_t) 539 540 inline void 541 __C(CHIP,_io_write_1)(v, ioh, off, val) 542 void *v; 543 bus_space_handle_t ioh; 544 bus_size_t off; 545 u_int8_t val; 546 { 547 register bus_space_handle_t tmpioh; 548 register u_int32_t *port, nval; 549 register int offset; 550 551 tmpioh = ioh + off; 552 offset = tmpioh & 3; 553 nval = val << (8 * offset); 554 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 555 *port = nval; 556 alpha_mb(); 557 } 558 559 inline void 560 __C(CHIP,_io_write_2)(v, ioh, off, val) 561 void *v; 562 bus_space_handle_t ioh; 563 bus_size_t off; 564 u_int16_t val; 565 { 566 register bus_space_handle_t tmpioh; 567 register u_int32_t *port, nval; 568 register int offset; 569 570 tmpioh = ioh + off; 571 offset = tmpioh & 3; 572 nval = val << (8 * offset); 573 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 574 *port = nval; 575 alpha_mb(); 576 } 577 578 inline void 579 __C(CHIP,_io_write_4)(v, ioh, off, val) 580 void *v; 581 bus_space_handle_t ioh; 582 bus_size_t off; 583 u_int32_t val; 584 { 585 register bus_space_handle_t tmpioh; 586 register u_int32_t *port, nval; 587 register int offset; 588 589 tmpioh = ioh + off; 590 offset = tmpioh & 3; 591 nval = val /*<< (8 * offset)*/; 592 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 593 *port = nval; 594 alpha_mb(); 595 } 596 597 inline void 598 __C(CHIP,_io_write_8)(v, ioh, off, val) 599 void *v; 600 bus_space_handle_t ioh; 601 bus_size_t off; 602 u_int64_t val; 603 { 604 605 /* XXX XXX XXX */ 606 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 607 alpha_mb(); 608 } 609 610 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 611 void \ 612 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 613 void *v; \ 614 bus_space_handle_t h; \ 615 bus_size_t o, c; \ 616 const TYPE *a; \ 617 { \ 618 \ 619 while (c-- > 0) { \ 620 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 621 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 622 BUS_BARRIER_WRITE); \ 623 } \ 624 } 625 CHIP_io_write_multi_N(1,u_int8_t) 626 CHIP_io_write_multi_N(2,u_int16_t) 627 CHIP_io_write_multi_N(4,u_int32_t) 628 CHIP_io_write_multi_N(8,u_int64_t) 629 630 #define CHIP_io_write_region_N(BYTES,TYPE) \ 631 void \ 632 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 633 void *v; \ 634 bus_space_handle_t h; \ 635 bus_size_t o, c; \ 636 const TYPE *a; \ 637 { \ 638 \ 639 while (c-- > 0) { \ 640 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 641 o += sizeof *a; \ 642 } \ 643 } 644 CHIP_io_write_region_N(1,u_int8_t) 645 CHIP_io_write_region_N(2,u_int16_t) 646 CHIP_io_write_region_N(4,u_int32_t) 647 CHIP_io_write_region_N(8,u_int64_t) 648 649 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 650 void \ 651 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 652 void *v; \ 653 bus_space_handle_t h; \ 654 bus_size_t o, c; \ 655 TYPE val; \ 656 { \ 657 \ 658 while (c-- > 0) { \ 659 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 660 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 661 BUS_BARRIER_WRITE); \ 662 } \ 663 } 664 CHIP_io_set_multi_N(1,u_int8_t) 665 CHIP_io_set_multi_N(2,u_int16_t) 666 CHIP_io_set_multi_N(4,u_int32_t) 667 CHIP_io_set_multi_N(8,u_int64_t) 668 669 #define CHIP_io_set_region_N(BYTES,TYPE) \ 670 void \ 671 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 672 void *v; \ 673 bus_space_handle_t h; \ 674 bus_size_t o, c; \ 675 TYPE val; \ 676 { \ 677 \ 678 while (c-- > 0) { \ 679 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 680 o += sizeof val; \ 681 } \ 682 } 683 CHIP_io_set_region_N(1,u_int8_t) 684 CHIP_io_set_region_N(2,u_int16_t) 685 CHIP_io_set_region_N(4,u_int32_t) 686 CHIP_io_set_region_N(8,u_int64_t) 687
Indexes created Tue Oct 14 15:09:51 GMT 2025