pci_swiz_bus_io_chipdep.c revision 1.14
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.14 1996/12/02 22:19:35 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #include <sys/extent.h> 40 41 #define __C(A,B) __CONCAT(A,B) 42 #define __S(S) __STRING(S) 43 44 /* mapping/unmapping */ 45 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 46 bus_space_handle_t *)); 47 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 48 bus_size_t)); 49 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 50 bus_size_t, bus_size_t, bus_space_handle_t *)); 51 52 /* allocation/deallocation */ 53 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 54 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 59 /* barrier */ 60 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 61 bus_size_t, bus_size_t, int)); 62 63 /* read (single) */ 64 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 65 bus_size_t)); 66 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 67 bus_size_t)); 68 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 69 bus_size_t)); 70 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 71 bus_size_t)); 72 73 /* read multiple */ 74 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 75 bus_size_t, u_int8_t *, bus_size_t)); 76 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 77 bus_size_t, u_int16_t *, bus_size_t)); 78 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 79 bus_size_t, u_int32_t *, bus_size_t)); 80 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 81 bus_size_t, u_int64_t *, bus_size_t)); 82 83 /* read region */ 84 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 85 bus_size_t, u_int8_t *, bus_size_t)); 86 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 87 bus_size_t, u_int16_t *, bus_size_t)); 88 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 89 bus_size_t, u_int32_t *, bus_size_t)); 90 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 91 bus_size_t, u_int64_t *, bus_size_t)); 92 93 /* write (single) */ 94 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 95 bus_size_t, u_int8_t)); 96 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 97 bus_size_t, u_int16_t)); 98 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 99 bus_size_t, u_int32_t)); 100 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 101 bus_size_t, u_int64_t)); 102 103 /* write multiple */ 104 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 105 bus_size_t, const u_int8_t *, bus_size_t)); 106 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 107 bus_size_t, const u_int16_t *, bus_size_t)); 108 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 109 bus_size_t, const u_int32_t *, bus_size_t)); 110 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 111 bus_size_t, const u_int64_t *, bus_size_t)); 112 113 /* write region */ 114 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 115 bus_size_t, const u_int8_t *, bus_size_t)); 116 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 117 bus_size_t, const u_int16_t *, bus_size_t)); 118 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 119 bus_size_t, const u_int32_t *, bus_size_t)); 120 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 121 bus_size_t, const u_int64_t *, bus_size_t)); 122 123 /* set multiple */ 124 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int8_t, bus_size_t)); 126 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int16_t, bus_size_t)); 128 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 129 bus_size_t, u_int32_t, bus_size_t)); 130 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int64_t, bus_size_t)); 132 133 /* set region */ 134 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int8_t, bus_size_t)); 136 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int16_t, bus_size_t)); 138 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int32_t, bus_size_t)); 140 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int64_t, bus_size_t)); 142 143 /* copy */ 144 void __C(CHIP,_io_copy_1) __P((void *, bus_space_handle_t, 145 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 146 void __C(CHIP,_io_copy_2) __P((void *, bus_space_handle_t, 147 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 148 void __C(CHIP,_io_copy_4) __P((void *, bus_space_handle_t, 149 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 150 void __C(CHIP,_io_copy_8) __P((void *, bus_space_handle_t, 151 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 152 153 static long 154 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 155 156 static struct alpha_bus_space __C(CHIP,_io_space) = { 157 /* cookie */ 158 NULL, 159 160 /* mapping/unmapping */ 161 __C(CHIP,_io_map), 162 __C(CHIP,_io_unmap), 163 __C(CHIP,_io_subregion), 164 165 /* allocation/deallocation */ 166 __C(CHIP,_io_alloc), 167 __C(CHIP,_io_free), 168 169 /* barrier */ 170 __C(CHIP,_io_barrier), 171 172 /* read (single) */ 173 __C(CHIP,_io_read_1), 174 __C(CHIP,_io_read_2), 175 __C(CHIP,_io_read_4), 176 __C(CHIP,_io_read_8), 177 178 /* read multiple */ 179 __C(CHIP,_io_read_multi_1), 180 __C(CHIP,_io_read_multi_2), 181 __C(CHIP,_io_read_multi_4), 182 __C(CHIP,_io_read_multi_8), 183 184 /* read region */ 185 __C(CHIP,_io_read_region_1), 186 __C(CHIP,_io_read_region_2), 187 __C(CHIP,_io_read_region_4), 188 __C(CHIP,_io_read_region_8), 189 190 /* write (single) */ 191 __C(CHIP,_io_write_1), 192 __C(CHIP,_io_write_2), 193 __C(CHIP,_io_write_4), 194 __C(CHIP,_io_write_8), 195 196 /* write multiple */ 197 __C(CHIP,_io_write_multi_1), 198 __C(CHIP,_io_write_multi_2), 199 __C(CHIP,_io_write_multi_4), 200 __C(CHIP,_io_write_multi_8), 201 202 /* write region */ 203 __C(CHIP,_io_write_region_1), 204 __C(CHIP,_io_write_region_2), 205 __C(CHIP,_io_write_region_4), 206 __C(CHIP,_io_write_region_8), 207 208 /* set multiple */ 209 __C(CHIP,_io_set_multi_1), 210 __C(CHIP,_io_set_multi_2), 211 __C(CHIP,_io_set_multi_4), 212 __C(CHIP,_io_set_multi_8), 213 214 /* set region */ 215 __C(CHIP,_io_set_region_1), 216 __C(CHIP,_io_set_region_2), 217 __C(CHIP,_io_set_region_4), 218 __C(CHIP,_io_set_region_8), 219 220 /* copy */ 221 __C(CHIP,_io_copy_1), 222 __C(CHIP,_io_copy_2), 223 __C(CHIP,_io_copy_4), 224 __C(CHIP,_io_copy_8), 225 }; 226 227 bus_space_tag_t 228 __C(CHIP,_bus_io_init)(v) 229 void *v; 230 { 231 bus_space_tag_t t = &__C(CHIP,_io_space); 232 struct extent *ex; 233 234 t->abs_cookie = v; 235 236 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 237 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 238 M_DEVBUF, (caddr_t)__C(CHIP,_io_ex_storage), 239 sizeof(__C(CHIP,_io_ex_storage)), EX_NOWAIT); 240 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 241 242 #ifdef CHIP_IO_W1_BUS_START 243 #ifdef EXTENT_DEBUG 244 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 245 CHIP_IO_W1_BUS_END(v)); 246 #endif 247 extent_free(ex, CHIP_IO_W1_BUS_START(v), 248 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 249 #endif 250 #ifdef CHIP_IO_W2_BUS_START 251 #ifdef EXTENT_DEBUG 252 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 253 CHIP_IO_W2_BUS_END(v)); 254 #endif 255 extent_free(ex, CHIP_IO_W2_BUS_START(v), 256 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 257 #endif 258 259 #ifdef EXTENT_DEBUG 260 extent_print(ex); 261 #endif 262 CHIP_IO_EXTENT(v) = ex; 263 264 return (t); 265 } 266 267 int 268 __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) 269 void *v; 270 bus_addr_t ioaddr; 271 bus_size_t iosize; 272 int cacheable; 273 bus_space_handle_t *iohp; 274 { 275 int error; 276 277 #ifdef EXTENT_DEBUG 278 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 279 #endif 280 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 281 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 282 if (error) { 283 #ifdef EXTENT_DEBUG 284 printf("io: allocation failed (%d)\n", error); 285 extent_print(CHIP_IO_EXTENT(v)); 286 #endif 287 return (error); 288 } 289 290 #ifdef CHIP_IO_W1_BUS_START 291 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 292 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 293 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 294 (ioaddr - CHIP_IO_W1_BUS_START(v)); 295 } else 296 #endif 297 #ifdef CHIP_IO_W2_BUS_START 298 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 299 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 300 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 301 (ioaddr - CHIP_IO_W2_BUS_START(v)); 302 } else 303 #endif 304 { 305 printf("\n"); 306 #ifdef CHIP_IO_W1_BUS_START 307 printf("%s: window[1]=0x%lx-0x%lx\n", 308 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 309 CHIP_IO_W1_BUS_END(v)); 310 #endif 311 #ifdef CHIP_IO_W2_BUS_START 312 printf("%s: window[2]=0x%lx-0x%lx\n", 313 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 314 CHIP_IO_W2_BUS_END(v)); 315 #endif 316 panic("%s: don't know how to map %lx", 317 __S(__C(CHIP,_io_map)), ioaddr); 318 } 319 320 return (0); 321 } 322 323 void 324 __C(CHIP,_io_unmap)(v, ioh, iosize) 325 void *v; 326 bus_space_handle_t ioh; 327 bus_size_t iosize; 328 { 329 bus_addr_t ioaddr; 330 int error; 331 332 #ifdef EXTENT_DEBUG 333 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 334 #endif 335 336 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 337 338 #ifdef CHIP_IO_W1_BUS_START 339 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 340 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 341 ioaddr = CHIP_IO_W1_BUS_START(v) + 342 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 343 } else 344 #endif 345 #ifdef CHIP_IO_W2_BUS_START 346 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 347 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 348 ioaddr = CHIP_IO_W2_BUS_START(v) + 349 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 350 } else 351 #endif 352 { 353 printf("\n"); 354 #ifdef CHIP_IO_W1_BUS_START 355 printf("%s: sys window[1]=0x%lx-0x%lx\n", 356 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 357 CHIP_IO_W1_SYS_END(v)); 358 #endif 359 #ifdef CHIP_IO_W2_BUS_START 360 printf("%s: sys window[2]=0x%lx-0x%lx\n", 361 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 362 CHIP_IO_W2_SYS_END(v)); 363 #endif 364 panic("%s: don't know how to unmap %lx", 365 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 366 } 367 368 #ifdef EXTENT_DEBUG 369 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 370 #endif 371 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 372 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 373 if (error) { 374 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 375 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 376 error); 377 #ifdef EXTENT_DEBUG 378 extent_print(CHIP_IO_EXTENT(v)); 379 #endif 380 } 381 } 382 383 int 384 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 385 void *v; 386 bus_space_handle_t ioh, *nioh; 387 bus_size_t offset, size; 388 { 389 390 *nioh = ioh + offset; 391 return (0); 392 } 393 394 int 395 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, 396 addrp, bshp) 397 void *v; 398 bus_addr_t rstart, rend, *addrp; 399 bus_size_t size, align, boundary; 400 int cacheable; 401 bus_space_handle_t *bshp; 402 { 403 404 /* XXX XXX XXX XXX XXX XXX */ 405 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 406 } 407 408 void 409 __C(CHIP,_io_free)(v, bsh, size) 410 void *v; 411 bus_space_handle_t bsh; 412 bus_size_t size; 413 { 414 415 /* XXX XXX XXX XXX XXX XXX */ 416 panic("%s not implemented", __S(__C(CHIP,_io_free))); 417 } 418 419 inline void 420 __C(CHIP,_io_barrier)(v, h, o, l, f) 421 void *v; 422 bus_space_handle_t h; 423 bus_size_t o, l; 424 int f; 425 { 426 427 if ((f & BUS_BARRIER_READ) != 0) 428 alpha_mb(); 429 else if ((f & BUS_BARRIER_WRITE) != 0) 430 alpha_wmb(); 431 } 432 433 inline u_int8_t 434 __C(CHIP,_io_read_1)(v, ioh, off) 435 void *v; 436 bus_space_handle_t ioh; 437 bus_size_t off; 438 { 439 register bus_space_handle_t tmpioh; 440 register u_int32_t *port, val; 441 register u_int8_t rval; 442 register int offset; 443 444 alpha_mb(); 445 446 tmpioh = ioh + off; 447 offset = tmpioh & 3; 448 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 449 val = *port; 450 rval = ((val) >> (8 * offset)) & 0xff; 451 452 return rval; 453 } 454 455 inline u_int16_t 456 __C(CHIP,_io_read_2)(v, ioh, off) 457 void *v; 458 bus_space_handle_t ioh; 459 bus_size_t off; 460 { 461 register bus_space_handle_t tmpioh; 462 register u_int32_t *port, val; 463 register u_int16_t rval; 464 register int offset; 465 466 alpha_mb(); 467 468 tmpioh = ioh + off; 469 offset = tmpioh & 3; 470 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 471 val = *port; 472 rval = ((val) >> (8 * offset)) & 0xffff; 473 474 return rval; 475 } 476 477 inline u_int32_t 478 __C(CHIP,_io_read_4)(v, ioh, off) 479 void *v; 480 bus_space_handle_t ioh; 481 bus_size_t off; 482 { 483 register bus_space_handle_t tmpioh; 484 register u_int32_t *port, val; 485 register u_int32_t rval; 486 register int offset; 487 488 alpha_mb(); 489 490 tmpioh = ioh + off; 491 offset = tmpioh & 3; 492 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 493 val = *port; 494 #if 0 495 rval = ((val) >> (8 * offset)) & 0xffffffff; 496 #else 497 rval = val; 498 #endif 499 500 return rval; 501 } 502 503 inline u_int64_t 504 __C(CHIP,_io_read_8)(v, ioh, off) 505 void *v; 506 bus_space_handle_t ioh; 507 bus_size_t off; 508 { 509 510 /* XXX XXX XXX */ 511 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 512 } 513 514 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 515 void \ 516 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 517 void *v; \ 518 bus_space_handle_t h; \ 519 bus_size_t o, c; \ 520 TYPE *a; \ 521 { \ 522 \ 523 while (c-- > 0) { \ 524 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 525 BUS_BARRIER_READ); \ 526 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 527 } \ 528 } 529 CHIP_io_read_multi_N(1,u_int8_t) 530 CHIP_io_read_multi_N(2,u_int16_t) 531 CHIP_io_read_multi_N(4,u_int32_t) 532 CHIP_io_read_multi_N(8,u_int64_t) 533 534 #define CHIP_io_read_region_N(BYTES,TYPE) \ 535 void \ 536 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 537 void *v; \ 538 bus_space_handle_t h; \ 539 bus_size_t o, c; \ 540 TYPE *a; \ 541 { \ 542 \ 543 while (c-- > 0) { \ 544 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 545 o += sizeof *a; \ 546 } \ 547 } 548 CHIP_io_read_region_N(1,u_int8_t) 549 CHIP_io_read_region_N(2,u_int16_t) 550 CHIP_io_read_region_N(4,u_int32_t) 551 CHIP_io_read_region_N(8,u_int64_t) 552 553 inline void 554 __C(CHIP,_io_write_1)(v, ioh, off, val) 555 void *v; 556 bus_space_handle_t ioh; 557 bus_size_t off; 558 u_int8_t val; 559 { 560 register bus_space_handle_t tmpioh; 561 register u_int32_t *port, nval; 562 register int offset; 563 564 tmpioh = ioh + off; 565 offset = tmpioh & 3; 566 nval = val << (8 * offset); 567 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 568 *port = nval; 569 alpha_mb(); 570 } 571 572 inline void 573 __C(CHIP,_io_write_2)(v, ioh, off, val) 574 void *v; 575 bus_space_handle_t ioh; 576 bus_size_t off; 577 u_int16_t val; 578 { 579 register bus_space_handle_t tmpioh; 580 register u_int32_t *port, nval; 581 register int offset; 582 583 tmpioh = ioh + off; 584 offset = tmpioh & 3; 585 nval = val << (8 * offset); 586 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 587 *port = nval; 588 alpha_mb(); 589 } 590 591 inline void 592 __C(CHIP,_io_write_4)(v, ioh, off, val) 593 void *v; 594 bus_space_handle_t ioh; 595 bus_size_t off; 596 u_int32_t val; 597 { 598 register bus_space_handle_t tmpioh; 599 register u_int32_t *port, nval; 600 register int offset; 601 602 tmpioh = ioh + off; 603 offset = tmpioh & 3; 604 nval = val /*<< (8 * offset)*/; 605 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 606 *port = nval; 607 alpha_mb(); 608 } 609 610 inline void 611 __C(CHIP,_io_write_8)(v, ioh, off, val) 612 void *v; 613 bus_space_handle_t ioh; 614 bus_size_t off; 615 u_int64_t val; 616 { 617 618 /* XXX XXX XXX */ 619 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 620 alpha_mb(); 621 } 622 623 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 624 void \ 625 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 626 void *v; \ 627 bus_space_handle_t h; \ 628 bus_size_t o, c; \ 629 const TYPE *a; \ 630 { \ 631 \ 632 while (c-- > 0) { \ 633 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 634 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 635 BUS_BARRIER_WRITE); \ 636 } \ 637 } 638 CHIP_io_write_multi_N(1,u_int8_t) 639 CHIP_io_write_multi_N(2,u_int16_t) 640 CHIP_io_write_multi_N(4,u_int32_t) 641 CHIP_io_write_multi_N(8,u_int64_t) 642 643 #define CHIP_io_write_region_N(BYTES,TYPE) \ 644 void \ 645 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 646 void *v; \ 647 bus_space_handle_t h; \ 648 bus_size_t o, c; \ 649 const TYPE *a; \ 650 { \ 651 \ 652 while (c-- > 0) { \ 653 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 654 o += sizeof *a; \ 655 } \ 656 } 657 CHIP_io_write_region_N(1,u_int8_t) 658 CHIP_io_write_region_N(2,u_int16_t) 659 CHIP_io_write_region_N(4,u_int32_t) 660 CHIP_io_write_region_N(8,u_int64_t) 661 662 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 663 void \ 664 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 665 void *v; \ 666 bus_space_handle_t h; \ 667 bus_size_t o, c; \ 668 TYPE val; \ 669 { \ 670 \ 671 while (c-- > 0) { \ 672 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 673 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 674 BUS_BARRIER_WRITE); \ 675 } \ 676 } 677 CHIP_io_set_multi_N(1,u_int8_t) 678 CHIP_io_set_multi_N(2,u_int16_t) 679 CHIP_io_set_multi_N(4,u_int32_t) 680 CHIP_io_set_multi_N(8,u_int64_t) 681 682 #define CHIP_io_set_region_N(BYTES,TYPE) \ 683 void \ 684 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 685 void *v; \ 686 bus_space_handle_t h; \ 687 bus_size_t o, c; \ 688 TYPE val; \ 689 { \ 690 \ 691 while (c-- > 0) { \ 692 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 693 o += sizeof val; \ 694 } \ 695 } 696 CHIP_io_set_region_N(1,u_int8_t) 697 CHIP_io_set_region_N(2,u_int16_t) 698 CHIP_io_set_region_N(4,u_int32_t) 699 CHIP_io_set_region_N(8,u_int64_t) 700 701 #define CHIP_io_copy_N(BYTES) \ 702 void \ 703 __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \ 704 void *v; \ 705 bus_space_handle_t h1, h2; \ 706 bus_size_t o1, o2, c; \ 707 { \ 708 bus_size_t i, o; \ 709 \ 710 for (i = 0, o = 0; i < c; i++, o += BYTES) \ 711 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 712 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 713 } 714 CHIP_io_copy_N(1) 715 CHIP_io_copy_N(2) 716 CHIP_io_copy_N(4) 717 CHIP_io_copy_N(8) 718
Indexes created Tue Oct 14 15:09:51 GMT 2025