pci_swiz_bus_io_chipdep.c revision 1.17
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.17 1997/09/02 10:26:55 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 * CHIP_IO_EX_STORE 38 * If defined, device-provided static storage area 39 * for the I/O space extent. If this is defined, 40 * CHIP_IO_EX_STORE_SIZE must also be defined. If 41 * this is not defined, a static area will be 42 * declared. 43 * CHIP_IO_EX_STORE_SIZE 44 * Size of the device-provided static storage area 45 * for the I/O memory space extent. 46 */ 47 48 #include <sys/extent.h> 49 50 #define __C(A,B) __CONCAT(A,B) 51 #define __S(S) __STRING(S) 52 53 /* mapping/unmapping */ 54 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 59 bus_size_t, bus_size_t, bus_space_handle_t *)); 60 61 /* allocation/deallocation */ 62 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 63 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 64 bus_space_handle_t *)); 65 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 66 bus_size_t)); 67 68 /* barrier */ 69 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 70 bus_size_t, bus_size_t, int)); 71 72 /* read (single) */ 73 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 74 bus_size_t)); 75 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 76 bus_size_t)); 77 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 78 bus_size_t)); 79 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 80 bus_size_t)); 81 82 /* read multiple */ 83 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 84 bus_size_t, u_int8_t *, bus_size_t)); 85 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 86 bus_size_t, u_int16_t *, bus_size_t)); 87 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 88 bus_size_t, u_int32_t *, bus_size_t)); 89 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 90 bus_size_t, u_int64_t *, bus_size_t)); 91 92 /* read region */ 93 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 94 bus_size_t, u_int8_t *, bus_size_t)); 95 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 96 bus_size_t, u_int16_t *, bus_size_t)); 97 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 98 bus_size_t, u_int32_t *, bus_size_t)); 99 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 100 bus_size_t, u_int64_t *, bus_size_t)); 101 102 /* write (single) */ 103 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 104 bus_size_t, u_int8_t)); 105 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 106 bus_size_t, u_int16_t)); 107 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 108 bus_size_t, u_int32_t)); 109 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 110 bus_size_t, u_int64_t)); 111 112 /* write multiple */ 113 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 114 bus_size_t, const u_int8_t *, bus_size_t)); 115 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 116 bus_size_t, const u_int16_t *, bus_size_t)); 117 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 118 bus_size_t, const u_int32_t *, bus_size_t)); 119 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 120 bus_size_t, const u_int64_t *, bus_size_t)); 121 122 /* write region */ 123 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 124 bus_size_t, const u_int8_t *, bus_size_t)); 125 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 126 bus_size_t, const u_int16_t *, bus_size_t)); 127 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 128 bus_size_t, const u_int32_t *, bus_size_t)); 129 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 130 bus_size_t, const u_int64_t *, bus_size_t)); 131 132 /* set multiple */ 133 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t, bus_size_t)); 135 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t, bus_size_t)); 137 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t, bus_size_t)); 139 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t, bus_size_t)); 141 142 /* set region */ 143 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t, bus_size_t)); 145 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t, bus_size_t)); 147 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t, bus_size_t)); 149 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t, bus_size_t)); 151 152 /* copy */ 153 void __C(CHIP,_io_copy_1) __P((void *, bus_space_handle_t, 154 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 155 void __C(CHIP,_io_copy_2) __P((void *, bus_space_handle_t, 156 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 157 void __C(CHIP,_io_copy_4) __P((void *, bus_space_handle_t, 158 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 159 void __C(CHIP,_io_copy_8) __P((void *, bus_space_handle_t, 160 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 161 162 #ifndef CHIP_IO_EX_STORE 163 static long 164 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 165 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 166 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 167 #endif 168 169 static struct alpha_bus_space __C(CHIP,_io_space) = { 170 /* cookie */ 171 NULL, 172 173 /* mapping/unmapping */ 174 __C(CHIP,_io_map), 175 __C(CHIP,_io_unmap), 176 __C(CHIP,_io_subregion), 177 178 /* allocation/deallocation */ 179 __C(CHIP,_io_alloc), 180 __C(CHIP,_io_free), 181 182 /* barrier */ 183 __C(CHIP,_io_barrier), 184 185 /* read (single) */ 186 __C(CHIP,_io_read_1), 187 __C(CHIP,_io_read_2), 188 __C(CHIP,_io_read_4), 189 __C(CHIP,_io_read_8), 190 191 /* read multiple */ 192 __C(CHIP,_io_read_multi_1), 193 __C(CHIP,_io_read_multi_2), 194 __C(CHIP,_io_read_multi_4), 195 __C(CHIP,_io_read_multi_8), 196 197 /* read region */ 198 __C(CHIP,_io_read_region_1), 199 __C(CHIP,_io_read_region_2), 200 __C(CHIP,_io_read_region_4), 201 __C(CHIP,_io_read_region_8), 202 203 /* write (single) */ 204 __C(CHIP,_io_write_1), 205 __C(CHIP,_io_write_2), 206 __C(CHIP,_io_write_4), 207 __C(CHIP,_io_write_8), 208 209 /* write multiple */ 210 __C(CHIP,_io_write_multi_1), 211 __C(CHIP,_io_write_multi_2), 212 __C(CHIP,_io_write_multi_4), 213 __C(CHIP,_io_write_multi_8), 214 215 /* write region */ 216 __C(CHIP,_io_write_region_1), 217 __C(CHIP,_io_write_region_2), 218 __C(CHIP,_io_write_region_4), 219 __C(CHIP,_io_write_region_8), 220 221 /* set multiple */ 222 __C(CHIP,_io_set_multi_1), 223 __C(CHIP,_io_set_multi_2), 224 __C(CHIP,_io_set_multi_4), 225 __C(CHIP,_io_set_multi_8), 226 227 /* set region */ 228 __C(CHIP,_io_set_region_1), 229 __C(CHIP,_io_set_region_2), 230 __C(CHIP,_io_set_region_4), 231 __C(CHIP,_io_set_region_8), 232 233 /* copy */ 234 __C(CHIP,_io_copy_1), 235 __C(CHIP,_io_copy_2), 236 __C(CHIP,_io_copy_4), 237 __C(CHIP,_io_copy_8), 238 }; 239 240 bus_space_tag_t 241 __C(CHIP,_bus_io_init)(v) 242 void *v; 243 { 244 bus_space_tag_t t = &__C(CHIP,_io_space); 245 struct extent *ex; 246 247 t->abs_cookie = v; 248 249 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 250 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 251 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 252 EX_NOWAIT); 253 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 254 255 #ifdef CHIP_IO_W1_BUS_START 256 #ifdef EXTENT_DEBUG 257 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 258 CHIP_IO_W1_BUS_END(v)); 259 #endif 260 extent_free(ex, CHIP_IO_W1_BUS_START(v), 261 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 262 #endif 263 #ifdef CHIP_IO_W2_BUS_START 264 #ifdef EXTENT_DEBUG 265 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 266 CHIP_IO_W2_BUS_END(v)); 267 #endif 268 extent_free(ex, CHIP_IO_W2_BUS_START(v), 269 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 270 #endif 271 272 #ifdef EXTENT_DEBUG 273 extent_print(ex); 274 #endif 275 CHIP_IO_EXTENT(v) = ex; 276 277 return (t); 278 } 279 280 int 281 __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) 282 void *v; 283 bus_addr_t ioaddr; 284 bus_size_t iosize; 285 int cacheable; 286 bus_space_handle_t *iohp; 287 { 288 int error; 289 290 #ifdef EXTENT_DEBUG 291 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 292 #endif 293 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 294 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 295 if (error) { 296 #ifdef EXTENT_DEBUG 297 printf("io: allocation failed (%d)\n", error); 298 extent_print(CHIP_IO_EXTENT(v)); 299 #endif 300 return (error); 301 } 302 303 #ifdef CHIP_IO_W1_BUS_START 304 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 305 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 306 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 307 (ioaddr - CHIP_IO_W1_BUS_START(v)); 308 } else 309 #endif 310 #ifdef CHIP_IO_W2_BUS_START 311 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 312 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 313 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 314 (ioaddr - CHIP_IO_W2_BUS_START(v)); 315 } else 316 #endif 317 { 318 printf("\n"); 319 #ifdef CHIP_IO_W1_BUS_START 320 printf("%s: window[1]=0x%lx-0x%lx\n", 321 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 322 CHIP_IO_W1_BUS_END(v)); 323 #endif 324 #ifdef CHIP_IO_W2_BUS_START 325 printf("%s: window[2]=0x%lx-0x%lx\n", 326 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 327 CHIP_IO_W2_BUS_END(v)); 328 #endif 329 panic("%s: don't know how to map %lx", 330 __S(__C(CHIP,_io_map)), ioaddr); 331 } 332 333 return (0); 334 } 335 336 void 337 __C(CHIP,_io_unmap)(v, ioh, iosize) 338 void *v; 339 bus_space_handle_t ioh; 340 bus_size_t iosize; 341 { 342 bus_addr_t ioaddr; 343 int error; 344 345 #ifdef EXTENT_DEBUG 346 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 347 #endif 348 349 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 350 351 #ifdef CHIP_IO_W1_BUS_START 352 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 353 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 354 ioaddr = CHIP_IO_W1_BUS_START(v) + 355 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 356 } else 357 #endif 358 #ifdef CHIP_IO_W2_BUS_START 359 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 360 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 361 ioaddr = CHIP_IO_W2_BUS_START(v) + 362 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 363 } else 364 #endif 365 { 366 printf("\n"); 367 #ifdef CHIP_IO_W1_BUS_START 368 printf("%s: sys window[1]=0x%lx-0x%lx\n", 369 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 370 CHIP_IO_W1_SYS_END(v)); 371 #endif 372 #ifdef CHIP_IO_W2_BUS_START 373 printf("%s: sys window[2]=0x%lx-0x%lx\n", 374 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 375 CHIP_IO_W2_SYS_END(v)); 376 #endif 377 panic("%s: don't know how to unmap %lx", 378 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 379 } 380 381 #ifdef EXTENT_DEBUG 382 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 383 #endif 384 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 385 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 386 if (error) { 387 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 388 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 389 error); 390 #ifdef EXTENT_DEBUG 391 extent_print(CHIP_IO_EXTENT(v)); 392 #endif 393 } 394 } 395 396 int 397 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 398 void *v; 399 bus_space_handle_t ioh, *nioh; 400 bus_size_t offset, size; 401 { 402 403 *nioh = ioh + offset; 404 return (0); 405 } 406 407 int 408 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, 409 addrp, bshp) 410 void *v; 411 bus_addr_t rstart, rend, *addrp; 412 bus_size_t size, align, boundary; 413 int cacheable; 414 bus_space_handle_t *bshp; 415 { 416 417 /* XXX XXX XXX XXX XXX XXX */ 418 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 419 } 420 421 void 422 __C(CHIP,_io_free)(v, bsh, size) 423 void *v; 424 bus_space_handle_t bsh; 425 bus_size_t size; 426 { 427 428 /* XXX XXX XXX XXX XXX XXX */ 429 panic("%s not implemented", __S(__C(CHIP,_io_free))); 430 } 431 432 inline void 433 __C(CHIP,_io_barrier)(v, h, o, l, f) 434 void *v; 435 bus_space_handle_t h; 436 bus_size_t o, l; 437 int f; 438 { 439 440 if ((f & BUS_BARRIER_READ) != 0) 441 alpha_mb(); 442 else if ((f & BUS_BARRIER_WRITE) != 0) 443 alpha_wmb(); 444 } 445 446 inline u_int8_t 447 __C(CHIP,_io_read_1)(v, ioh, off) 448 void *v; 449 bus_space_handle_t ioh; 450 bus_size_t off; 451 { 452 register bus_space_handle_t tmpioh; 453 register u_int32_t *port, val; 454 register u_int8_t rval; 455 register int offset; 456 457 alpha_mb(); 458 459 tmpioh = ioh + off; 460 offset = tmpioh & 3; 461 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 462 val = *port; 463 rval = ((val) >> (8 * offset)) & 0xff; 464 465 return rval; 466 } 467 468 inline u_int16_t 469 __C(CHIP,_io_read_2)(v, ioh, off) 470 void *v; 471 bus_space_handle_t ioh; 472 bus_size_t off; 473 { 474 register bus_space_handle_t tmpioh; 475 register u_int32_t *port, val; 476 register u_int16_t rval; 477 register int offset; 478 479 alpha_mb(); 480 481 tmpioh = ioh + off; 482 offset = tmpioh & 3; 483 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 484 val = *port; 485 rval = ((val) >> (8 * offset)) & 0xffff; 486 487 return rval; 488 } 489 490 inline u_int32_t 491 __C(CHIP,_io_read_4)(v, ioh, off) 492 void *v; 493 bus_space_handle_t ioh; 494 bus_size_t off; 495 { 496 register bus_space_handle_t tmpioh; 497 register u_int32_t *port, val; 498 register u_int32_t rval; 499 register int offset; 500 501 alpha_mb(); 502 503 tmpioh = ioh + off; 504 offset = tmpioh & 3; 505 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 506 val = *port; 507 #if 0 508 rval = ((val) >> (8 * offset)) & 0xffffffff; 509 #else 510 rval = val; 511 #endif 512 513 return rval; 514 } 515 516 inline u_int64_t 517 __C(CHIP,_io_read_8)(v, ioh, off) 518 void *v; 519 bus_space_handle_t ioh; 520 bus_size_t off; 521 { 522 523 /* XXX XXX XXX */ 524 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 525 } 526 527 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 528 void \ 529 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 530 void *v; \ 531 bus_space_handle_t h; \ 532 bus_size_t o, c; \ 533 TYPE *a; \ 534 { \ 535 \ 536 while (c-- > 0) { \ 537 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 538 BUS_BARRIER_READ); \ 539 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 540 } \ 541 } 542 CHIP_io_read_multi_N(1,u_int8_t) 543 CHIP_io_read_multi_N(2,u_int16_t) 544 CHIP_io_read_multi_N(4,u_int32_t) 545 CHIP_io_read_multi_N(8,u_int64_t) 546 547 #define CHIP_io_read_region_N(BYTES,TYPE) \ 548 void \ 549 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 550 void *v; \ 551 bus_space_handle_t h; \ 552 bus_size_t o, c; \ 553 TYPE *a; \ 554 { \ 555 \ 556 while (c-- > 0) { \ 557 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 558 o += sizeof *a; \ 559 } \ 560 } 561 CHIP_io_read_region_N(1,u_int8_t) 562 CHIP_io_read_region_N(2,u_int16_t) 563 CHIP_io_read_region_N(4,u_int32_t) 564 CHIP_io_read_region_N(8,u_int64_t) 565 566 inline void 567 __C(CHIP,_io_write_1)(v, ioh, off, val) 568 void *v; 569 bus_space_handle_t ioh; 570 bus_size_t off; 571 u_int8_t val; 572 { 573 register bus_space_handle_t tmpioh; 574 register u_int32_t *port, nval; 575 register int offset; 576 577 tmpioh = ioh + off; 578 offset = tmpioh & 3; 579 nval = val << (8 * offset); 580 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 581 *port = nval; 582 alpha_mb(); 583 } 584 585 inline void 586 __C(CHIP,_io_write_2)(v, ioh, off, val) 587 void *v; 588 bus_space_handle_t ioh; 589 bus_size_t off; 590 u_int16_t val; 591 { 592 register bus_space_handle_t tmpioh; 593 register u_int32_t *port, nval; 594 register int offset; 595 596 tmpioh = ioh + off; 597 offset = tmpioh & 3; 598 nval = val << (8 * offset); 599 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 600 *port = nval; 601 alpha_mb(); 602 } 603 604 inline void 605 __C(CHIP,_io_write_4)(v, ioh, off, val) 606 void *v; 607 bus_space_handle_t ioh; 608 bus_size_t off; 609 u_int32_t val; 610 { 611 register bus_space_handle_t tmpioh; 612 register u_int32_t *port, nval; 613 register int offset; 614 615 tmpioh = ioh + off; 616 offset = tmpioh & 3; 617 nval = val /*<< (8 * offset)*/; 618 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 619 *port = nval; 620 alpha_mb(); 621 } 622 623 inline void 624 __C(CHIP,_io_write_8)(v, ioh, off, val) 625 void *v; 626 bus_space_handle_t ioh; 627 bus_size_t off; 628 u_int64_t val; 629 { 630 631 /* XXX XXX XXX */ 632 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 633 alpha_mb(); 634 } 635 636 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 637 void \ 638 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 639 void *v; \ 640 bus_space_handle_t h; \ 641 bus_size_t o, c; \ 642 const TYPE *a; \ 643 { \ 644 \ 645 while (c-- > 0) { \ 646 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 647 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 648 BUS_BARRIER_WRITE); \ 649 } \ 650 } 651 CHIP_io_write_multi_N(1,u_int8_t) 652 CHIP_io_write_multi_N(2,u_int16_t) 653 CHIP_io_write_multi_N(4,u_int32_t) 654 CHIP_io_write_multi_N(8,u_int64_t) 655 656 #define CHIP_io_write_region_N(BYTES,TYPE) \ 657 void \ 658 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 659 void *v; \ 660 bus_space_handle_t h; \ 661 bus_size_t o, c; \ 662 const TYPE *a; \ 663 { \ 664 \ 665 while (c-- > 0) { \ 666 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 667 o += sizeof *a; \ 668 } \ 669 } 670 CHIP_io_write_region_N(1,u_int8_t) 671 CHIP_io_write_region_N(2,u_int16_t) 672 CHIP_io_write_region_N(4,u_int32_t) 673 CHIP_io_write_region_N(8,u_int64_t) 674 675 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 676 void \ 677 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 678 void *v; \ 679 bus_space_handle_t h; \ 680 bus_size_t o, c; \ 681 TYPE val; \ 682 { \ 683 \ 684 while (c-- > 0) { \ 685 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 686 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 687 BUS_BARRIER_WRITE); \ 688 } \ 689 } 690 CHIP_io_set_multi_N(1,u_int8_t) 691 CHIP_io_set_multi_N(2,u_int16_t) 692 CHIP_io_set_multi_N(4,u_int32_t) 693 CHIP_io_set_multi_N(8,u_int64_t) 694 695 #define CHIP_io_set_region_N(BYTES,TYPE) \ 696 void \ 697 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 698 void *v; \ 699 bus_space_handle_t h; \ 700 bus_size_t o, c; \ 701 TYPE val; \ 702 { \ 703 \ 704 while (c-- > 0) { \ 705 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 706 o += sizeof val; \ 707 } \ 708 } 709 CHIP_io_set_region_N(1,u_int8_t) 710 CHIP_io_set_region_N(2,u_int16_t) 711 CHIP_io_set_region_N(4,u_int32_t) 712 CHIP_io_set_region_N(8,u_int64_t) 713 714 #define CHIP_io_copy_N(BYTES) \ 715 void \ 716 __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \ 717 void *v; \ 718 bus_space_handle_t h1, h2; \ 719 bus_size_t o1, o2, c; \ 720 { \ 721 bus_size_t i, o; \ 722 \ 723 for (i = 0, o = 0; i < c; i++, o += BYTES) \ 724 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 725 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 726 } 727 CHIP_io_copy_N(1) 728 CHIP_io_copy_N(2) 729 CHIP_io_copy_N(4) 730 CHIP_io_copy_N(8) 731
Indexes created Tue Oct 14 01:09:49 GMT 2025