pci_swiz_bus_io_chipdep.c revision 1.2
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.2 1996/04/18 05:53:04 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #define __C(A,B) __CONCAT(A,B) 40 41 int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, 42 bus_io_handle_t *)); 43 void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, 44 bus_io_size_t)); 45 u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, 46 bus_io_size_t)); 47 u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, 48 bus_io_size_t)); 49 u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, 50 bus_io_size_t)); 51 u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, 52 bus_io_size_t)); 53 void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t, 54 bus_io_size_t, u_int8_t *, bus_io_size_t)); 55 void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t, 56 bus_io_size_t, u_int16_t *, bus_io_size_t)); 57 void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t, 58 bus_io_size_t, u_int32_t *, bus_io_size_t)); 59 void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t, 60 bus_io_size_t, u_int64_t *, bus_io_size_t)); 61 void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, 62 bus_io_size_t, u_int8_t)); 63 void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, 64 bus_io_size_t, u_int16_t)); 65 void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, 66 bus_io_size_t, u_int32_t)); 67 void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, 68 bus_io_size_t, u_int64_t)); 69 void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t, 70 bus_io_size_t, const u_int8_t *, bus_io_size_t)); 71 void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t, 72 bus_io_size_t, const u_int16_t *, bus_io_size_t)); 73 void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t, 74 bus_io_size_t, const u_int32_t *, bus_io_size_t)); 75 void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t, 76 bus_io_size_t, const u_int64_t *, bus_io_size_t)); 77 78 void 79 __C(CHIP,_bus_io_init)(bc, iov) 80 bus_chipset_tag_t bc; 81 void *iov; 82 { 83 84 bc->bc_i_v = iov; 85 86 bc->bc_i_map = __C(CHIP,_io_map); 87 bc->bc_i_unmap = __C(CHIP,_io_unmap); 88 89 bc->bc_ir1 = __C(CHIP,_io_read_1); 90 bc->bc_ir2 = __C(CHIP,_io_read_2); 91 bc->bc_ir4 = __C(CHIP,_io_read_4); 92 bc->bc_ir8 = __C(CHIP,_io_read_8); 93 94 bc->bc_irm1 = __C(CHIP,_io_read_multi_1); 95 bc->bc_irm2 = __C(CHIP,_io_read_multi_2); 96 bc->bc_irm4 = __C(CHIP,_io_read_multi_4); 97 bc->bc_irm8 = __C(CHIP,_io_read_multi_8); 98 99 bc->bc_iw1 = __C(CHIP,_io_write_1); 100 bc->bc_iw2 = __C(CHIP,_io_write_2); 101 bc->bc_iw4 = __C(CHIP,_io_write_4); 102 bc->bc_iw8 = __C(CHIP,_io_write_8); 103 104 bc->bc_iwm1 = __C(CHIP,_io_write_multi_1); 105 bc->bc_iwm2 = __C(CHIP,_io_write_multi_2); 106 bc->bc_iwm4 = __C(CHIP,_io_write_multi_4); 107 bc->bc_iwm8 = __C(CHIP,_io_write_multi_8); 108 } 109 110 int 111 __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) 112 void *v; 113 bus_io_addr_t ioaddr; 114 bus_io_size_t iosize; 115 bus_io_handle_t *iohp; 116 { 117 118 *iohp = (phystok0seg(CHIP_IO_BASE) >> 5) + ioaddr; 119 return (0); 120 } 121 122 void 123 __C(CHIP,_io_unmap)(v, ioh, iosize) 124 void *v; 125 bus_io_handle_t ioh; 126 bus_io_size_t iosize; 127 { 128 129 /* XXX nothing to do. */ 130 } 131 132 u_int8_t 133 __C(CHIP,_io_read_1)(v, ioh, off) 134 void *v; 135 bus_io_handle_t ioh; 136 bus_io_size_t off; 137 { 138 register bus_io_handle_t tmpioh; 139 register u_int32_t *port, val; 140 register u_int8_t rval; 141 register int offset; 142 143 wbflush(); 144 145 tmpioh = ioh + off; 146 offset = tmpioh & 3; 147 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 148 val = *port; 149 rval = ((val) >> (8 * offset)) & 0xff; 150 151 return rval; 152 } 153 154 u_int16_t 155 __C(CHIP,_io_read_2)(v, ioh, off) 156 void *v; 157 bus_io_handle_t ioh; 158 bus_io_size_t off; 159 { 160 register bus_io_handle_t tmpioh; 161 register u_int32_t *port, val; 162 register u_int16_t rval; 163 register int offset; 164 165 wbflush(); 166 167 tmpioh = ioh + off; 168 offset = tmpioh & 3; 169 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 170 val = *port; 171 rval = ((val) >> (8 * offset)) & 0xffff; 172 173 return rval; 174 } 175 176 u_int32_t 177 __C(CHIP,_io_read_4)(v, ioh, off) 178 void *v; 179 bus_io_handle_t ioh; 180 bus_io_size_t off; 181 { 182 register bus_io_handle_t tmpioh; 183 register u_int32_t *port, val; 184 register u_int32_t rval; 185 register int offset; 186 187 wbflush(); 188 189 tmpioh = ioh + off; 190 offset = tmpioh & 3; 191 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 192 val = *port; 193 #if 0 194 rval = ((val) >> (8 * offset)) & 0xffffffff; 195 #else 196 rval = val; 197 #endif 198 199 return rval; 200 } 201 202 u_int64_t 203 __C(CHIP,_io_read_8)(v, ioh, off) 204 void *v; 205 bus_io_handle_t ioh; 206 bus_io_size_t off; 207 { 208 209 /* XXX XXX XXX */ 210 panic("%s not implemented\n", __STRING(__C(CHIP,_io_read_8))); 211 } 212 213 void 214 __C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count) 215 void *v; 216 bus_io_handle_t ioh; 217 bus_io_size_t off, count; 218 u_int8_t *addr; 219 { 220 register bus_io_handle_t tmpioh; 221 register u_int32_t *port, val; 222 register int offset; 223 224 wbflush(); 225 226 while (count--) { 227 tmpioh = ioh + off; 228 offset = tmpioh & 3; 229 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 230 val = *port; 231 *addr++ = ((val) >> (8 * offset)) & 0xff; 232 off++; 233 } 234 } 235 236 void 237 __C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count) 238 void *v; 239 bus_io_handle_t ioh; 240 bus_io_size_t off, count; 241 u_int16_t *addr; 242 { 243 register bus_io_handle_t tmpioh; 244 register u_int32_t *port, val; 245 register int offset; 246 247 wbflush(); 248 249 while (count--) { 250 tmpioh = ioh + off; 251 offset = tmpioh & 3; 252 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 253 val = *port; 254 *addr++ = ((val) >> (8 * offset)) & 0xffff; 255 off++; 256 } 257 } 258 259 void 260 __C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count) 261 void *v; 262 bus_io_handle_t ioh; 263 bus_io_size_t off, count; 264 u_int32_t *addr; 265 { 266 register bus_io_handle_t tmpioh; 267 register u_int32_t *port, val; 268 register int offset; 269 270 wbflush(); 271 272 while (count--) { 273 tmpioh = ioh + off; 274 offset = tmpioh & 3; 275 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 276 val = *port; 277 #if 0 278 *addr++ = ((val) >> (8 * offset)) & 0xffffffff; 279 #else 280 *addr++ = val; 281 #endif 282 off++; 283 } 284 } 285 286 void 287 __C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count) 288 void *v; 289 bus_io_handle_t ioh; 290 bus_io_size_t off, count; 291 u_int64_t *addr; 292 { 293 294 /* XXX XXX XXX */ 295 panic("%s not implemented\n", __STRING(__C(CHIP,_io_read_multi_8))); 296 } 297 298 void 299 __C(CHIP,_io_write_1)(v, ioh, off, val) 300 void *v; 301 bus_io_handle_t ioh; 302 bus_io_size_t off; 303 u_int8_t val; 304 { 305 register bus_io_handle_t tmpioh; 306 register u_int32_t *port, nval; 307 register int offset; 308 309 tmpioh = ioh + off; 310 offset = tmpioh & 3; 311 nval = val << (8 * offset); 312 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 313 *port = nval; 314 wbflush(); 315 } 316 317 void 318 __C(CHIP,_io_write_2)(v, ioh, off, val) 319 void *v; 320 bus_io_handle_t ioh; 321 bus_io_size_t off; 322 u_int16_t val; 323 { 324 register bus_io_handle_t tmpioh; 325 register u_int32_t *port, nval; 326 register int offset; 327 328 tmpioh = ioh + off; 329 offset = tmpioh & 3; 330 nval = val << (8 * offset); 331 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 332 *port = nval; 333 wbflush(); 334 } 335 336 void 337 __C(CHIP,_io_write_4)(v, ioh, off, val) 338 void *v; 339 bus_io_handle_t ioh; 340 bus_io_size_t off; 341 u_int32_t val; 342 { 343 register bus_io_handle_t tmpioh; 344 register u_int32_t *port, nval; 345 register int offset; 346 347 tmpioh = ioh + off; 348 offset = tmpioh & 3; 349 nval = val /*<< (8 * offset)*/; 350 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 351 *port = nval; 352 wbflush(); 353 } 354 355 void 356 __C(CHIP,_io_write_8)(v, ioh, off, val) 357 void *v; 358 bus_io_handle_t ioh; 359 bus_io_size_t off; 360 u_int64_t val; 361 { 362 363 /* XXX XXX XXX */ 364 panic("%s not implemented\n", __STRING(__C(CHIP,_io_write_8))); 365 wbflush(); 366 } 367 368 void 369 __C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count) 370 void *v; 371 bus_io_handle_t ioh; 372 bus_io_size_t off, count; 373 const u_int8_t *addr; 374 { 375 register bus_io_handle_t tmpioh; 376 register u_int32_t *port, nval; 377 register int offset; 378 379 while (count--) { 380 tmpioh = ioh + off; 381 offset = tmpioh & 3; 382 nval = (*addr++) << (8 * offset); 383 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 384 *port = nval; 385 off++; 386 } 387 wbflush(); 388 } 389 390 void 391 __C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count) 392 void *v; 393 bus_io_handle_t ioh; 394 bus_io_size_t off, count; 395 const u_int16_t *addr; 396 { 397 register bus_io_handle_t tmpioh; 398 register u_int32_t *port, nval; 399 register int offset; 400 401 while (count--) { 402 tmpioh = ioh + off; 403 offset = tmpioh & 3; 404 nval = (*addr++) << (8 * offset); 405 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 406 *port = nval; 407 off++; 408 } 409 wbflush(); 410 } 411 412 void 413 __C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count) 414 void *v; 415 bus_io_handle_t ioh; 416 bus_io_size_t off, count; 417 const u_int32_t *addr; 418 { 419 register bus_io_handle_t tmpioh; 420 register u_int32_t *port, nval; 421 register int offset; 422 423 while (count--) { 424 tmpioh = ioh + off; 425 offset = tmpioh & 3; 426 nval = (*addr++) /*<< (8 * offset)*/; 427 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 428 *port = nval; 429 off++; 430 } 431 wbflush(); 432 } 433 434 void 435 __C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count) 436 void *v; 437 bus_io_handle_t ioh; 438 bus_io_size_t off, count; 439 const u_int64_t *addr; 440 { 441 442 /* XXX XXX XXX */ 443 panic("%s not implemented\n", __STRING(__C(CHIP,_io_write_multi_8))); 444 } 445
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