pci_swiz_bus_io_chipdep.c revision 1.2.4.1
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.2.4.1 1996/06/09 23:51:03 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #define __C(A,B) __CONCAT(A,B) 40 #define __S(S) __STRING(S) 41 42 int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, 43 bus_io_handle_t *)); 44 void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, 45 bus_io_size_t)); 46 u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, 47 bus_io_size_t)); 48 u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, 49 bus_io_size_t)); 50 u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, 51 bus_io_size_t)); 52 u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, 53 bus_io_size_t)); 54 void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t, 55 bus_io_size_t, u_int8_t *, bus_io_size_t)); 56 void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t, 57 bus_io_size_t, u_int16_t *, bus_io_size_t)); 58 void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t, 59 bus_io_size_t, u_int32_t *, bus_io_size_t)); 60 void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t, 61 bus_io_size_t, u_int64_t *, bus_io_size_t)); 62 void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, 63 bus_io_size_t, u_int8_t)); 64 void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, 65 bus_io_size_t, u_int16_t)); 66 void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, 67 bus_io_size_t, u_int32_t)); 68 void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, 69 bus_io_size_t, u_int64_t)); 70 void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t, 71 bus_io_size_t, const u_int8_t *, bus_io_size_t)); 72 void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t, 73 bus_io_size_t, const u_int16_t *, bus_io_size_t)); 74 void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t, 75 bus_io_size_t, const u_int32_t *, bus_io_size_t)); 76 void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t, 77 bus_io_size_t, const u_int64_t *, bus_io_size_t)); 78 79 void 80 __C(CHIP,_bus_io_init)(bc, iov) 81 bus_chipset_tag_t bc; 82 void *iov; 83 { 84 85 bc->bc_i_v = iov; 86 87 bc->bc_i_map = __C(CHIP,_io_map); 88 bc->bc_i_unmap = __C(CHIP,_io_unmap); 89 90 bc->bc_ir1 = __C(CHIP,_io_read_1); 91 bc->bc_ir2 = __C(CHIP,_io_read_2); 92 bc->bc_ir4 = __C(CHIP,_io_read_4); 93 bc->bc_ir8 = __C(CHIP,_io_read_8); 94 95 bc->bc_irm1 = __C(CHIP,_io_read_multi_1); 96 bc->bc_irm2 = __C(CHIP,_io_read_multi_2); 97 bc->bc_irm4 = __C(CHIP,_io_read_multi_4); 98 bc->bc_irm8 = __C(CHIP,_io_read_multi_8); 99 100 bc->bc_iw1 = __C(CHIP,_io_write_1); 101 bc->bc_iw2 = __C(CHIP,_io_write_2); 102 bc->bc_iw4 = __C(CHIP,_io_write_4); 103 bc->bc_iw8 = __C(CHIP,_io_write_8); 104 105 bc->bc_iwm1 = __C(CHIP,_io_write_multi_1); 106 bc->bc_iwm2 = __C(CHIP,_io_write_multi_2); 107 bc->bc_iwm4 = __C(CHIP,_io_write_multi_4); 108 bc->bc_iwm8 = __C(CHIP,_io_write_multi_8); 109 } 110 111 int 112 __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) 113 void *v; 114 bus_io_addr_t ioaddr; 115 bus_io_size_t iosize; 116 bus_io_handle_t *iohp; 117 { 118 119 *iohp = (phystok0seg(CHIP_IO_BASE) >> 5) + ioaddr; 120 return (0); 121 } 122 123 void 124 __C(CHIP,_io_unmap)(v, ioh, iosize) 125 void *v; 126 bus_io_handle_t ioh; 127 bus_io_size_t iosize; 128 { 129 130 /* XXX nothing to do. */ 131 } 132 133 u_int8_t 134 __C(CHIP,_io_read_1)(v, ioh, off) 135 void *v; 136 bus_io_handle_t ioh; 137 bus_io_size_t off; 138 { 139 register bus_io_handle_t tmpioh; 140 register u_int32_t *port, val; 141 register u_int8_t rval; 142 register int offset; 143 144 wbflush(); 145 146 tmpioh = ioh + off; 147 offset = tmpioh & 3; 148 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 149 val = *port; 150 rval = ((val) >> (8 * offset)) & 0xff; 151 152 return rval; 153 } 154 155 u_int16_t 156 __C(CHIP,_io_read_2)(v, ioh, off) 157 void *v; 158 bus_io_handle_t ioh; 159 bus_io_size_t off; 160 { 161 register bus_io_handle_t tmpioh; 162 register u_int32_t *port, val; 163 register u_int16_t rval; 164 register int offset; 165 166 wbflush(); 167 168 tmpioh = ioh + off; 169 offset = tmpioh & 3; 170 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 171 val = *port; 172 rval = ((val) >> (8 * offset)) & 0xffff; 173 174 return rval; 175 } 176 177 u_int32_t 178 __C(CHIP,_io_read_4)(v, ioh, off) 179 void *v; 180 bus_io_handle_t ioh; 181 bus_io_size_t off; 182 { 183 register bus_io_handle_t tmpioh; 184 register u_int32_t *port, val; 185 register u_int32_t rval; 186 register int offset; 187 188 wbflush(); 189 190 tmpioh = ioh + off; 191 offset = tmpioh & 3; 192 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 193 val = *port; 194 #if 0 195 rval = ((val) >> (8 * offset)) & 0xffffffff; 196 #else 197 rval = val; 198 #endif 199 200 return rval; 201 } 202 203 u_int64_t 204 __C(CHIP,_io_read_8)(v, ioh, off) 205 void *v; 206 bus_io_handle_t ioh; 207 bus_io_size_t off; 208 { 209 210 /* XXX XXX XXX */ 211 panic("%s not implemented\n", __S(__C(CHIP,_io_read_8))); 212 } 213 214 void 215 __C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count) 216 void *v; 217 bus_io_handle_t ioh; 218 bus_io_size_t off, count; 219 u_int8_t *addr; 220 { 221 register bus_io_handle_t tmpioh; 222 register u_int32_t *port, val; 223 register int offset; 224 225 wbflush(); 226 227 while (count--) { 228 tmpioh = ioh + off; 229 offset = tmpioh & 3; 230 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 231 val = *port; 232 *addr++ = ((val) >> (8 * offset)) & 0xff; 233 off++; 234 } 235 } 236 237 void 238 __C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count) 239 void *v; 240 bus_io_handle_t ioh; 241 bus_io_size_t off, count; 242 u_int16_t *addr; 243 { 244 register bus_io_handle_t tmpioh; 245 register u_int32_t *port, val; 246 register int offset; 247 248 wbflush(); 249 250 while (count--) { 251 tmpioh = ioh + off; 252 offset = tmpioh & 3; 253 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 254 val = *port; 255 *addr++ = ((val) >> (8 * offset)) & 0xffff; 256 off++; 257 } 258 } 259 260 void 261 __C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count) 262 void *v; 263 bus_io_handle_t ioh; 264 bus_io_size_t off, count; 265 u_int32_t *addr; 266 { 267 register bus_io_handle_t tmpioh; 268 register u_int32_t *port, val; 269 register int offset; 270 271 wbflush(); 272 273 while (count--) { 274 tmpioh = ioh + off; 275 offset = tmpioh & 3; 276 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 277 val = *port; 278 #if 0 279 *addr++ = ((val) >> (8 * offset)) & 0xffffffff; 280 #else 281 *addr++ = val; 282 #endif 283 off++; 284 } 285 } 286 287 void 288 __C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count) 289 void *v; 290 bus_io_handle_t ioh; 291 bus_io_size_t off, count; 292 u_int64_t *addr; 293 { 294 295 /* XXX XXX XXX */ 296 panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8))); 297 } 298 299 void 300 __C(CHIP,_io_write_1)(v, ioh, off, val) 301 void *v; 302 bus_io_handle_t ioh; 303 bus_io_size_t off; 304 u_int8_t val; 305 { 306 register bus_io_handle_t tmpioh; 307 register u_int32_t *port, nval; 308 register int offset; 309 310 tmpioh = ioh + off; 311 offset = tmpioh & 3; 312 nval = val << (8 * offset); 313 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 314 *port = nval; 315 wbflush(); 316 } 317 318 void 319 __C(CHIP,_io_write_2)(v, ioh, off, val) 320 void *v; 321 bus_io_handle_t ioh; 322 bus_io_size_t off; 323 u_int16_t val; 324 { 325 register bus_io_handle_t tmpioh; 326 register u_int32_t *port, nval; 327 register int offset; 328 329 tmpioh = ioh + off; 330 offset = tmpioh & 3; 331 nval = val << (8 * offset); 332 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 333 *port = nval; 334 wbflush(); 335 } 336 337 void 338 __C(CHIP,_io_write_4)(v, ioh, off, val) 339 void *v; 340 bus_io_handle_t ioh; 341 bus_io_size_t off; 342 u_int32_t val; 343 { 344 register bus_io_handle_t tmpioh; 345 register u_int32_t *port, nval; 346 register int offset; 347 348 tmpioh = ioh + off; 349 offset = tmpioh & 3; 350 nval = val /*<< (8 * offset)*/; 351 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 352 *port = nval; 353 wbflush(); 354 } 355 356 void 357 __C(CHIP,_io_write_8)(v, ioh, off, val) 358 void *v; 359 bus_io_handle_t ioh; 360 bus_io_size_t off; 361 u_int64_t val; 362 { 363 364 /* XXX XXX XXX */ 365 panic("%s not implemented\n", __S(__C(CHIP,_io_write_8))); 366 wbflush(); 367 } 368 369 void 370 __C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count) 371 void *v; 372 bus_io_handle_t ioh; 373 bus_io_size_t off, count; 374 const u_int8_t *addr; 375 { 376 register bus_io_handle_t tmpioh; 377 register u_int32_t *port, nval; 378 register int offset; 379 380 while (count--) { 381 tmpioh = ioh + off; 382 offset = tmpioh & 3; 383 nval = (*addr++) << (8 * offset); 384 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 385 *port = nval; 386 off++; 387 } 388 wbflush(); 389 } 390 391 void 392 __C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count) 393 void *v; 394 bus_io_handle_t ioh; 395 bus_io_size_t off, count; 396 const u_int16_t *addr; 397 { 398 register bus_io_handle_t tmpioh; 399 register u_int32_t *port, nval; 400 register int offset; 401 402 while (count--) { 403 tmpioh = ioh + off; 404 offset = tmpioh & 3; 405 nval = (*addr++) << (8 * offset); 406 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 407 *port = nval; 408 off++; 409 } 410 wbflush(); 411 } 412 413 void 414 __C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count) 415 void *v; 416 bus_io_handle_t ioh; 417 bus_io_size_t off, count; 418 const u_int32_t *addr; 419 { 420 register bus_io_handle_t tmpioh; 421 register u_int32_t *port, nval; 422 register int offset; 423 424 while (count--) { 425 tmpioh = ioh + off; 426 offset = tmpioh & 3; 427 nval = (*addr++) /*<< (8 * offset)*/; 428 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 429 *port = nval; 430 off++; 431 } 432 wbflush(); 433 } 434 435 void 436 __C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count) 437 void *v; 438 bus_io_handle_t ioh; 439 bus_io_size_t off, count; 440 const u_int64_t *addr; 441 { 442 443 /* XXX XXX XXX */ 444 panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8))); 445 } 446
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