pci_swiz_bus_io_chipdep.c revision 1.20
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.20 1997/09/02 19:39:15 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 * CHIP_IO_EX_STORE 38 * If defined, device-provided static storage area 39 * for the I/O space extent. If this is defined, 40 * CHIP_IO_EX_STORE_SIZE must also be defined. If 41 * this is not defined, a static area will be 42 * declared. 43 * CHIP_IO_EX_STORE_SIZE 44 * Size of the device-provided static storage area 45 * for the I/O memory space extent. 46 */ 47 48 #include <sys/extent.h> 49 50 #define __C(A,B) __CONCAT(A,B) 51 #define __S(S) __STRING(S) 52 53 /* mapping/unmapping */ 54 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 59 bus_size_t, bus_size_t, bus_space_handle_t *)); 60 61 /* allocation/deallocation */ 62 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 63 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 64 bus_space_handle_t *)); 65 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 66 bus_size_t)); 67 68 /* barrier */ 69 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 70 bus_size_t, bus_size_t, int)); 71 72 /* read (single) */ 73 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 74 bus_size_t)); 75 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 76 bus_size_t)); 77 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 78 bus_size_t)); 79 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 80 bus_size_t)); 81 82 /* read multiple */ 83 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 84 bus_size_t, u_int8_t *, bus_size_t)); 85 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 86 bus_size_t, u_int16_t *, bus_size_t)); 87 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 88 bus_size_t, u_int32_t *, bus_size_t)); 89 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 90 bus_size_t, u_int64_t *, bus_size_t)); 91 92 /* read region */ 93 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 94 bus_size_t, u_int8_t *, bus_size_t)); 95 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 96 bus_size_t, u_int16_t *, bus_size_t)); 97 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 98 bus_size_t, u_int32_t *, bus_size_t)); 99 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 100 bus_size_t, u_int64_t *, bus_size_t)); 101 102 /* write (single) */ 103 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 104 bus_size_t, u_int8_t)); 105 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 106 bus_size_t, u_int16_t)); 107 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 108 bus_size_t, u_int32_t)); 109 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 110 bus_size_t, u_int64_t)); 111 112 /* write multiple */ 113 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 114 bus_size_t, const u_int8_t *, bus_size_t)); 115 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 116 bus_size_t, const u_int16_t *, bus_size_t)); 117 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 118 bus_size_t, const u_int32_t *, bus_size_t)); 119 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 120 bus_size_t, const u_int64_t *, bus_size_t)); 121 122 /* write region */ 123 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 124 bus_size_t, const u_int8_t *, bus_size_t)); 125 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 126 bus_size_t, const u_int16_t *, bus_size_t)); 127 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 128 bus_size_t, const u_int32_t *, bus_size_t)); 129 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 130 bus_size_t, const u_int64_t *, bus_size_t)); 131 132 /* set multiple */ 133 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t, bus_size_t)); 135 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t, bus_size_t)); 137 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t, bus_size_t)); 139 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t, bus_size_t)); 141 142 /* set region */ 143 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t, bus_size_t)); 145 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t, bus_size_t)); 147 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t, bus_size_t)); 149 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t, bus_size_t)); 151 152 /* copy */ 153 void __C(CHIP,_io_copy_1) __P((void *, bus_space_handle_t, 154 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 155 void __C(CHIP,_io_copy_2) __P((void *, bus_space_handle_t, 156 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 157 void __C(CHIP,_io_copy_4) __P((void *, bus_space_handle_t, 158 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 159 void __C(CHIP,_io_copy_8) __P((void *, bus_space_handle_t, 160 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 161 162 #ifndef CHIP_IO_EX_STORE 163 static long 164 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 165 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 166 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 167 #endif 168 169 void 170 __C(CHIP,_bus_io_init)(t, v) 171 bus_space_tag_t t; 172 void *v; 173 { 174 struct extent *ex; 175 176 /* 177 * Initialize the bus space tag. 178 */ 179 180 /* cookie */ 181 t->abs_cookie = v; 182 183 /* mapping/unmapping */ 184 t->abs_map = __C(CHIP,_io_map); 185 t->abs_unmap = __C(CHIP,_io_unmap); 186 t->abs_subregion = __C(CHIP,_io_subregion); 187 188 /* allocation/deallocation */ 189 t->abs_alloc = __C(CHIP,_io_alloc); 190 t->abs_free = __C(CHIP,_io_free); 191 192 /* barrier */ 193 t->abs_barrier = __C(CHIP,_io_barrier); 194 195 /* read (single) */ 196 t->abs_r_1 = __C(CHIP,_io_read_1); 197 t->abs_r_2 = __C(CHIP,_io_read_2); 198 t->abs_r_4 = __C(CHIP,_io_read_4); 199 t->abs_r_8 = __C(CHIP,_io_read_8); 200 201 /* read multiple */ 202 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 203 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 204 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 205 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 206 207 /* read region */ 208 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 209 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 210 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 211 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 212 213 /* write (single) */ 214 t->abs_w_1 = __C(CHIP,_io_write_1); 215 t->abs_w_2 = __C(CHIP,_io_write_2); 216 t->abs_w_4 = __C(CHIP,_io_write_4); 217 t->abs_w_8 = __C(CHIP,_io_write_8); 218 219 /* write multiple */ 220 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 221 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 222 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 223 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 224 225 /* write region */ 226 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 227 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 228 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 229 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 230 231 /* set multiple */ 232 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 233 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 234 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 235 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 236 237 /* set region */ 238 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 239 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 240 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 241 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 242 243 /* copy */ 244 t->abs_c_1 = __C(CHIP,_io_copy_1); 245 t->abs_c_2 = __C(CHIP,_io_copy_2); 246 t->abs_c_4 = __C(CHIP,_io_copy_4); 247 t->abs_c_8 = __C(CHIP,_io_copy_8); 248 249 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 250 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 251 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 252 EX_NOWAIT); 253 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 254 255 #ifdef CHIP_IO_W1_BUS_START 256 #ifdef EXTENT_DEBUG 257 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 258 CHIP_IO_W1_BUS_END(v)); 259 #endif 260 extent_free(ex, CHIP_IO_W1_BUS_START(v), 261 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 262 #endif 263 #ifdef CHIP_IO_W2_BUS_START 264 #ifdef EXTENT_DEBUG 265 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 266 CHIP_IO_W2_BUS_END(v)); 267 #endif 268 extent_free(ex, CHIP_IO_W2_BUS_START(v), 269 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 270 #endif 271 272 #ifdef EXTENT_DEBUG 273 extent_print(ex); 274 #endif 275 CHIP_IO_EXTENT(v) = ex; 276 } 277 278 int 279 __C(CHIP,_io_map)(v, ioaddr, iosize, cacheable, iohp) 280 void *v; 281 bus_addr_t ioaddr; 282 bus_size_t iosize; 283 int cacheable; 284 bus_space_handle_t *iohp; 285 { 286 int error; 287 288 #ifdef EXTENT_DEBUG 289 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 290 #endif 291 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 292 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 293 if (error) { 294 #ifdef EXTENT_DEBUG 295 printf("io: allocation failed (%d)\n", error); 296 extent_print(CHIP_IO_EXTENT(v)); 297 #endif 298 return (error); 299 } 300 301 #ifdef CHIP_IO_W1_BUS_START 302 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 303 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 304 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 305 (ioaddr - CHIP_IO_W1_BUS_START(v)); 306 } else 307 #endif 308 #ifdef CHIP_IO_W2_BUS_START 309 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 310 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 311 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 312 (ioaddr - CHIP_IO_W2_BUS_START(v)); 313 } else 314 #endif 315 { 316 printf("\n"); 317 #ifdef CHIP_IO_W1_BUS_START 318 printf("%s: window[1]=0x%lx-0x%lx\n", 319 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 320 CHIP_IO_W1_BUS_END(v)); 321 #endif 322 #ifdef CHIP_IO_W2_BUS_START 323 printf("%s: window[2]=0x%lx-0x%lx\n", 324 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 325 CHIP_IO_W2_BUS_END(v)); 326 #endif 327 panic("%s: don't know how to map %lx", 328 __S(__C(CHIP,_io_map)), ioaddr); 329 } 330 331 return (0); 332 } 333 334 void 335 __C(CHIP,_io_unmap)(v, ioh, iosize) 336 void *v; 337 bus_space_handle_t ioh; 338 bus_size_t iosize; 339 { 340 bus_addr_t ioaddr; 341 int error; 342 343 #ifdef EXTENT_DEBUG 344 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 345 #endif 346 347 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 348 349 #ifdef CHIP_IO_W1_BUS_START 350 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 351 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 352 ioaddr = CHIP_IO_W1_BUS_START(v) + 353 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 354 } else 355 #endif 356 #ifdef CHIP_IO_W2_BUS_START 357 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 358 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 359 ioaddr = CHIP_IO_W2_BUS_START(v) + 360 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 361 } else 362 #endif 363 { 364 printf("\n"); 365 #ifdef CHIP_IO_W1_BUS_START 366 printf("%s: sys window[1]=0x%lx-0x%lx\n", 367 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 368 CHIP_IO_W1_SYS_END(v)); 369 #endif 370 #ifdef CHIP_IO_W2_BUS_START 371 printf("%s: sys window[2]=0x%lx-0x%lx\n", 372 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 373 CHIP_IO_W2_SYS_END(v)); 374 #endif 375 panic("%s: don't know how to unmap %lx", 376 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 377 } 378 379 #ifdef EXTENT_DEBUG 380 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 381 #endif 382 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 383 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 384 if (error) { 385 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 386 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 387 error); 388 #ifdef EXTENT_DEBUG 389 extent_print(CHIP_IO_EXTENT(v)); 390 #endif 391 } 392 } 393 394 int 395 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 396 void *v; 397 bus_space_handle_t ioh, *nioh; 398 bus_size_t offset, size; 399 { 400 401 *nioh = ioh + offset; 402 return (0); 403 } 404 405 int 406 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, cacheable, 407 addrp, bshp) 408 void *v; 409 bus_addr_t rstart, rend, *addrp; 410 bus_size_t size, align, boundary; 411 int cacheable; 412 bus_space_handle_t *bshp; 413 { 414 415 /* XXX XXX XXX XXX XXX XXX */ 416 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 417 } 418 419 void 420 __C(CHIP,_io_free)(v, bsh, size) 421 void *v; 422 bus_space_handle_t bsh; 423 bus_size_t size; 424 { 425 426 /* XXX XXX XXX XXX XXX XXX */ 427 panic("%s not implemented", __S(__C(CHIP,_io_free))); 428 } 429 430 inline void 431 __C(CHIP,_io_barrier)(v, h, o, l, f) 432 void *v; 433 bus_space_handle_t h; 434 bus_size_t o, l; 435 int f; 436 { 437 438 if ((f & BUS_BARRIER_READ) != 0) 439 alpha_mb(); 440 else if ((f & BUS_BARRIER_WRITE) != 0) 441 alpha_wmb(); 442 } 443 444 inline u_int8_t 445 __C(CHIP,_io_read_1)(v, ioh, off) 446 void *v; 447 bus_space_handle_t ioh; 448 bus_size_t off; 449 { 450 register bus_space_handle_t tmpioh; 451 register u_int32_t *port, val; 452 register u_int8_t rval; 453 register int offset; 454 455 alpha_mb(); 456 457 tmpioh = ioh + off; 458 offset = tmpioh & 3; 459 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 460 val = *port; 461 rval = ((val) >> (8 * offset)) & 0xff; 462 463 return rval; 464 } 465 466 inline u_int16_t 467 __C(CHIP,_io_read_2)(v, ioh, off) 468 void *v; 469 bus_space_handle_t ioh; 470 bus_size_t off; 471 { 472 register bus_space_handle_t tmpioh; 473 register u_int32_t *port, val; 474 register u_int16_t rval; 475 register int offset; 476 477 alpha_mb(); 478 479 tmpioh = ioh + off; 480 offset = tmpioh & 3; 481 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 482 val = *port; 483 rval = ((val) >> (8 * offset)) & 0xffff; 484 485 return rval; 486 } 487 488 inline u_int32_t 489 __C(CHIP,_io_read_4)(v, ioh, off) 490 void *v; 491 bus_space_handle_t ioh; 492 bus_size_t off; 493 { 494 register bus_space_handle_t tmpioh; 495 register u_int32_t *port, val; 496 register u_int32_t rval; 497 register int offset; 498 499 alpha_mb(); 500 501 tmpioh = ioh + off; 502 offset = tmpioh & 3; 503 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 504 val = *port; 505 #if 0 506 rval = ((val) >> (8 * offset)) & 0xffffffff; 507 #else 508 rval = val; 509 #endif 510 511 return rval; 512 } 513 514 inline u_int64_t 515 __C(CHIP,_io_read_8)(v, ioh, off) 516 void *v; 517 bus_space_handle_t ioh; 518 bus_size_t off; 519 { 520 521 /* XXX XXX XXX */ 522 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 523 } 524 525 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 526 void \ 527 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 528 void *v; \ 529 bus_space_handle_t h; \ 530 bus_size_t o, c; \ 531 TYPE *a; \ 532 { \ 533 \ 534 while (c-- > 0) { \ 535 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 536 BUS_BARRIER_READ); \ 537 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 538 } \ 539 } 540 CHIP_io_read_multi_N(1,u_int8_t) 541 CHIP_io_read_multi_N(2,u_int16_t) 542 CHIP_io_read_multi_N(4,u_int32_t) 543 CHIP_io_read_multi_N(8,u_int64_t) 544 545 #define CHIP_io_read_region_N(BYTES,TYPE) \ 546 void \ 547 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 548 void *v; \ 549 bus_space_handle_t h; \ 550 bus_size_t o, c; \ 551 TYPE *a; \ 552 { \ 553 \ 554 while (c-- > 0) { \ 555 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 556 o += sizeof *a; \ 557 } \ 558 } 559 CHIP_io_read_region_N(1,u_int8_t) 560 CHIP_io_read_region_N(2,u_int16_t) 561 CHIP_io_read_region_N(4,u_int32_t) 562 CHIP_io_read_region_N(8,u_int64_t) 563 564 inline void 565 __C(CHIP,_io_write_1)(v, ioh, off, val) 566 void *v; 567 bus_space_handle_t ioh; 568 bus_size_t off; 569 u_int8_t val; 570 { 571 register bus_space_handle_t tmpioh; 572 register u_int32_t *port, nval; 573 register int offset; 574 575 tmpioh = ioh + off; 576 offset = tmpioh & 3; 577 nval = val << (8 * offset); 578 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 579 *port = nval; 580 alpha_mb(); 581 } 582 583 inline void 584 __C(CHIP,_io_write_2)(v, ioh, off, val) 585 void *v; 586 bus_space_handle_t ioh; 587 bus_size_t off; 588 u_int16_t val; 589 { 590 register bus_space_handle_t tmpioh; 591 register u_int32_t *port, nval; 592 register int offset; 593 594 tmpioh = ioh + off; 595 offset = tmpioh & 3; 596 nval = val << (8 * offset); 597 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 598 *port = nval; 599 alpha_mb(); 600 } 601 602 inline void 603 __C(CHIP,_io_write_4)(v, ioh, off, val) 604 void *v; 605 bus_space_handle_t ioh; 606 bus_size_t off; 607 u_int32_t val; 608 { 609 register bus_space_handle_t tmpioh; 610 register u_int32_t *port, nval; 611 register int offset; 612 613 tmpioh = ioh + off; 614 offset = tmpioh & 3; 615 nval = val /*<< (8 * offset)*/; 616 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 617 *port = nval; 618 alpha_mb(); 619 } 620 621 inline void 622 __C(CHIP,_io_write_8)(v, ioh, off, val) 623 void *v; 624 bus_space_handle_t ioh; 625 bus_size_t off; 626 u_int64_t val; 627 { 628 629 /* XXX XXX XXX */ 630 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 631 alpha_mb(); 632 } 633 634 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 635 void \ 636 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 637 void *v; \ 638 bus_space_handle_t h; \ 639 bus_size_t o, c; \ 640 const TYPE *a; \ 641 { \ 642 \ 643 while (c-- > 0) { \ 644 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 645 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 646 BUS_BARRIER_WRITE); \ 647 } \ 648 } 649 CHIP_io_write_multi_N(1,u_int8_t) 650 CHIP_io_write_multi_N(2,u_int16_t) 651 CHIP_io_write_multi_N(4,u_int32_t) 652 CHIP_io_write_multi_N(8,u_int64_t) 653 654 #define CHIP_io_write_region_N(BYTES,TYPE) \ 655 void \ 656 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 657 void *v; \ 658 bus_space_handle_t h; \ 659 bus_size_t o, c; \ 660 const TYPE *a; \ 661 { \ 662 \ 663 while (c-- > 0) { \ 664 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 665 o += sizeof *a; \ 666 } \ 667 } 668 CHIP_io_write_region_N(1,u_int8_t) 669 CHIP_io_write_region_N(2,u_int16_t) 670 CHIP_io_write_region_N(4,u_int32_t) 671 CHIP_io_write_region_N(8,u_int64_t) 672 673 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 674 void \ 675 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 676 void *v; \ 677 bus_space_handle_t h; \ 678 bus_size_t o, c; \ 679 TYPE val; \ 680 { \ 681 \ 682 while (c-- > 0) { \ 683 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 684 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 685 BUS_BARRIER_WRITE); \ 686 } \ 687 } 688 CHIP_io_set_multi_N(1,u_int8_t) 689 CHIP_io_set_multi_N(2,u_int16_t) 690 CHIP_io_set_multi_N(4,u_int32_t) 691 CHIP_io_set_multi_N(8,u_int64_t) 692 693 #define CHIP_io_set_region_N(BYTES,TYPE) \ 694 void \ 695 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 696 void *v; \ 697 bus_space_handle_t h; \ 698 bus_size_t o, c; \ 699 TYPE val; \ 700 { \ 701 \ 702 while (c-- > 0) { \ 703 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 704 o += sizeof val; \ 705 } \ 706 } 707 CHIP_io_set_region_N(1,u_int8_t) 708 CHIP_io_set_region_N(2,u_int16_t) 709 CHIP_io_set_region_N(4,u_int32_t) 710 CHIP_io_set_region_N(8,u_int64_t) 711 712 #define CHIP_io_copy_N(BYTES) \ 713 void \ 714 __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \ 715 void *v; \ 716 bus_space_handle_t h1, h2; \ 717 bus_size_t o1, o2, c; \ 718 { \ 719 bus_size_t i, o; \ 720 \ 721 for (i = 0, o = 0; i < c; i++, o += BYTES) \ 722 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 723 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 724 } 725 CHIP_io_copy_N(1) 726 CHIP_io_copy_N(2) 727 CHIP_io_copy_N(4) 728 CHIP_io_copy_N(8) 729
Indexes created Tue Oct 14 15:09:51 GMT 2025