pci_swiz_bus_io_chipdep.c revision 1.22.4.1
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.22.4.1 1997/10/25 01:25:09 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 * CHIP_IO_EX_STORE 38 * If defined, device-provided static storage area 39 * for the I/O space extent. If this is defined, 40 * CHIP_IO_EX_STORE_SIZE must also be defined. If 41 * this is not defined, a static area will be 42 * declared. 43 * CHIP_IO_EX_STORE_SIZE 44 * Size of the device-provided static storage area 45 * for the I/O memory space extent. 46 */ 47 48 #include <sys/extent.h> 49 50 #define __C(A,B) __CONCAT(A,B) 51 #define __S(S) __STRING(S) 52 53 /* mapping/unmapping */ 54 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 55 bus_space_handle_t *)); 56 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 57 bus_size_t)); 58 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 59 bus_size_t, bus_size_t, bus_space_handle_t *)); 60 61 /* allocation/deallocation */ 62 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 63 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 64 bus_space_handle_t *)); 65 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 66 bus_size_t)); 67 68 /* barrier */ 69 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 70 bus_size_t, bus_size_t, int)); 71 72 /* read (single) */ 73 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 74 bus_size_t)); 75 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 76 bus_size_t)); 77 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 78 bus_size_t)); 79 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 80 bus_size_t)); 81 82 /* read multiple */ 83 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 84 bus_size_t, u_int8_t *, bus_size_t)); 85 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 86 bus_size_t, u_int16_t *, bus_size_t)); 87 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 88 bus_size_t, u_int32_t *, bus_size_t)); 89 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 90 bus_size_t, u_int64_t *, bus_size_t)); 91 92 /* read region */ 93 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 94 bus_size_t, u_int8_t *, bus_size_t)); 95 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 96 bus_size_t, u_int16_t *, bus_size_t)); 97 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 98 bus_size_t, u_int32_t *, bus_size_t)); 99 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 100 bus_size_t, u_int64_t *, bus_size_t)); 101 102 /* write (single) */ 103 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 104 bus_size_t, u_int8_t)); 105 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 106 bus_size_t, u_int16_t)); 107 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 108 bus_size_t, u_int32_t)); 109 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 110 bus_size_t, u_int64_t)); 111 112 /* write multiple */ 113 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 114 bus_size_t, const u_int8_t *, bus_size_t)); 115 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 116 bus_size_t, const u_int16_t *, bus_size_t)); 117 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 118 bus_size_t, const u_int32_t *, bus_size_t)); 119 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 120 bus_size_t, const u_int64_t *, bus_size_t)); 121 122 /* write region */ 123 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 124 bus_size_t, const u_int8_t *, bus_size_t)); 125 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 126 bus_size_t, const u_int16_t *, bus_size_t)); 127 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 128 bus_size_t, const u_int32_t *, bus_size_t)); 129 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 130 bus_size_t, const u_int64_t *, bus_size_t)); 131 132 /* set multiple */ 133 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t, bus_size_t)); 135 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t, bus_size_t)); 137 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t, bus_size_t)); 139 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t, bus_size_t)); 141 142 /* set region */ 143 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t, bus_size_t)); 145 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t, bus_size_t)); 147 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t, bus_size_t)); 149 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t, bus_size_t)); 151 152 /* copy */ 153 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 154 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 155 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 156 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 157 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 158 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 159 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 160 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 161 162 #ifndef CHIP_IO_EX_STORE 163 static long 164 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 165 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 166 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 167 #endif 168 169 void 170 __C(CHIP,_bus_io_init)(t, v) 171 bus_space_tag_t t; 172 void *v; 173 { 174 struct extent *ex; 175 176 /* 177 * Initialize the bus space tag. 178 */ 179 180 /* cookie */ 181 t->abs_cookie = v; 182 183 /* mapping/unmapping */ 184 t->abs_map = __C(CHIP,_io_map); 185 t->abs_unmap = __C(CHIP,_io_unmap); 186 t->abs_subregion = __C(CHIP,_io_subregion); 187 188 /* allocation/deallocation */ 189 t->abs_alloc = __C(CHIP,_io_alloc); 190 t->abs_free = __C(CHIP,_io_free); 191 192 /* barrier */ 193 t->abs_barrier = __C(CHIP,_io_barrier); 194 195 /* read (single) */ 196 t->abs_r_1 = __C(CHIP,_io_read_1); 197 t->abs_r_2 = __C(CHIP,_io_read_2); 198 t->abs_r_4 = __C(CHIP,_io_read_4); 199 t->abs_r_8 = __C(CHIP,_io_read_8); 200 201 /* read multiple */ 202 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 203 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 204 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 205 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 206 207 /* read region */ 208 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 209 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 210 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 211 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 212 213 /* write (single) */ 214 t->abs_w_1 = __C(CHIP,_io_write_1); 215 t->abs_w_2 = __C(CHIP,_io_write_2); 216 t->abs_w_4 = __C(CHIP,_io_write_4); 217 t->abs_w_8 = __C(CHIP,_io_write_8); 218 219 /* write multiple */ 220 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 221 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 222 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 223 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 224 225 /* write region */ 226 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 227 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 228 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 229 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 230 231 /* set multiple */ 232 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 233 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 234 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 235 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 236 237 /* set region */ 238 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 239 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 240 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 241 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 242 243 /* copy */ 244 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 245 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 246 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 247 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 248 249 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 250 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 251 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 252 EX_NOWAIT); 253 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 254 255 #ifdef CHIP_IO_W1_BUS_START 256 #ifdef EXTENT_DEBUG 257 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 258 CHIP_IO_W1_BUS_END(v)); 259 #endif 260 extent_free(ex, CHIP_IO_W1_BUS_START(v), 261 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 262 #endif 263 #ifdef CHIP_IO_W2_BUS_START 264 #ifdef EXTENT_DEBUG 265 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 266 CHIP_IO_W2_BUS_END(v)); 267 #endif 268 extent_free(ex, CHIP_IO_W2_BUS_START(v), 269 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 270 #endif 271 272 #ifdef EXTENT_DEBUG 273 extent_print(ex); 274 #endif 275 CHIP_IO_EXTENT(v) = ex; 276 } 277 278 int 279 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp) 280 void *v; 281 bus_addr_t ioaddr; 282 bus_size_t iosize; 283 int flags; 284 bus_space_handle_t *iohp; 285 { 286 int linear = flags & BUS_SPACE_MAP_LINEAR; 287 int error; 288 289 /* 290 * Can't map i/o space linearly. 291 */ 292 if (linear) 293 return (EOPNOTSUPP); 294 295 #ifdef EXTENT_DEBUG 296 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 297 #endif 298 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 299 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 300 if (error) { 301 #ifdef EXTENT_DEBUG 302 printf("io: allocation failed (%d)\n", error); 303 extent_print(CHIP_IO_EXTENT(v)); 304 #endif 305 return (error); 306 } 307 308 #ifdef CHIP_IO_W1_BUS_START 309 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 310 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 311 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 312 (ioaddr - CHIP_IO_W1_BUS_START(v)); 313 } else 314 #endif 315 #ifdef CHIP_IO_W2_BUS_START 316 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 317 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 318 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 319 (ioaddr - CHIP_IO_W2_BUS_START(v)); 320 } else 321 #endif 322 { 323 printf("\n"); 324 #ifdef CHIP_IO_W1_BUS_START 325 printf("%s: window[1]=0x%lx-0x%lx\n", 326 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 327 CHIP_IO_W1_BUS_END(v)); 328 #endif 329 #ifdef CHIP_IO_W2_BUS_START 330 printf("%s: window[2]=0x%lx-0x%lx\n", 331 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 332 CHIP_IO_W2_BUS_END(v)); 333 #endif 334 panic("%s: don't know how to map %lx", 335 __S(__C(CHIP,_io_map)), ioaddr); 336 } 337 338 return (0); 339 } 340 341 void 342 __C(CHIP,_io_unmap)(v, ioh, iosize) 343 void *v; 344 bus_space_handle_t ioh; 345 bus_size_t iosize; 346 { 347 bus_addr_t ioaddr; 348 int error; 349 350 #ifdef EXTENT_DEBUG 351 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 352 #endif 353 354 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 355 356 #ifdef CHIP_IO_W1_BUS_START 357 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 358 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 359 ioaddr = CHIP_IO_W1_BUS_START(v) + 360 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 361 } else 362 #endif 363 #ifdef CHIP_IO_W2_BUS_START 364 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 365 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 366 ioaddr = CHIP_IO_W2_BUS_START(v) + 367 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 368 } else 369 #endif 370 { 371 printf("\n"); 372 #ifdef CHIP_IO_W1_BUS_START 373 printf("%s: sys window[1]=0x%lx-0x%lx\n", 374 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 375 CHIP_IO_W1_SYS_END(v)); 376 #endif 377 #ifdef CHIP_IO_W2_BUS_START 378 printf("%s: sys window[2]=0x%lx-0x%lx\n", 379 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 380 CHIP_IO_W2_SYS_END(v)); 381 #endif 382 panic("%s: don't know how to unmap %lx", 383 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 384 } 385 386 #ifdef EXTENT_DEBUG 387 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 388 #endif 389 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 390 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 391 if (error) { 392 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 393 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 394 error); 395 #ifdef EXTENT_DEBUG 396 extent_print(CHIP_IO_EXTENT(v)); 397 #endif 398 } 399 } 400 401 int 402 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 403 void *v; 404 bus_space_handle_t ioh, *nioh; 405 bus_size_t offset, size; 406 { 407 408 *nioh = ioh + offset; 409 return (0); 410 } 411 412 int 413 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 414 addrp, bshp) 415 void *v; 416 bus_addr_t rstart, rend, *addrp; 417 bus_size_t size, align, boundary; 418 int flags; 419 bus_space_handle_t *bshp; 420 { 421 422 /* XXX XXX XXX XXX XXX XXX */ 423 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 424 } 425 426 void 427 __C(CHIP,_io_free)(v, bsh, size) 428 void *v; 429 bus_space_handle_t bsh; 430 bus_size_t size; 431 { 432 433 /* XXX XXX XXX XXX XXX XXX */ 434 panic("%s not implemented", __S(__C(CHIP,_io_free))); 435 } 436 437 inline void 438 __C(CHIP,_io_barrier)(v, h, o, l, f) 439 void *v; 440 bus_space_handle_t h; 441 bus_size_t o, l; 442 int f; 443 { 444 445 if ((f & BUS_SPACE_BARRIER_READ) != 0) 446 alpha_mb(); 447 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 448 alpha_wmb(); 449 } 450 451 inline u_int8_t 452 __C(CHIP,_io_read_1)(v, ioh, off) 453 void *v; 454 bus_space_handle_t ioh; 455 bus_size_t off; 456 { 457 register bus_space_handle_t tmpioh; 458 register u_int32_t *port, val; 459 register u_int8_t rval; 460 register int offset; 461 462 alpha_mb(); 463 464 tmpioh = ioh + off; 465 offset = tmpioh & 3; 466 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 467 val = *port; 468 rval = ((val) >> (8 * offset)) & 0xff; 469 470 return rval; 471 } 472 473 inline u_int16_t 474 __C(CHIP,_io_read_2)(v, ioh, off) 475 void *v; 476 bus_space_handle_t ioh; 477 bus_size_t off; 478 { 479 register bus_space_handle_t tmpioh; 480 register u_int32_t *port, val; 481 register u_int16_t rval; 482 register int offset; 483 484 alpha_mb(); 485 486 tmpioh = ioh + off; 487 offset = tmpioh & 3; 488 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 489 val = *port; 490 rval = ((val) >> (8 * offset)) & 0xffff; 491 492 return rval; 493 } 494 495 inline u_int32_t 496 __C(CHIP,_io_read_4)(v, ioh, off) 497 void *v; 498 bus_space_handle_t ioh; 499 bus_size_t off; 500 { 501 register bus_space_handle_t tmpioh; 502 register u_int32_t *port, val; 503 register u_int32_t rval; 504 register int offset; 505 506 alpha_mb(); 507 508 tmpioh = ioh + off; 509 offset = tmpioh & 3; 510 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 511 val = *port; 512 #if 0 513 rval = ((val) >> (8 * offset)) & 0xffffffff; 514 #else 515 rval = val; 516 #endif 517 518 return rval; 519 } 520 521 inline u_int64_t 522 __C(CHIP,_io_read_8)(v, ioh, off) 523 void *v; 524 bus_space_handle_t ioh; 525 bus_size_t off; 526 { 527 528 /* XXX XXX XXX */ 529 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 530 } 531 532 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 533 void \ 534 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 535 void *v; \ 536 bus_space_handle_t h; \ 537 bus_size_t o, c; \ 538 TYPE *a; \ 539 { \ 540 \ 541 while (c-- > 0) { \ 542 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 543 BUS_BARRIER_READ); \ 544 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 545 } \ 546 } 547 CHIP_io_read_multi_N(1,u_int8_t) 548 CHIP_io_read_multi_N(2,u_int16_t) 549 CHIP_io_read_multi_N(4,u_int32_t) 550 CHIP_io_read_multi_N(8,u_int64_t) 551 552 #define CHIP_io_read_region_N(BYTES,TYPE) \ 553 void \ 554 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 555 void *v; \ 556 bus_space_handle_t h; \ 557 bus_size_t o, c; \ 558 TYPE *a; \ 559 { \ 560 \ 561 while (c-- > 0) { \ 562 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 563 o += sizeof *a; \ 564 } \ 565 } 566 CHIP_io_read_region_N(1,u_int8_t) 567 CHIP_io_read_region_N(2,u_int16_t) 568 CHIP_io_read_region_N(4,u_int32_t) 569 CHIP_io_read_region_N(8,u_int64_t) 570 571 inline void 572 __C(CHIP,_io_write_1)(v, ioh, off, val) 573 void *v; 574 bus_space_handle_t ioh; 575 bus_size_t off; 576 u_int8_t val; 577 { 578 register bus_space_handle_t tmpioh; 579 register u_int32_t *port, nval; 580 register int offset; 581 582 tmpioh = ioh + off; 583 offset = tmpioh & 3; 584 nval = val << (8 * offset); 585 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 586 *port = nval; 587 alpha_mb(); 588 } 589 590 inline void 591 __C(CHIP,_io_write_2)(v, ioh, off, val) 592 void *v; 593 bus_space_handle_t ioh; 594 bus_size_t off; 595 u_int16_t val; 596 { 597 register bus_space_handle_t tmpioh; 598 register u_int32_t *port, nval; 599 register int offset; 600 601 tmpioh = ioh + off; 602 offset = tmpioh & 3; 603 nval = val << (8 * offset); 604 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 605 *port = nval; 606 alpha_mb(); 607 } 608 609 inline void 610 __C(CHIP,_io_write_4)(v, ioh, off, val) 611 void *v; 612 bus_space_handle_t ioh; 613 bus_size_t off; 614 u_int32_t val; 615 { 616 register bus_space_handle_t tmpioh; 617 register u_int32_t *port, nval; 618 register int offset; 619 620 tmpioh = ioh + off; 621 offset = tmpioh & 3; 622 nval = val /*<< (8 * offset)*/; 623 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 624 *port = nval; 625 alpha_mb(); 626 } 627 628 inline void 629 __C(CHIP,_io_write_8)(v, ioh, off, val) 630 void *v; 631 bus_space_handle_t ioh; 632 bus_size_t off; 633 u_int64_t val; 634 { 635 636 /* XXX XXX XXX */ 637 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 638 alpha_mb(); 639 } 640 641 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 642 void \ 643 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 644 void *v; \ 645 bus_space_handle_t h; \ 646 bus_size_t o, c; \ 647 const TYPE *a; \ 648 { \ 649 \ 650 while (c-- > 0) { \ 651 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 652 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 653 BUS_BARRIER_WRITE); \ 654 } \ 655 } 656 CHIP_io_write_multi_N(1,u_int8_t) 657 CHIP_io_write_multi_N(2,u_int16_t) 658 CHIP_io_write_multi_N(4,u_int32_t) 659 CHIP_io_write_multi_N(8,u_int64_t) 660 661 #define CHIP_io_write_region_N(BYTES,TYPE) \ 662 void \ 663 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 664 void *v; \ 665 bus_space_handle_t h; \ 666 bus_size_t o, c; \ 667 const TYPE *a; \ 668 { \ 669 \ 670 while (c-- > 0) { \ 671 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 672 o += sizeof *a; \ 673 } \ 674 } 675 CHIP_io_write_region_N(1,u_int8_t) 676 CHIP_io_write_region_N(2,u_int16_t) 677 CHIP_io_write_region_N(4,u_int32_t) 678 CHIP_io_write_region_N(8,u_int64_t) 679 680 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 681 void \ 682 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 683 void *v; \ 684 bus_space_handle_t h; \ 685 bus_size_t o, c; \ 686 TYPE val; \ 687 { \ 688 \ 689 while (c-- > 0) { \ 690 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 691 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 692 BUS_BARRIER_WRITE); \ 693 } \ 694 } 695 CHIP_io_set_multi_N(1,u_int8_t) 696 CHIP_io_set_multi_N(2,u_int16_t) 697 CHIP_io_set_multi_N(4,u_int32_t) 698 CHIP_io_set_multi_N(8,u_int64_t) 699 700 #define CHIP_io_set_region_N(BYTES,TYPE) \ 701 void \ 702 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 703 void *v; \ 704 bus_space_handle_t h; \ 705 bus_size_t o, c; \ 706 TYPE val; \ 707 { \ 708 \ 709 while (c-- > 0) { \ 710 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 711 o += sizeof val; \ 712 } \ 713 } 714 CHIP_io_set_region_N(1,u_int8_t) 715 CHIP_io_set_region_N(2,u_int16_t) 716 CHIP_io_set_region_N(4,u_int32_t) 717 CHIP_io_set_region_N(8,u_int64_t) 718 719 #define CHIP_io_copy_region_N(BYTES) \ 720 void \ 721 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 722 void *v; \ 723 bus_space_handle_t h1, h2; \ 724 bus_size_t o1, o2, c; \ 725 { \ 726 bus_size_t o; \ 727 \ 728 if ((h1 + o1) >= (h2 + o2)) { \ 729 /* src after dest: copy forward */ \ 730 for (o = 0; c != 0; c--, o += BYTES) \ 731 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 732 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 733 } else { \ 734 /* dest after src: copy backwards */ \ 735 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 736 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 737 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 738 } \ 739 } 740 CHIP_io_copy_region_N(1) 741 CHIP_io_copy_region_N(2) 742 CHIP_io_copy_region_N(4) 743 CHIP_io_copy_region_N(8) 744
Indexes created Tue Oct 14 11:09:46 GMT 2025