pci_swiz_bus_io_chipdep.c revision 1.24
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.24 1998/06/06 22:44:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE Sparse I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *)); 93 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t)); 95 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 /* allocation/deallocation */ 99 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 100 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 101 bus_space_handle_t *)); 102 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 103 bus_size_t)); 104 105 /* barrier */ 106 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 107 bus_size_t, bus_size_t, int)); 108 109 /* read (single) */ 110 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* read multiple */ 120 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t *, bus_size_t)); 122 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t *, bus_size_t)); 124 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t *, bus_size_t)); 126 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t *, bus_size_t)); 128 129 /* read region */ 130 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* write (single) */ 140 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t)); 142 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t)); 144 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t)); 146 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t)); 148 149 /* write multiple */ 150 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 151 bus_size_t, const u_int8_t *, bus_size_t)); 152 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int16_t *, bus_size_t)); 154 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int32_t *, bus_size_t)); 156 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int64_t *, bus_size_t)); 158 159 /* write region */ 160 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* set multiple */ 170 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, u_int8_t, bus_size_t)); 172 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int16_t, bus_size_t)); 174 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int32_t, bus_size_t)); 176 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int64_t, bus_size_t)); 178 179 /* set region */ 180 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* copy */ 190 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 192 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 199 /* Internal */ 200 void __C(CHIP,_io_mapit) __P((void *, bus_addr_t, 201 bus_space_handle_t *)); 202 203 #ifndef CHIP_IO_EX_STORE 204 static long 205 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 206 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 207 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 208 #endif 209 210 void 211 __C(CHIP,_bus_io_init)(t, v) 212 bus_space_tag_t t; 213 void *v; 214 { 215 struct extent *ex; 216 217 /* 218 * Initialize the bus space tag. 219 */ 220 221 /* cookie */ 222 t->abs_cookie = v; 223 224 /* mapping/unmapping */ 225 t->abs_map = __C(CHIP,_io_map); 226 t->abs_unmap = __C(CHIP,_io_unmap); 227 t->abs_subregion = __C(CHIP,_io_subregion); 228 229 /* allocation/deallocation */ 230 t->abs_alloc = __C(CHIP,_io_alloc); 231 t->abs_free = __C(CHIP,_io_free); 232 233 /* barrier */ 234 t->abs_barrier = __C(CHIP,_io_barrier); 235 236 /* read (single) */ 237 t->abs_r_1 = __C(CHIP,_io_read_1); 238 t->abs_r_2 = __C(CHIP,_io_read_2); 239 t->abs_r_4 = __C(CHIP,_io_read_4); 240 t->abs_r_8 = __C(CHIP,_io_read_8); 241 242 /* read multiple */ 243 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 244 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 245 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 246 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 247 248 /* read region */ 249 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 250 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 251 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 252 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 253 254 /* write (single) */ 255 t->abs_w_1 = __C(CHIP,_io_write_1); 256 t->abs_w_2 = __C(CHIP,_io_write_2); 257 t->abs_w_4 = __C(CHIP,_io_write_4); 258 t->abs_w_8 = __C(CHIP,_io_write_8); 259 260 /* write multiple */ 261 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 262 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 263 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 264 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 265 266 /* write region */ 267 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 268 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 269 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 270 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 271 272 /* set multiple */ 273 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 274 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 275 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 276 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 277 278 /* set region */ 279 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 280 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 281 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 282 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 283 284 /* copy */ 285 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 286 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 287 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 288 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 289 290 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 291 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 292 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 293 EX_NOWAIT); 294 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 295 296 #ifdef CHIP_IO_W1_BUS_START 297 #ifdef EXTENT_DEBUG 298 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 299 CHIP_IO_W1_BUS_END(v)); 300 #endif 301 extent_free(ex, CHIP_IO_W1_BUS_START(v), 302 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 303 #endif 304 #ifdef CHIP_IO_W2_BUS_START 305 #ifdef EXTENT_DEBUG 306 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 307 CHIP_IO_W2_BUS_END(v)); 308 #endif 309 extent_free(ex, CHIP_IO_W2_BUS_START(v), 310 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 311 #endif 312 313 #ifdef EXTENT_DEBUG 314 extent_print(ex); 315 #endif 316 CHIP_IO_EXTENT(v) = ex; 317 } 318 319 void 320 __C(CHIP,_io_mapit)(v, ioaddr, iohp) 321 void *v; 322 bus_addr_t ioaddr; 323 bus_space_handle_t *iohp; 324 { 325 326 #ifdef CHIP_IO_W1_BUS_START 327 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 328 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 329 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 330 (ioaddr - CHIP_IO_W1_BUS_START(v)); 331 } else 332 #endif 333 #ifdef CHIP_IO_W2_BUS_START 334 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 335 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 336 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 337 (ioaddr - CHIP_IO_W2_BUS_START(v)); 338 } else 339 #endif 340 { 341 printf("\n"); 342 #ifdef CHIP_IO_W1_BUS_START 343 printf("%s: window[1]=0x%lx-0x%lx\n", 344 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 345 CHIP_IO_W1_BUS_END(v)); 346 #endif 347 #ifdef CHIP_IO_W2_BUS_START 348 printf("%s: window[2]=0x%lx-0x%lx\n", 349 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 350 CHIP_IO_W2_BUS_END(v)); 351 #endif 352 panic("%s: don't know how to map %lx", 353 __S(__C(CHIP,_io_mapit)), ioaddr); 354 } 355 } 356 357 int 358 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp) 359 void *v; 360 bus_addr_t ioaddr; 361 bus_size_t iosize; 362 int flags; 363 bus_space_handle_t *iohp; 364 { 365 int linear = flags & BUS_SPACE_MAP_LINEAR; 366 int error; 367 368 /* 369 * Can't map i/o space linearly. 370 */ 371 if (linear) 372 return (EOPNOTSUPP); 373 374 #ifdef EXTENT_DEBUG 375 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 376 #endif 377 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 378 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 379 if (error) { 380 #ifdef EXTENT_DEBUG 381 printf("io: allocation failed (%d)\n", error); 382 extent_print(CHIP_IO_EXTENT(v)); 383 #endif 384 return (error); 385 } 386 387 __C(CHIP,_io_mapit)(v, ioaddr, iohp); 388 389 return (0); 390 } 391 392 void 393 __C(CHIP,_io_unmap)(v, ioh, iosize) 394 void *v; 395 bus_space_handle_t ioh; 396 bus_size_t iosize; 397 { 398 bus_addr_t ioaddr; 399 int error; 400 401 #ifdef EXTENT_DEBUG 402 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 403 #endif 404 405 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 406 407 #ifdef CHIP_IO_W1_BUS_START 408 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 409 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 410 ioaddr = CHIP_IO_W1_BUS_START(v) + 411 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 412 } else 413 #endif 414 #ifdef CHIP_IO_W2_BUS_START 415 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 416 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 417 ioaddr = CHIP_IO_W2_BUS_START(v) + 418 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 419 } else 420 #endif 421 { 422 printf("\n"); 423 #ifdef CHIP_IO_W1_BUS_START 424 printf("%s: sys window[1]=0x%lx-0x%lx\n", 425 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 426 CHIP_IO_W1_SYS_END(v)); 427 #endif 428 #ifdef CHIP_IO_W2_BUS_START 429 printf("%s: sys window[2]=0x%lx-0x%lx\n", 430 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 431 CHIP_IO_W2_SYS_END(v)); 432 #endif 433 panic("%s: don't know how to unmap %lx", 434 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 435 } 436 437 #ifdef EXTENT_DEBUG 438 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 439 #endif 440 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 441 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 442 if (error) { 443 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 444 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 445 error); 446 #ifdef EXTENT_DEBUG 447 extent_print(CHIP_IO_EXTENT(v)); 448 #endif 449 } 450 } 451 452 int 453 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 454 void *v; 455 bus_space_handle_t ioh, *nioh; 456 bus_size_t offset, size; 457 { 458 459 *nioh = ioh + offset; 460 return (0); 461 } 462 463 int 464 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 465 addrp, bshp) 466 void *v; 467 bus_addr_t rstart, rend, *addrp; 468 bus_size_t size, align, boundary; 469 int flags; 470 bus_space_handle_t *bshp; 471 { 472 int linear = flags & BUS_SPACE_MAP_LINEAR; 473 bus_addr_t ioaddr; 474 int error; 475 476 /* 477 * Can't map i/o space linearly. 478 */ 479 if (linear) 480 return (EOPNOTSUPP); 481 482 /* 483 * Do the requested allocation. 484 */ 485 #ifdef EXTENT_DEBUG 486 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 487 #endif 488 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 489 size, align, boundary, 490 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 491 &ioaddr); 492 if (error) { 493 #ifdef EXTENT_DEBUG 494 printf("io: allocation failed (%d)\n", error); 495 extent_print(CHIP_IO_EXTENT(v)); 496 #endif 497 return (error); 498 } 499 500 #ifdef EXTENT_DEBUG 501 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 502 #endif 503 504 __C(CHIP,_io_mapit)(v, ioaddr, bshp); 505 506 return (0); 507 } 508 509 void 510 __C(CHIP,_io_free)(v, bsh, size) 511 void *v; 512 bus_space_handle_t bsh; 513 bus_size_t size; 514 { 515 516 /* Unmap does all we need to do. */ 517 __C(CHIP,_io_unmap)(v, bsh, size); 518 } 519 520 inline void 521 __C(CHIP,_io_barrier)(v, h, o, l, f) 522 void *v; 523 bus_space_handle_t h; 524 bus_size_t o, l; 525 int f; 526 { 527 528 if ((f & BUS_SPACE_BARRIER_READ) != 0) 529 alpha_mb(); 530 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 531 alpha_wmb(); 532 } 533 534 inline u_int8_t 535 __C(CHIP,_io_read_1)(v, ioh, off) 536 void *v; 537 bus_space_handle_t ioh; 538 bus_size_t off; 539 { 540 register bus_space_handle_t tmpioh; 541 register u_int32_t *port, val; 542 register u_int8_t rval; 543 register int offset; 544 545 alpha_mb(); 546 547 tmpioh = ioh + off; 548 offset = tmpioh & 3; 549 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 550 val = *port; 551 rval = ((val) >> (8 * offset)) & 0xff; 552 553 return rval; 554 } 555 556 inline u_int16_t 557 __C(CHIP,_io_read_2)(v, ioh, off) 558 void *v; 559 bus_space_handle_t ioh; 560 bus_size_t off; 561 { 562 register bus_space_handle_t tmpioh; 563 register u_int32_t *port, val; 564 register u_int16_t rval; 565 register int offset; 566 567 alpha_mb(); 568 569 tmpioh = ioh + off; 570 offset = tmpioh & 3; 571 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 572 val = *port; 573 rval = ((val) >> (8 * offset)) & 0xffff; 574 575 return rval; 576 } 577 578 inline u_int32_t 579 __C(CHIP,_io_read_4)(v, ioh, off) 580 void *v; 581 bus_space_handle_t ioh; 582 bus_size_t off; 583 { 584 register bus_space_handle_t tmpioh; 585 register u_int32_t *port, val; 586 register u_int32_t rval; 587 register int offset; 588 589 alpha_mb(); 590 591 tmpioh = ioh + off; 592 offset = tmpioh & 3; 593 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 594 val = *port; 595 #if 0 596 rval = ((val) >> (8 * offset)) & 0xffffffff; 597 #else 598 rval = val; 599 #endif 600 601 return rval; 602 } 603 604 inline u_int64_t 605 __C(CHIP,_io_read_8)(v, ioh, off) 606 void *v; 607 bus_space_handle_t ioh; 608 bus_size_t off; 609 { 610 611 /* XXX XXX XXX */ 612 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 613 } 614 615 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 616 void \ 617 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 618 void *v; \ 619 bus_space_handle_t h; \ 620 bus_size_t o, c; \ 621 TYPE *a; \ 622 { \ 623 \ 624 while (c-- > 0) { \ 625 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 626 BUS_BARRIER_READ); \ 627 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 628 } \ 629 } 630 CHIP_io_read_multi_N(1,u_int8_t) 631 CHIP_io_read_multi_N(2,u_int16_t) 632 CHIP_io_read_multi_N(4,u_int32_t) 633 CHIP_io_read_multi_N(8,u_int64_t) 634 635 #define CHIP_io_read_region_N(BYTES,TYPE) \ 636 void \ 637 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 638 void *v; \ 639 bus_space_handle_t h; \ 640 bus_size_t o, c; \ 641 TYPE *a; \ 642 { \ 643 \ 644 while (c-- > 0) { \ 645 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 646 o += sizeof *a; \ 647 } \ 648 } 649 CHIP_io_read_region_N(1,u_int8_t) 650 CHIP_io_read_region_N(2,u_int16_t) 651 CHIP_io_read_region_N(4,u_int32_t) 652 CHIP_io_read_region_N(8,u_int64_t) 653 654 inline void 655 __C(CHIP,_io_write_1)(v, ioh, off, val) 656 void *v; 657 bus_space_handle_t ioh; 658 bus_size_t off; 659 u_int8_t val; 660 { 661 register bus_space_handle_t tmpioh; 662 register u_int32_t *port, nval; 663 register int offset; 664 665 tmpioh = ioh + off; 666 offset = tmpioh & 3; 667 nval = val << (8 * offset); 668 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 669 *port = nval; 670 alpha_mb(); 671 } 672 673 inline void 674 __C(CHIP,_io_write_2)(v, ioh, off, val) 675 void *v; 676 bus_space_handle_t ioh; 677 bus_size_t off; 678 u_int16_t val; 679 { 680 register bus_space_handle_t tmpioh; 681 register u_int32_t *port, nval; 682 register int offset; 683 684 tmpioh = ioh + off; 685 offset = tmpioh & 3; 686 nval = val << (8 * offset); 687 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 688 *port = nval; 689 alpha_mb(); 690 } 691 692 inline void 693 __C(CHIP,_io_write_4)(v, ioh, off, val) 694 void *v; 695 bus_space_handle_t ioh; 696 bus_size_t off; 697 u_int32_t val; 698 { 699 register bus_space_handle_t tmpioh; 700 register u_int32_t *port, nval; 701 register int offset; 702 703 tmpioh = ioh + off; 704 offset = tmpioh & 3; 705 nval = val /*<< (8 * offset)*/; 706 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 707 *port = nval; 708 alpha_mb(); 709 } 710 711 inline void 712 __C(CHIP,_io_write_8)(v, ioh, off, val) 713 void *v; 714 bus_space_handle_t ioh; 715 bus_size_t off; 716 u_int64_t val; 717 { 718 719 /* XXX XXX XXX */ 720 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 721 alpha_mb(); 722 } 723 724 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 725 void \ 726 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 727 void *v; \ 728 bus_space_handle_t h; \ 729 bus_size_t o, c; \ 730 const TYPE *a; \ 731 { \ 732 \ 733 while (c-- > 0) { \ 734 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 735 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 736 BUS_BARRIER_WRITE); \ 737 } \ 738 } 739 CHIP_io_write_multi_N(1,u_int8_t) 740 CHIP_io_write_multi_N(2,u_int16_t) 741 CHIP_io_write_multi_N(4,u_int32_t) 742 CHIP_io_write_multi_N(8,u_int64_t) 743 744 #define CHIP_io_write_region_N(BYTES,TYPE) \ 745 void \ 746 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 747 void *v; \ 748 bus_space_handle_t h; \ 749 bus_size_t o, c; \ 750 const TYPE *a; \ 751 { \ 752 \ 753 while (c-- > 0) { \ 754 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 755 o += sizeof *a; \ 756 } \ 757 } 758 CHIP_io_write_region_N(1,u_int8_t) 759 CHIP_io_write_region_N(2,u_int16_t) 760 CHIP_io_write_region_N(4,u_int32_t) 761 CHIP_io_write_region_N(8,u_int64_t) 762 763 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 764 void \ 765 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 766 void *v; \ 767 bus_space_handle_t h; \ 768 bus_size_t o, c; \ 769 TYPE val; \ 770 { \ 771 \ 772 while (c-- > 0) { \ 773 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 774 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 775 BUS_BARRIER_WRITE); \ 776 } \ 777 } 778 CHIP_io_set_multi_N(1,u_int8_t) 779 CHIP_io_set_multi_N(2,u_int16_t) 780 CHIP_io_set_multi_N(4,u_int32_t) 781 CHIP_io_set_multi_N(8,u_int64_t) 782 783 #define CHIP_io_set_region_N(BYTES,TYPE) \ 784 void \ 785 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 786 void *v; \ 787 bus_space_handle_t h; \ 788 bus_size_t o, c; \ 789 TYPE val; \ 790 { \ 791 \ 792 while (c-- > 0) { \ 793 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 794 o += sizeof val; \ 795 } \ 796 } 797 CHIP_io_set_region_N(1,u_int8_t) 798 CHIP_io_set_region_N(2,u_int16_t) 799 CHIP_io_set_region_N(4,u_int32_t) 800 CHIP_io_set_region_N(8,u_int64_t) 801 802 #define CHIP_io_copy_region_N(BYTES) \ 803 void \ 804 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 805 void *v; \ 806 bus_space_handle_t h1, h2; \ 807 bus_size_t o1, o2, c; \ 808 { \ 809 bus_size_t o; \ 810 \ 811 if ((h1 + o1) >= (h2 + o2)) { \ 812 /* src after dest: copy forward */ \ 813 for (o = 0; c != 0; c--, o += BYTES) \ 814 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 815 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 816 } else { \ 817 /* dest after src: copy backwards */ \ 818 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 819 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 820 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 821 } \ 822 } 823 CHIP_io_copy_region_N(1) 824 CHIP_io_copy_region_N(2) 825 CHIP_io_copy_region_N(4) 826 CHIP_io_copy_region_N(8) 827
Indexes created Tue Oct 14 06:10:07 GMT 2025