pci_swiz_bus_io_chipdep.c revision 1.28
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.28 1999/12/07 05:44:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE Sparse I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *, int)); 93 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t, int)); 95 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 /* allocation/deallocation */ 99 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 100 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 101 bus_space_handle_t *)); 102 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 103 bus_size_t)); 104 105 /* barrier */ 106 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 107 bus_size_t, bus_size_t, int)); 108 109 /* read (single) */ 110 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 115 bus_size_t)); 116 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 117 bus_size_t)); 118 119 /* read multiple */ 120 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 121 bus_size_t, u_int8_t *, bus_size_t)); 122 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 123 bus_size_t, u_int16_t *, bus_size_t)); 124 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 125 bus_size_t, u_int32_t *, bus_size_t)); 126 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 127 bus_size_t, u_int64_t *, bus_size_t)); 128 129 /* read region */ 130 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* write (single) */ 140 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t)); 142 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t)); 144 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t)); 146 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t)); 148 149 /* write multiple */ 150 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 151 bus_size_t, const u_int8_t *, bus_size_t)); 152 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 153 bus_size_t, const u_int16_t *, bus_size_t)); 154 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 155 bus_size_t, const u_int32_t *, bus_size_t)); 156 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 157 bus_size_t, const u_int64_t *, bus_size_t)); 158 159 /* write region */ 160 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* set multiple */ 170 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 171 bus_size_t, u_int8_t, bus_size_t)); 172 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 173 bus_size_t, u_int16_t, bus_size_t)); 174 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 175 bus_size_t, u_int32_t, bus_size_t)); 176 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 177 bus_size_t, u_int64_t, bus_size_t)); 178 179 /* set region */ 180 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* copy */ 190 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 192 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 194 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 196 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 198 199 /* Internal */ 200 void __C(CHIP,_io_mapit) __P((void *, bus_addr_t, 201 bus_space_handle_t *)); 202 203 #ifndef CHIP_IO_EX_STORE 204 static long 205 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 206 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 207 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 208 #endif 209 210 #ifndef CHIP_ADDR_SHIFT 211 #define CHIP_ADDR_SHIFT 5 212 #endif 213 214 #ifndef CHIP_SIZE_SHIFT 215 #define CHIP_SIZE_SHIFT 3 216 #endif 217 218 void 219 __C(CHIP,_bus_io_init)(t, v) 220 bus_space_tag_t t; 221 void *v; 222 { 223 struct extent *ex; 224 225 /* 226 * Initialize the bus space tag. 227 */ 228 229 /* cookie */ 230 t->abs_cookie = v; 231 232 /* mapping/unmapping */ 233 t->abs_map = __C(CHIP,_io_map); 234 t->abs_unmap = __C(CHIP,_io_unmap); 235 t->abs_subregion = __C(CHIP,_io_subregion); 236 237 /* allocation/deallocation */ 238 t->abs_alloc = __C(CHIP,_io_alloc); 239 t->abs_free = __C(CHIP,_io_free); 240 241 /* barrier */ 242 t->abs_barrier = __C(CHIP,_io_barrier); 243 244 /* read (single) */ 245 t->abs_r_1 = __C(CHIP,_io_read_1); 246 t->abs_r_2 = __C(CHIP,_io_read_2); 247 t->abs_r_4 = __C(CHIP,_io_read_4); 248 t->abs_r_8 = __C(CHIP,_io_read_8); 249 250 /* read multiple */ 251 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 252 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 253 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 254 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 255 256 /* read region */ 257 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 258 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 259 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 260 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 261 262 /* write (single) */ 263 t->abs_w_1 = __C(CHIP,_io_write_1); 264 t->abs_w_2 = __C(CHIP,_io_write_2); 265 t->abs_w_4 = __C(CHIP,_io_write_4); 266 t->abs_w_8 = __C(CHIP,_io_write_8); 267 268 /* write multiple */ 269 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 270 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 271 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 272 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 273 274 /* write region */ 275 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 276 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 277 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 278 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 279 280 /* set multiple */ 281 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 282 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 283 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 284 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 285 286 /* set region */ 287 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 288 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 289 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 290 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 291 292 /* copy */ 293 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 294 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 295 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 296 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 297 298 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 299 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 300 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 301 EX_NOWAIT); 302 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 303 304 #ifdef CHIP_IO_W1_BUS_START 305 #ifdef EXTENT_DEBUG 306 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 307 CHIP_IO_W1_BUS_END(v)); 308 #endif 309 extent_free(ex, CHIP_IO_W1_BUS_START(v), 310 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 311 #endif 312 #ifdef CHIP_IO_W2_BUS_START 313 #ifdef EXTENT_DEBUG 314 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 315 CHIP_IO_W2_BUS_END(v)); 316 #endif 317 extent_free(ex, CHIP_IO_W2_BUS_START(v), 318 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 319 #endif 320 321 #ifdef EXTENT_DEBUG 322 extent_print(ex); 323 #endif 324 CHIP_IO_EXTENT(v) = ex; 325 } 326 327 void 328 __C(CHIP,_io_mapit)(v, ioaddr, iohp) 329 void *v; 330 bus_addr_t ioaddr; 331 bus_space_handle_t *iohp; 332 { 333 334 #ifdef CHIP_IO_W1_BUS_START 335 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 336 ioaddr <= CHIP_IO_W1_BUS_END(v)) { 337 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 338 CHIP_ADDR_SHIFT) + (ioaddr - CHIP_IO_W1_BUS_START(v)); 339 } else 340 #endif 341 #ifdef CHIP_IO_W2_BUS_START 342 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 343 ioaddr <= CHIP_IO_W2_BUS_END(v)) { 344 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 345 CHIP_ADDR_SHIFT) + (ioaddr - CHIP_IO_W2_BUS_START(v)); 346 } else 347 #endif 348 { 349 printf("\n"); 350 #ifdef CHIP_IO_W1_BUS_START 351 printf("%s: window[1]=0x%lx-0x%lx\n", 352 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 353 CHIP_IO_W1_BUS_END(v)); 354 #endif 355 #ifdef CHIP_IO_W2_BUS_START 356 printf("%s: window[2]=0x%lx-0x%lx\n", 357 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 358 CHIP_IO_W2_BUS_END(v)); 359 #endif 360 panic("%s: don't know how to map %lx", 361 __S(__C(CHIP,_io_mapit)), ioaddr); 362 } 363 } 364 365 int 366 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct) 367 void *v; 368 bus_addr_t ioaddr; 369 bus_size_t iosize; 370 int flags; 371 bus_space_handle_t *iohp; 372 int acct; 373 { 374 int linear = flags & BUS_SPACE_MAP_LINEAR; 375 int error; 376 377 /* 378 * Can't map i/o space linearly. 379 */ 380 if (linear) 381 return (EOPNOTSUPP); 382 383 if (acct == 0) { 384 /* 385 * XXX We should ensure that the region is actually 386 * XXX mappable, but nothing should really be using 387 * XXX this interface (only ISA PnP does, and only 388 * XXX via a machine-dependent hook), so we don't 389 * XXX bother. 390 */ 391 goto mapit; 392 } 393 394 #ifdef EXTENT_DEBUG 395 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 396 #endif 397 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 398 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 399 if (error) { 400 #ifdef EXTENT_DEBUG 401 printf("io: allocation failed (%d)\n", error); 402 extent_print(CHIP_IO_EXTENT(v)); 403 #endif 404 return (error); 405 } 406 407 mapit: 408 __C(CHIP,_io_mapit)(v, ioaddr, iohp); 409 410 return (0); 411 } 412 413 void 414 __C(CHIP,_io_unmap)(v, ioh, iosize, acct) 415 void *v; 416 bus_space_handle_t ioh; 417 bus_size_t iosize; 418 int acct; 419 { 420 bus_addr_t ioaddr; 421 int error; 422 423 if (acct == 0) 424 return; 425 426 #ifdef EXTENT_DEBUG 427 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 428 #endif 429 430 ioh = ALPHA_K0SEG_TO_PHYS(ioh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 431 432 #ifdef CHIP_IO_W1_BUS_START 433 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W1_SYS_START(v) && 434 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W1_SYS_END(v)) { 435 ioaddr = CHIP_IO_W1_BUS_START(v) + 436 (ioh - (CHIP_IO_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 437 } else 438 #endif 439 #ifdef CHIP_IO_W2_BUS_START 440 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W2_SYS_START(v) && 441 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W2_SYS_END(v)) { 442 ioaddr = CHIP_IO_W2_BUS_START(v) + 443 (ioh - (CHIP_IO_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 444 } else 445 #endif 446 { 447 printf("\n"); 448 #ifdef CHIP_IO_W1_BUS_START 449 printf("%s: sys window[1]=0x%lx-0x%lx\n", 450 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 451 CHIP_IO_W1_SYS_END(v)); 452 #endif 453 #ifdef CHIP_IO_W2_BUS_START 454 printf("%s: sys window[2]=0x%lx-0x%lx\n", 455 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 456 CHIP_IO_W2_SYS_END(v)); 457 #endif 458 panic("%s: don't know how to unmap %lx", 459 __S(__C(CHIP,_io_unmap)), (ioh << CHIP_ADDR_SHIFT)); 460 } 461 462 #ifdef EXTENT_DEBUG 463 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 464 #endif 465 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 466 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 467 if (error) { 468 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 469 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 470 error); 471 #ifdef EXTENT_DEBUG 472 extent_print(CHIP_IO_EXTENT(v)); 473 #endif 474 } 475 } 476 477 int 478 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 479 void *v; 480 bus_space_handle_t ioh, *nioh; 481 bus_size_t offset, size; 482 { 483 484 *nioh = ioh + offset; 485 return (0); 486 } 487 488 int 489 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 490 addrp, bshp) 491 void *v; 492 bus_addr_t rstart, rend, *addrp; 493 bus_size_t size, align, boundary; 494 int flags; 495 bus_space_handle_t *bshp; 496 { 497 int linear = flags & BUS_SPACE_MAP_LINEAR; 498 bus_addr_t ioaddr; 499 int error; 500 501 /* 502 * Can't map i/o space linearly. 503 */ 504 if (linear) 505 return (EOPNOTSUPP); 506 507 /* 508 * Do the requested allocation. 509 */ 510 #ifdef EXTENT_DEBUG 511 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 512 #endif 513 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 514 size, align, boundary, 515 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 516 &ioaddr); 517 if (error) { 518 #ifdef EXTENT_DEBUG 519 printf("io: allocation failed (%d)\n", error); 520 extent_print(CHIP_IO_EXTENT(v)); 521 #endif 522 return (error); 523 } 524 525 #ifdef EXTENT_DEBUG 526 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 527 #endif 528 529 *addrp = ioaddr; 530 __C(CHIP,_io_mapit)(v, ioaddr, bshp); 531 532 return (0); 533 } 534 535 void 536 __C(CHIP,_io_free)(v, bsh, size) 537 void *v; 538 bus_space_handle_t bsh; 539 bus_size_t size; 540 { 541 542 /* Unmap does all we need to do. */ 543 __C(CHIP,_io_unmap)(v, bsh, size, 1); 544 } 545 546 inline void 547 __C(CHIP,_io_barrier)(v, h, o, l, f) 548 void *v; 549 bus_space_handle_t h; 550 bus_size_t o, l; 551 int f; 552 { 553 554 if ((f & BUS_SPACE_BARRIER_READ) != 0) 555 alpha_mb(); 556 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 557 alpha_wmb(); 558 } 559 560 inline u_int8_t 561 __C(CHIP,_io_read_1)(v, ioh, off) 562 void *v; 563 bus_space_handle_t ioh; 564 bus_size_t off; 565 { 566 register bus_space_handle_t tmpioh; 567 register u_int32_t *port, val; 568 register u_int8_t rval; 569 register int offset; 570 571 alpha_mb(); 572 573 tmpioh = ioh + off; 574 offset = tmpioh & 3; 575 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 576 (0 << CHIP_SIZE_SHIFT)); 577 val = *port; 578 rval = ((val) >> (8 * offset)) & 0xff; 579 580 return rval; 581 } 582 583 inline u_int16_t 584 __C(CHIP,_io_read_2)(v, ioh, off) 585 void *v; 586 bus_space_handle_t ioh; 587 bus_size_t off; 588 { 589 register bus_space_handle_t tmpioh; 590 register u_int32_t *port, val; 591 register u_int16_t rval; 592 register int offset; 593 594 alpha_mb(); 595 596 tmpioh = ioh + off; 597 offset = tmpioh & 3; 598 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 599 (1 << CHIP_SIZE_SHIFT)); 600 val = *port; 601 rval = ((val) >> (8 * offset)) & 0xffff; 602 603 return rval; 604 } 605 606 inline u_int32_t 607 __C(CHIP,_io_read_4)(v, ioh, off) 608 void *v; 609 bus_space_handle_t ioh; 610 bus_size_t off; 611 { 612 register bus_space_handle_t tmpioh; 613 register u_int32_t *port, val; 614 register u_int32_t rval; 615 register int offset; 616 617 alpha_mb(); 618 619 tmpioh = ioh + off; 620 offset = tmpioh & 3; 621 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 622 (3 << CHIP_SIZE_SHIFT)); 623 val = *port; 624 #if 0 625 rval = ((val) >> (8 * offset)) & 0xffffffff; 626 #else 627 rval = val; 628 #endif 629 630 return rval; 631 } 632 633 inline u_int64_t 634 __C(CHIP,_io_read_8)(v, ioh, off) 635 void *v; 636 bus_space_handle_t ioh; 637 bus_size_t off; 638 { 639 640 /* XXX XXX XXX */ 641 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 642 } 643 644 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 645 void \ 646 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 647 void *v; \ 648 bus_space_handle_t h; \ 649 bus_size_t o, c; \ 650 TYPE *a; \ 651 { \ 652 \ 653 while (c-- > 0) { \ 654 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 655 BUS_SPACE_BARRIER_READ); \ 656 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 657 } \ 658 } 659 CHIP_io_read_multi_N(1,u_int8_t) 660 CHIP_io_read_multi_N(2,u_int16_t) 661 CHIP_io_read_multi_N(4,u_int32_t) 662 CHIP_io_read_multi_N(8,u_int64_t) 663 664 #define CHIP_io_read_region_N(BYTES,TYPE) \ 665 void \ 666 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 667 void *v; \ 668 bus_space_handle_t h; \ 669 bus_size_t o, c; \ 670 TYPE *a; \ 671 { \ 672 \ 673 while (c-- > 0) { \ 674 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 675 o += sizeof *a; \ 676 } \ 677 } 678 CHIP_io_read_region_N(1,u_int8_t) 679 CHIP_io_read_region_N(2,u_int16_t) 680 CHIP_io_read_region_N(4,u_int32_t) 681 CHIP_io_read_region_N(8,u_int64_t) 682 683 inline void 684 __C(CHIP,_io_write_1)(v, ioh, off, val) 685 void *v; 686 bus_space_handle_t ioh; 687 bus_size_t off; 688 u_int8_t val; 689 { 690 register bus_space_handle_t tmpioh; 691 register u_int32_t *port, nval; 692 register int offset; 693 694 tmpioh = ioh + off; 695 offset = tmpioh & 3; 696 nval = val << (8 * offset); 697 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 698 (0 << CHIP_SIZE_SHIFT)); 699 *port = nval; 700 alpha_mb(); 701 } 702 703 inline void 704 __C(CHIP,_io_write_2)(v, ioh, off, val) 705 void *v; 706 bus_space_handle_t ioh; 707 bus_size_t off; 708 u_int16_t val; 709 { 710 register bus_space_handle_t tmpioh; 711 register u_int32_t *port, nval; 712 register int offset; 713 714 tmpioh = ioh + off; 715 offset = tmpioh & 3; 716 nval = val << (8 * offset); 717 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 718 (1 << CHIP_SIZE_SHIFT)); 719 *port = nval; 720 alpha_mb(); 721 } 722 723 inline void 724 __C(CHIP,_io_write_4)(v, ioh, off, val) 725 void *v; 726 bus_space_handle_t ioh; 727 bus_size_t off; 728 u_int32_t val; 729 { 730 register bus_space_handle_t tmpioh; 731 register u_int32_t *port, nval; 732 register int offset; 733 734 tmpioh = ioh + off; 735 offset = tmpioh & 3; 736 nval = val /*<< (8 * offset)*/; 737 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 738 (3 << CHIP_SIZE_SHIFT)); 739 *port = nval; 740 alpha_mb(); 741 } 742 743 inline void 744 __C(CHIP,_io_write_8)(v, ioh, off, val) 745 void *v; 746 bus_space_handle_t ioh; 747 bus_size_t off; 748 u_int64_t val; 749 { 750 751 /* XXX XXX XXX */ 752 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 753 alpha_mb(); 754 } 755 756 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 757 void \ 758 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 759 void *v; \ 760 bus_space_handle_t h; \ 761 bus_size_t o, c; \ 762 const TYPE *a; \ 763 { \ 764 \ 765 while (c-- > 0) { \ 766 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 767 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 768 BUS_SPACE_BARRIER_WRITE); \ 769 } \ 770 } 771 CHIP_io_write_multi_N(1,u_int8_t) 772 CHIP_io_write_multi_N(2,u_int16_t) 773 CHIP_io_write_multi_N(4,u_int32_t) 774 CHIP_io_write_multi_N(8,u_int64_t) 775 776 #define CHIP_io_write_region_N(BYTES,TYPE) \ 777 void \ 778 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 779 void *v; \ 780 bus_space_handle_t h; \ 781 bus_size_t o, c; \ 782 const TYPE *a; \ 783 { \ 784 \ 785 while (c-- > 0) { \ 786 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 787 o += sizeof *a; \ 788 } \ 789 } 790 CHIP_io_write_region_N(1,u_int8_t) 791 CHIP_io_write_region_N(2,u_int16_t) 792 CHIP_io_write_region_N(4,u_int32_t) 793 CHIP_io_write_region_N(8,u_int64_t) 794 795 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 796 void \ 797 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 798 void *v; \ 799 bus_space_handle_t h; \ 800 bus_size_t o, c; \ 801 TYPE val; \ 802 { \ 803 \ 804 while (c-- > 0) { \ 805 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 806 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 807 BUS_SPACE_BARRIER_WRITE); \ 808 } \ 809 } 810 CHIP_io_set_multi_N(1,u_int8_t) 811 CHIP_io_set_multi_N(2,u_int16_t) 812 CHIP_io_set_multi_N(4,u_int32_t) 813 CHIP_io_set_multi_N(8,u_int64_t) 814 815 #define CHIP_io_set_region_N(BYTES,TYPE) \ 816 void \ 817 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 818 void *v; \ 819 bus_space_handle_t h; \ 820 bus_size_t o, c; \ 821 TYPE val; \ 822 { \ 823 \ 824 while (c-- > 0) { \ 825 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 826 o += sizeof val; \ 827 } \ 828 } 829 CHIP_io_set_region_N(1,u_int8_t) 830 CHIP_io_set_region_N(2,u_int16_t) 831 CHIP_io_set_region_N(4,u_int32_t) 832 CHIP_io_set_region_N(8,u_int64_t) 833 834 #define CHIP_io_copy_region_N(BYTES) \ 835 void \ 836 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 837 void *v; \ 838 bus_space_handle_t h1, h2; \ 839 bus_size_t o1, o2, c; \ 840 { \ 841 bus_size_t o; \ 842 \ 843 if ((h1 + o1) >= (h2 + o2)) { \ 844 /* src after dest: copy forward */ \ 845 for (o = 0; c != 0; c--, o += BYTES) \ 846 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 847 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 848 } else { \ 849 /* dest after src: copy backwards */ \ 850 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 851 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 852 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 853 } \ 854 } 855 CHIP_io_copy_region_N(1) 856 CHIP_io_copy_region_N(2) 857 CHIP_io_copy_region_N(4) 858 CHIP_io_copy_region_N(8) 859
Indexes created Mon Oct 13 16:09:52 GMT 2025