pci_swiz_bus_io_chipdep.c revision 1.29
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.29 2000/02/25 00:45:05 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE Sparse I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *, int)); 93 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t, int)); 95 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 int __C(CHIP,_io_translate) __P((void *, bus_addr_t, bus_size_t, 99 int, struct alpha_bus_space_translation *)); 100 101 /* allocation/deallocation */ 102 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 103 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 104 bus_space_handle_t *)); 105 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 106 bus_size_t)); 107 108 /* barrier */ 109 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 110 bus_size_t, bus_size_t, int)); 111 112 /* read (single) */ 113 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 114 bus_size_t)); 115 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 116 bus_size_t)); 117 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 118 bus_size_t)); 119 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 120 bus_size_t)); 121 122 /* read multiple */ 123 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 124 bus_size_t, u_int8_t *, bus_size_t)); 125 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 126 bus_size_t, u_int16_t *, bus_size_t)); 127 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 128 bus_size_t, u_int32_t *, bus_size_t)); 129 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 130 bus_size_t, u_int64_t *, bus_size_t)); 131 132 /* read region */ 133 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t *, bus_size_t)); 135 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t *, bus_size_t)); 137 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t *, bus_size_t)); 139 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t *, bus_size_t)); 141 142 /* write (single) */ 143 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t)); 145 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t)); 147 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t)); 149 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t)); 151 152 /* write multiple */ 153 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 154 bus_size_t, const u_int8_t *, bus_size_t)); 155 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 156 bus_size_t, const u_int16_t *, bus_size_t)); 157 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 158 bus_size_t, const u_int32_t *, bus_size_t)); 159 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 160 bus_size_t, const u_int64_t *, bus_size_t)); 161 162 /* write region */ 163 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 164 bus_size_t, const u_int8_t *, bus_size_t)); 165 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 166 bus_size_t, const u_int16_t *, bus_size_t)); 167 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 168 bus_size_t, const u_int32_t *, bus_size_t)); 169 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 170 bus_size_t, const u_int64_t *, bus_size_t)); 171 172 /* set multiple */ 173 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 174 bus_size_t, u_int8_t, bus_size_t)); 175 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 176 bus_size_t, u_int16_t, bus_size_t)); 177 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 178 bus_size_t, u_int32_t, bus_size_t)); 179 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 180 bus_size_t, u_int64_t, bus_size_t)); 181 182 /* set region */ 183 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 184 bus_size_t, u_int8_t, bus_size_t)); 185 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 186 bus_size_t, u_int16_t, bus_size_t)); 187 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 188 bus_size_t, u_int32_t, bus_size_t)); 189 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 190 bus_size_t, u_int64_t, bus_size_t)); 191 192 /* copy */ 193 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 194 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 195 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 196 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 197 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 198 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 199 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 200 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 201 202 #ifndef CHIP_IO_EX_STORE 203 static long 204 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 205 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 206 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 207 #endif 208 209 #ifndef CHIP_ADDR_SHIFT 210 #define CHIP_ADDR_SHIFT 5 211 #endif 212 213 #ifndef CHIP_SIZE_SHIFT 214 #define CHIP_SIZE_SHIFT 3 215 #endif 216 217 void 218 __C(CHIP,_bus_io_init)(t, v) 219 bus_space_tag_t t; 220 void *v; 221 { 222 struct extent *ex; 223 224 /* 225 * Initialize the bus space tag. 226 */ 227 228 /* cookie */ 229 t->abs_cookie = v; 230 231 /* mapping/unmapping */ 232 t->abs_map = __C(CHIP,_io_map); 233 t->abs_unmap = __C(CHIP,_io_unmap); 234 t->abs_subregion = __C(CHIP,_io_subregion); 235 236 t->abs_translate = __C(CHIP,_io_translate); 237 238 /* allocation/deallocation */ 239 t->abs_alloc = __C(CHIP,_io_alloc); 240 t->abs_free = __C(CHIP,_io_free); 241 242 /* barrier */ 243 t->abs_barrier = __C(CHIP,_io_barrier); 244 245 /* read (single) */ 246 t->abs_r_1 = __C(CHIP,_io_read_1); 247 t->abs_r_2 = __C(CHIP,_io_read_2); 248 t->abs_r_4 = __C(CHIP,_io_read_4); 249 t->abs_r_8 = __C(CHIP,_io_read_8); 250 251 /* read multiple */ 252 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 253 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 254 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 255 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 256 257 /* read region */ 258 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 259 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 260 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 261 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 262 263 /* write (single) */ 264 t->abs_w_1 = __C(CHIP,_io_write_1); 265 t->abs_w_2 = __C(CHIP,_io_write_2); 266 t->abs_w_4 = __C(CHIP,_io_write_4); 267 t->abs_w_8 = __C(CHIP,_io_write_8); 268 269 /* write multiple */ 270 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 271 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 272 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 273 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 274 275 /* write region */ 276 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 277 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 278 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 279 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 280 281 /* set multiple */ 282 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 283 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 284 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 285 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 286 287 /* set region */ 288 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 289 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 290 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 291 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 292 293 /* copy */ 294 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 295 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 296 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 297 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 298 299 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 300 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 301 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 302 EX_NOWAIT); 303 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 304 305 #ifdef CHIP_IO_W1_BUS_START 306 #ifdef EXTENT_DEBUG 307 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 308 CHIP_IO_W1_BUS_END(v)); 309 #endif 310 extent_free(ex, CHIP_IO_W1_BUS_START(v), 311 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 312 #endif 313 #ifdef CHIP_IO_W2_BUS_START 314 #ifdef EXTENT_DEBUG 315 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 316 CHIP_IO_W2_BUS_END(v)); 317 #endif 318 extent_free(ex, CHIP_IO_W2_BUS_START(v), 319 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 320 #endif 321 322 #ifdef EXTENT_DEBUG 323 extent_print(ex); 324 #endif 325 CHIP_IO_EXTENT(v) = ex; 326 } 327 328 int 329 __C(CHIP,_io_translate)(v, ioaddr, iolen, flags, abst) 330 void *v; 331 bus_addr_t ioaddr; 332 bus_size_t iolen; 333 int flags; 334 struct alpha_bus_space_translation *abst; 335 { 336 bus_addr_t ioend = ioaddr + (iolen - 1); 337 int linear = flags & BUS_SPACE_MAP_LINEAR; 338 339 /* 340 * Can't map i/o space linearly. 341 */ 342 if (linear) 343 return (EOPNOTSUPP); 344 345 #ifdef CHIP_IO_W1_BUS_START 346 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 347 ioend <= CHIP_IO_W1_BUS_END(v)) { 348 abst->abst_bus_start = CHIP_IO_W1_BUS_START(v); 349 abst->abst_bus_end = CHIP_IO_W1_BUS_END(v); 350 abst->abst_sys_start = CHIP_IO_W1_SYS_START(v); 351 abst->abst_sys_end = CHIP_IO_W1_SYS_END(v); 352 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 353 abst->abst_size_shift = CHIP_SIZE_SHIFT; 354 abst->abst_flags = 0; 355 return (0); 356 } 357 #endif 358 #ifdef CHIP_IO_W2_BUS_START 359 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 360 ioend <= CHIP_IO_W2_BUS_END(v)) { 361 abst->abst_bus_start = CHIP_IO_W2_BUS_START(v); 362 abst->abst_bus_end = CHIP_IO_W2_BUS_END(v); 363 abst->abst_sys_start = CHIP_IO_W2_SYS_START(v); 364 abst->abst_sys_end = CHIP_IO_W2_SYS_END(v); 365 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 366 abst->abst_size_shift = CHIP_SIZE_SHIFT; 367 abst->abst_flags = 0; 368 return (0); 369 } 370 #endif 371 #ifdef EXTENT_DEBUG 372 printf("\n"); 373 #ifdef CHIP_IO_W1_BUS_START 374 printf("%s: window[1]=0x%lx-0x%lx\n", 375 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 376 CHIP_IO_W1_BUS_END(v)); 377 #endif 378 #ifdef CHIP_IO_W2_BUS_START 379 printf("%s: window[2]=0x%lx-0x%lx\n", 380 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 381 CHIP_IO_W2_BUS_END(v)); 382 #endif 383 #endif /* EXTENT_DEBUG */ 384 /* No translation. */ 385 return (EINVAL); 386 } 387 388 int 389 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct) 390 void *v; 391 bus_addr_t ioaddr; 392 bus_size_t iosize; 393 int flags; 394 bus_space_handle_t *iohp; 395 int acct; 396 { 397 struct alpha_bus_space_translation abst; 398 int error; 399 400 /* 401 * Get the translation for this address. 402 */ 403 error = __C(CHIP,_io_translate)(v, ioaddr, iosize, flags, &abst); 404 if (error) 405 return (error); 406 407 if (acct == 0) 408 goto mapit; 409 410 #ifdef EXTENT_DEBUG 411 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 412 #endif 413 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 414 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 415 if (error) { 416 #ifdef EXTENT_DEBUG 417 printf("io: allocation failed (%d)\n", error); 418 extent_print(CHIP_IO_EXTENT(v)); 419 #endif 420 return (error); 421 } 422 423 mapit: 424 *iohp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 425 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 426 427 return (0); 428 } 429 430 void 431 __C(CHIP,_io_unmap)(v, ioh, iosize, acct) 432 void *v; 433 bus_space_handle_t ioh; 434 bus_size_t iosize; 435 int acct; 436 { 437 bus_addr_t ioaddr; 438 int error; 439 440 if (acct == 0) 441 return; 442 443 #ifdef EXTENT_DEBUG 444 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 445 #endif 446 447 ioh = ALPHA_K0SEG_TO_PHYS(ioh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 448 449 #ifdef CHIP_IO_W1_BUS_START 450 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W1_SYS_START(v) && 451 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W1_SYS_END(v)) { 452 ioaddr = CHIP_IO_W1_BUS_START(v) + 453 (ioh - (CHIP_IO_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 454 } else 455 #endif 456 #ifdef CHIP_IO_W2_BUS_START 457 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W2_SYS_START(v) && 458 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W2_SYS_END(v)) { 459 ioaddr = CHIP_IO_W2_BUS_START(v) + 460 (ioh - (CHIP_IO_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 461 } else 462 #endif 463 { 464 printf("\n"); 465 #ifdef CHIP_IO_W1_BUS_START 466 printf("%s: sys window[1]=0x%lx-0x%lx\n", 467 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 468 CHIP_IO_W1_SYS_END(v)); 469 #endif 470 #ifdef CHIP_IO_W2_BUS_START 471 printf("%s: sys window[2]=0x%lx-0x%lx\n", 472 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 473 CHIP_IO_W2_SYS_END(v)); 474 #endif 475 panic("%s: don't know how to unmap %lx", 476 __S(__C(CHIP,_io_unmap)), (ioh << CHIP_ADDR_SHIFT)); 477 } 478 479 #ifdef EXTENT_DEBUG 480 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 481 #endif 482 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 483 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 484 if (error) { 485 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 486 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 487 error); 488 #ifdef EXTENT_DEBUG 489 extent_print(CHIP_IO_EXTENT(v)); 490 #endif 491 } 492 } 493 494 int 495 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 496 void *v; 497 bus_space_handle_t ioh, *nioh; 498 bus_size_t offset, size; 499 { 500 501 *nioh = ioh + offset; 502 return (0); 503 } 504 505 int 506 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 507 addrp, bshp) 508 void *v; 509 bus_addr_t rstart, rend, *addrp; 510 bus_size_t size, align, boundary; 511 int flags; 512 bus_space_handle_t *bshp; 513 { 514 struct alpha_bus_space_translation abst; 515 int linear = flags & BUS_SPACE_MAP_LINEAR; 516 bus_addr_t ioaddr; 517 int error; 518 519 /* 520 * Can't map i/o space linearly. 521 */ 522 if (linear) 523 return (EOPNOTSUPP); 524 525 /* 526 * Do the requested allocation. 527 */ 528 #ifdef EXTENT_DEBUG 529 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 530 #endif 531 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 532 size, align, boundary, 533 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 534 &ioaddr); 535 if (error) { 536 #ifdef EXTENT_DEBUG 537 printf("io: allocation failed (%d)\n", error); 538 extent_print(CHIP_IO_EXTENT(v)); 539 #endif 540 return (error); 541 } 542 543 #ifdef EXTENT_DEBUG 544 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 545 #endif 546 547 error = __C(CHIP,_io_translate)(v, ioaddr, size, flags, &abst); 548 if (error) { 549 (void) extent_free(CHIP_IO_EXTENT(v), ioaddr, size, 550 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 551 return (error); 552 } 553 554 *addrp = ioaddr; 555 *bshp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 556 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 557 558 return (0); 559 } 560 561 void 562 __C(CHIP,_io_free)(v, bsh, size) 563 void *v; 564 bus_space_handle_t bsh; 565 bus_size_t size; 566 { 567 568 /* Unmap does all we need to do. */ 569 __C(CHIP,_io_unmap)(v, bsh, size, 1); 570 } 571 572 inline void 573 __C(CHIP,_io_barrier)(v, h, o, l, f) 574 void *v; 575 bus_space_handle_t h; 576 bus_size_t o, l; 577 int f; 578 { 579 580 if ((f & BUS_SPACE_BARRIER_READ) != 0) 581 alpha_mb(); 582 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 583 alpha_wmb(); 584 } 585 586 inline u_int8_t 587 __C(CHIP,_io_read_1)(v, ioh, off) 588 void *v; 589 bus_space_handle_t ioh; 590 bus_size_t off; 591 { 592 register bus_space_handle_t tmpioh; 593 register u_int32_t *port, val; 594 register u_int8_t rval; 595 register int offset; 596 597 alpha_mb(); 598 599 tmpioh = ioh + off; 600 offset = tmpioh & 3; 601 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 602 (0 << CHIP_SIZE_SHIFT)); 603 val = *port; 604 rval = ((val) >> (8 * offset)) & 0xff; 605 606 return rval; 607 } 608 609 inline u_int16_t 610 __C(CHIP,_io_read_2)(v, ioh, off) 611 void *v; 612 bus_space_handle_t ioh; 613 bus_size_t off; 614 { 615 register bus_space_handle_t tmpioh; 616 register u_int32_t *port, val; 617 register u_int16_t rval; 618 register int offset; 619 620 alpha_mb(); 621 622 tmpioh = ioh + off; 623 offset = tmpioh & 3; 624 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 625 (1 << CHIP_SIZE_SHIFT)); 626 val = *port; 627 rval = ((val) >> (8 * offset)) & 0xffff; 628 629 return rval; 630 } 631 632 inline u_int32_t 633 __C(CHIP,_io_read_4)(v, ioh, off) 634 void *v; 635 bus_space_handle_t ioh; 636 bus_size_t off; 637 { 638 register bus_space_handle_t tmpioh; 639 register u_int32_t *port, val; 640 register u_int32_t rval; 641 register int offset; 642 643 alpha_mb(); 644 645 tmpioh = ioh + off; 646 offset = tmpioh & 3; 647 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 648 (3 << CHIP_SIZE_SHIFT)); 649 val = *port; 650 #if 0 651 rval = ((val) >> (8 * offset)) & 0xffffffff; 652 #else 653 rval = val; 654 #endif 655 656 return rval; 657 } 658 659 inline u_int64_t 660 __C(CHIP,_io_read_8)(v, ioh, off) 661 void *v; 662 bus_space_handle_t ioh; 663 bus_size_t off; 664 { 665 666 /* XXX XXX XXX */ 667 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 668 } 669 670 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 671 void \ 672 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 673 void *v; \ 674 bus_space_handle_t h; \ 675 bus_size_t o, c; \ 676 TYPE *a; \ 677 { \ 678 \ 679 while (c-- > 0) { \ 680 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 681 BUS_SPACE_BARRIER_READ); \ 682 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 683 } \ 684 } 685 CHIP_io_read_multi_N(1,u_int8_t) 686 CHIP_io_read_multi_N(2,u_int16_t) 687 CHIP_io_read_multi_N(4,u_int32_t) 688 CHIP_io_read_multi_N(8,u_int64_t) 689 690 #define CHIP_io_read_region_N(BYTES,TYPE) \ 691 void \ 692 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 693 void *v; \ 694 bus_space_handle_t h; \ 695 bus_size_t o, c; \ 696 TYPE *a; \ 697 { \ 698 \ 699 while (c-- > 0) { \ 700 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 701 o += sizeof *a; \ 702 } \ 703 } 704 CHIP_io_read_region_N(1,u_int8_t) 705 CHIP_io_read_region_N(2,u_int16_t) 706 CHIP_io_read_region_N(4,u_int32_t) 707 CHIP_io_read_region_N(8,u_int64_t) 708 709 inline void 710 __C(CHIP,_io_write_1)(v, ioh, off, val) 711 void *v; 712 bus_space_handle_t ioh; 713 bus_size_t off; 714 u_int8_t val; 715 { 716 register bus_space_handle_t tmpioh; 717 register u_int32_t *port, nval; 718 register int offset; 719 720 tmpioh = ioh + off; 721 offset = tmpioh & 3; 722 nval = val << (8 * offset); 723 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 724 (0 << CHIP_SIZE_SHIFT)); 725 *port = nval; 726 alpha_mb(); 727 } 728 729 inline void 730 __C(CHIP,_io_write_2)(v, ioh, off, val) 731 void *v; 732 bus_space_handle_t ioh; 733 bus_size_t off; 734 u_int16_t val; 735 { 736 register bus_space_handle_t tmpioh; 737 register u_int32_t *port, nval; 738 register int offset; 739 740 tmpioh = ioh + off; 741 offset = tmpioh & 3; 742 nval = val << (8 * offset); 743 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 744 (1 << CHIP_SIZE_SHIFT)); 745 *port = nval; 746 alpha_mb(); 747 } 748 749 inline void 750 __C(CHIP,_io_write_4)(v, ioh, off, val) 751 void *v; 752 bus_space_handle_t ioh; 753 bus_size_t off; 754 u_int32_t val; 755 { 756 register bus_space_handle_t tmpioh; 757 register u_int32_t *port, nval; 758 register int offset; 759 760 tmpioh = ioh + off; 761 offset = tmpioh & 3; 762 nval = val /*<< (8 * offset)*/; 763 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 764 (3 << CHIP_SIZE_SHIFT)); 765 *port = nval; 766 alpha_mb(); 767 } 768 769 inline void 770 __C(CHIP,_io_write_8)(v, ioh, off, val) 771 void *v; 772 bus_space_handle_t ioh; 773 bus_size_t off; 774 u_int64_t val; 775 { 776 777 /* XXX XXX XXX */ 778 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 779 alpha_mb(); 780 } 781 782 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 783 void \ 784 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 785 void *v; \ 786 bus_space_handle_t h; \ 787 bus_size_t o, c; \ 788 const TYPE *a; \ 789 { \ 790 \ 791 while (c-- > 0) { \ 792 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 793 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 794 BUS_SPACE_BARRIER_WRITE); \ 795 } \ 796 } 797 CHIP_io_write_multi_N(1,u_int8_t) 798 CHIP_io_write_multi_N(2,u_int16_t) 799 CHIP_io_write_multi_N(4,u_int32_t) 800 CHIP_io_write_multi_N(8,u_int64_t) 801 802 #define CHIP_io_write_region_N(BYTES,TYPE) \ 803 void \ 804 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 805 void *v; \ 806 bus_space_handle_t h; \ 807 bus_size_t o, c; \ 808 const TYPE *a; \ 809 { \ 810 \ 811 while (c-- > 0) { \ 812 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 813 o += sizeof *a; \ 814 } \ 815 } 816 CHIP_io_write_region_N(1,u_int8_t) 817 CHIP_io_write_region_N(2,u_int16_t) 818 CHIP_io_write_region_N(4,u_int32_t) 819 CHIP_io_write_region_N(8,u_int64_t) 820 821 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 822 void \ 823 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 824 void *v; \ 825 bus_space_handle_t h; \ 826 bus_size_t o, c; \ 827 TYPE val; \ 828 { \ 829 \ 830 while (c-- > 0) { \ 831 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 832 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 833 BUS_SPACE_BARRIER_WRITE); \ 834 } \ 835 } 836 CHIP_io_set_multi_N(1,u_int8_t) 837 CHIP_io_set_multi_N(2,u_int16_t) 838 CHIP_io_set_multi_N(4,u_int32_t) 839 CHIP_io_set_multi_N(8,u_int64_t) 840 841 #define CHIP_io_set_region_N(BYTES,TYPE) \ 842 void \ 843 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 844 void *v; \ 845 bus_space_handle_t h; \ 846 bus_size_t o, c; \ 847 TYPE val; \ 848 { \ 849 \ 850 while (c-- > 0) { \ 851 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 852 o += sizeof val; \ 853 } \ 854 } 855 CHIP_io_set_region_N(1,u_int8_t) 856 CHIP_io_set_region_N(2,u_int16_t) 857 CHIP_io_set_region_N(4,u_int32_t) 858 CHIP_io_set_region_N(8,u_int64_t) 859 860 #define CHIP_io_copy_region_N(BYTES) \ 861 void \ 862 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 863 void *v; \ 864 bus_space_handle_t h1, h2; \ 865 bus_size_t o1, o2, c; \ 866 { \ 867 bus_size_t o; \ 868 \ 869 if ((h1 + o1) >= (h2 + o2)) { \ 870 /* src after dest: copy forward */ \ 871 for (o = 0; c != 0; c--, o += BYTES) \ 872 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 873 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 874 } else { \ 875 /* dest after src: copy backwards */ \ 876 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 877 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 878 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 879 } \ 880 } 881 CHIP_io_copy_region_N(1) 882 CHIP_io_copy_region_N(2) 883 CHIP_io_copy_region_N(4) 884 CHIP_io_copy_region_N(8) 885
Indexes created Wed Oct 15 16:09:53 GMT 2025