pci_swiz_bus_io_chipdep.c revision 1.30
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.30 2000/02/26 18:53:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE Sparse I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #define __C(A,B) __CONCAT(A,B) 88 #define __S(S) __STRING(S) 89 90 /* mapping/unmapping */ 91 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 92 bus_space_handle_t *, int)); 93 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 94 bus_size_t, int)); 95 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 96 bus_size_t, bus_size_t, bus_space_handle_t *)); 97 98 int __C(CHIP,_io_translate) __P((void *, bus_addr_t, bus_size_t, 99 int, struct alpha_bus_space_translation *)); 100 int __C(CHIP,_io_get_window) __P((void *, int, 101 struct alpha_bus_space_translation *)); 102 103 /* allocation/deallocation */ 104 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 105 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 106 bus_space_handle_t *)); 107 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 108 bus_size_t)); 109 110 /* barrier */ 111 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 112 bus_size_t, bus_size_t, int)); 113 114 /* read (single) */ 115 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 116 bus_size_t)); 117 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 118 bus_size_t)); 119 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 120 bus_size_t)); 121 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 122 bus_size_t)); 123 124 /* read multiple */ 125 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 126 bus_size_t, u_int8_t *, bus_size_t)); 127 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 128 bus_size_t, u_int16_t *, bus_size_t)); 129 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 130 bus_size_t, u_int32_t *, bus_size_t)); 131 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 132 bus_size_t, u_int64_t *, bus_size_t)); 133 134 /* read region */ 135 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 136 bus_size_t, u_int8_t *, bus_size_t)); 137 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 138 bus_size_t, u_int16_t *, bus_size_t)); 139 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 140 bus_size_t, u_int32_t *, bus_size_t)); 141 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 142 bus_size_t, u_int64_t *, bus_size_t)); 143 144 /* write (single) */ 145 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 146 bus_size_t, u_int8_t)); 147 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 148 bus_size_t, u_int16_t)); 149 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 150 bus_size_t, u_int32_t)); 151 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 152 bus_size_t, u_int64_t)); 153 154 /* write multiple */ 155 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 156 bus_size_t, const u_int8_t *, bus_size_t)); 157 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 158 bus_size_t, const u_int16_t *, bus_size_t)); 159 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 160 bus_size_t, const u_int32_t *, bus_size_t)); 161 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 162 bus_size_t, const u_int64_t *, bus_size_t)); 163 164 /* write region */ 165 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 166 bus_size_t, const u_int8_t *, bus_size_t)); 167 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 168 bus_size_t, const u_int16_t *, bus_size_t)); 169 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 170 bus_size_t, const u_int32_t *, bus_size_t)); 171 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 172 bus_size_t, const u_int64_t *, bus_size_t)); 173 174 /* set multiple */ 175 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 176 bus_size_t, u_int8_t, bus_size_t)); 177 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 178 bus_size_t, u_int16_t, bus_size_t)); 179 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 180 bus_size_t, u_int32_t, bus_size_t)); 181 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 182 bus_size_t, u_int64_t, bus_size_t)); 183 184 /* set region */ 185 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 186 bus_size_t, u_int8_t, bus_size_t)); 187 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 188 bus_size_t, u_int16_t, bus_size_t)); 189 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 190 bus_size_t, u_int32_t, bus_size_t)); 191 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 192 bus_size_t, u_int64_t, bus_size_t)); 193 194 /* copy */ 195 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 196 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 197 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 198 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 199 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 200 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 201 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 202 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 203 204 #ifndef CHIP_IO_EX_STORE 205 static long 206 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 207 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 208 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 209 #endif 210 211 #ifndef CHIP_ADDR_SHIFT 212 #define CHIP_ADDR_SHIFT 5 213 #endif 214 215 #ifndef CHIP_SIZE_SHIFT 216 #define CHIP_SIZE_SHIFT 3 217 #endif 218 219 void 220 __C(CHIP,_bus_io_init)(t, v) 221 bus_space_tag_t t; 222 void *v; 223 { 224 struct extent *ex; 225 226 /* 227 * Initialize the bus space tag. 228 */ 229 230 /* cookie */ 231 t->abs_cookie = v; 232 233 /* mapping/unmapping */ 234 t->abs_map = __C(CHIP,_io_map); 235 t->abs_unmap = __C(CHIP,_io_unmap); 236 t->abs_subregion = __C(CHIP,_io_subregion); 237 238 t->abs_translate = __C(CHIP,_io_translate); 239 t->abs_get_window = __C(CHIP,_io_get_window); 240 241 /* allocation/deallocation */ 242 t->abs_alloc = __C(CHIP,_io_alloc); 243 t->abs_free = __C(CHIP,_io_free); 244 245 /* barrier */ 246 t->abs_barrier = __C(CHIP,_io_barrier); 247 248 /* read (single) */ 249 t->abs_r_1 = __C(CHIP,_io_read_1); 250 t->abs_r_2 = __C(CHIP,_io_read_2); 251 t->abs_r_4 = __C(CHIP,_io_read_4); 252 t->abs_r_8 = __C(CHIP,_io_read_8); 253 254 /* read multiple */ 255 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 256 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 257 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 258 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 259 260 /* read region */ 261 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 262 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 263 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 264 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 265 266 /* write (single) */ 267 t->abs_w_1 = __C(CHIP,_io_write_1); 268 t->abs_w_2 = __C(CHIP,_io_write_2); 269 t->abs_w_4 = __C(CHIP,_io_write_4); 270 t->abs_w_8 = __C(CHIP,_io_write_8); 271 272 /* write multiple */ 273 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 274 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 275 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 276 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 277 278 /* write region */ 279 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 280 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 281 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 282 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 283 284 /* set multiple */ 285 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 286 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 287 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 288 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 289 290 /* set region */ 291 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 292 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 293 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 294 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 295 296 /* copy */ 297 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 298 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 299 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 300 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 301 302 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 303 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 304 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 305 EX_NOWAIT); 306 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 307 308 #ifdef CHIP_IO_W1_BUS_START 309 #ifdef EXTENT_DEBUG 310 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 311 CHIP_IO_W1_BUS_END(v)); 312 #endif 313 extent_free(ex, CHIP_IO_W1_BUS_START(v), 314 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 315 #endif 316 #ifdef CHIP_IO_W2_BUS_START 317 #ifdef EXTENT_DEBUG 318 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 319 CHIP_IO_W2_BUS_END(v)); 320 #endif 321 extent_free(ex, CHIP_IO_W2_BUS_START(v), 322 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 323 #endif 324 325 #ifdef EXTENT_DEBUG 326 extent_print(ex); 327 #endif 328 CHIP_IO_EXTENT(v) = ex; 329 } 330 331 int 332 __C(CHIP,_io_translate)(v, ioaddr, iolen, flags, abst) 333 void *v; 334 bus_addr_t ioaddr; 335 bus_size_t iolen; 336 int flags; 337 struct alpha_bus_space_translation *abst; 338 { 339 bus_addr_t ioend = ioaddr + (iolen - 1); 340 int linear = flags & BUS_SPACE_MAP_LINEAR; 341 342 /* 343 * Can't map i/o space linearly. 344 */ 345 if (linear) 346 return (EOPNOTSUPP); 347 348 #ifdef CHIP_IO_W1_BUS_START 349 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 350 ioend <= CHIP_IO_W1_BUS_END(v)) 351 return (__C(CHIP,_io_get_window)(v, 0, abst)); 352 #endif 353 354 #ifdef CHIP_IO_W2_BUS_START 355 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 356 ioend <= CHIP_IO_W2_BUS_END(v)) 357 return (__C(CHIP,_io_get_window)(v, 1, abst)); 358 #endif 359 360 #ifdef EXTENT_DEBUG 361 printf("\n"); 362 #ifdef CHIP_IO_W1_BUS_START 363 printf("%s: window[1]=0x%lx-0x%lx\n", 364 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 365 CHIP_IO_W1_BUS_END(v)); 366 #endif 367 #ifdef CHIP_IO_W2_BUS_START 368 printf("%s: window[2]=0x%lx-0x%lx\n", 369 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 370 CHIP_IO_W2_BUS_END(v)); 371 #endif 372 #endif /* EXTENT_DEBUG */ 373 /* No translation. */ 374 return (EINVAL); 375 } 376 377 int 378 __C(CHIP,_io_get_window)(v, window, abst) 379 void *v; 380 int window; 381 struct alpha_bus_space_translation *abst; 382 { 383 384 switch (window) { 385 #ifdef CHIP_IO_W1_BUS_START 386 case 0: 387 abst->abst_bus_start = CHIP_IO_W1_BUS_START(v); 388 abst->abst_bus_end = CHIP_IO_W1_BUS_END(v); 389 abst->abst_sys_start = CHIP_IO_W1_SYS_START(v); 390 abst->abst_sys_end = CHIP_IO_W1_SYS_END(v); 391 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 392 abst->abst_size_shift = CHIP_SIZE_SHIFT; 393 abst->abst_flags = 0; 394 break; 395 #endif 396 397 #ifdef CHIP_IO_W2_BUS_START 398 case 1: 399 abst->abst_bus_start = CHIP_IO_W2_BUS_START(v); 400 abst->abst_bus_end = CHIP_IO_W2_BUS_END(v); 401 abst->abst_sys_start = CHIP_IO_W2_SYS_START(v); 402 abst->abst_sys_end = CHIP_IO_W2_SYS_END(v); 403 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 404 abst->abst_size_shift = CHIP_SIZE_SHIFT; 405 abst->abst_flags = 0; 406 break; 407 #endif 408 409 default: 410 panic(__S(__C(CHIP,_io_get_window)) ": invalid window %d", 411 window); 412 } 413 414 return (0); 415 } 416 417 int 418 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct) 419 void *v; 420 bus_addr_t ioaddr; 421 bus_size_t iosize; 422 int flags; 423 bus_space_handle_t *iohp; 424 int acct; 425 { 426 struct alpha_bus_space_translation abst; 427 int error; 428 429 /* 430 * Get the translation for this address. 431 */ 432 error = __C(CHIP,_io_translate)(v, ioaddr, iosize, flags, &abst); 433 if (error) 434 return (error); 435 436 if (acct == 0) 437 goto mapit; 438 439 #ifdef EXTENT_DEBUG 440 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 441 #endif 442 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 443 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 444 if (error) { 445 #ifdef EXTENT_DEBUG 446 printf("io: allocation failed (%d)\n", error); 447 extent_print(CHIP_IO_EXTENT(v)); 448 #endif 449 return (error); 450 } 451 452 mapit: 453 *iohp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 454 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 455 456 return (0); 457 } 458 459 void 460 __C(CHIP,_io_unmap)(v, ioh, iosize, acct) 461 void *v; 462 bus_space_handle_t ioh; 463 bus_size_t iosize; 464 int acct; 465 { 466 bus_addr_t ioaddr; 467 int error; 468 469 if (acct == 0) 470 return; 471 472 #ifdef EXTENT_DEBUG 473 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 474 #endif 475 476 ioh = ALPHA_K0SEG_TO_PHYS(ioh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 477 478 #ifdef CHIP_IO_W1_BUS_START 479 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W1_SYS_START(v) && 480 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W1_SYS_END(v)) { 481 ioaddr = CHIP_IO_W1_BUS_START(v) + 482 (ioh - (CHIP_IO_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 483 } else 484 #endif 485 #ifdef CHIP_IO_W2_BUS_START 486 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W2_SYS_START(v) && 487 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W2_SYS_END(v)) { 488 ioaddr = CHIP_IO_W2_BUS_START(v) + 489 (ioh - (CHIP_IO_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 490 } else 491 #endif 492 { 493 printf("\n"); 494 #ifdef CHIP_IO_W1_BUS_START 495 printf("%s: sys window[1]=0x%lx-0x%lx\n", 496 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 497 CHIP_IO_W1_SYS_END(v)); 498 #endif 499 #ifdef CHIP_IO_W2_BUS_START 500 printf("%s: sys window[2]=0x%lx-0x%lx\n", 501 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 502 CHIP_IO_W2_SYS_END(v)); 503 #endif 504 panic("%s: don't know how to unmap %lx", 505 __S(__C(CHIP,_io_unmap)), (ioh << CHIP_ADDR_SHIFT)); 506 } 507 508 #ifdef EXTENT_DEBUG 509 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 510 #endif 511 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 512 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 513 if (error) { 514 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 515 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 516 error); 517 #ifdef EXTENT_DEBUG 518 extent_print(CHIP_IO_EXTENT(v)); 519 #endif 520 } 521 } 522 523 int 524 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 525 void *v; 526 bus_space_handle_t ioh, *nioh; 527 bus_size_t offset, size; 528 { 529 530 *nioh = ioh + offset; 531 return (0); 532 } 533 534 int 535 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 536 addrp, bshp) 537 void *v; 538 bus_addr_t rstart, rend, *addrp; 539 bus_size_t size, align, boundary; 540 int flags; 541 bus_space_handle_t *bshp; 542 { 543 struct alpha_bus_space_translation abst; 544 int linear = flags & BUS_SPACE_MAP_LINEAR; 545 bus_addr_t ioaddr; 546 int error; 547 548 /* 549 * Can't map i/o space linearly. 550 */ 551 if (linear) 552 return (EOPNOTSUPP); 553 554 /* 555 * Do the requested allocation. 556 */ 557 #ifdef EXTENT_DEBUG 558 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 559 #endif 560 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 561 size, align, boundary, 562 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 563 &ioaddr); 564 if (error) { 565 #ifdef EXTENT_DEBUG 566 printf("io: allocation failed (%d)\n", error); 567 extent_print(CHIP_IO_EXTENT(v)); 568 #endif 569 return (error); 570 } 571 572 #ifdef EXTENT_DEBUG 573 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 574 #endif 575 576 error = __C(CHIP,_io_translate)(v, ioaddr, size, flags, &abst); 577 if (error) { 578 (void) extent_free(CHIP_IO_EXTENT(v), ioaddr, size, 579 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 580 return (error); 581 } 582 583 *addrp = ioaddr; 584 *bshp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 585 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 586 587 return (0); 588 } 589 590 void 591 __C(CHIP,_io_free)(v, bsh, size) 592 void *v; 593 bus_space_handle_t bsh; 594 bus_size_t size; 595 { 596 597 /* Unmap does all we need to do. */ 598 __C(CHIP,_io_unmap)(v, bsh, size, 1); 599 } 600 601 inline void 602 __C(CHIP,_io_barrier)(v, h, o, l, f) 603 void *v; 604 bus_space_handle_t h; 605 bus_size_t o, l; 606 int f; 607 { 608 609 if ((f & BUS_SPACE_BARRIER_READ) != 0) 610 alpha_mb(); 611 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 612 alpha_wmb(); 613 } 614 615 inline u_int8_t 616 __C(CHIP,_io_read_1)(v, ioh, off) 617 void *v; 618 bus_space_handle_t ioh; 619 bus_size_t off; 620 { 621 register bus_space_handle_t tmpioh; 622 register u_int32_t *port, val; 623 register u_int8_t rval; 624 register int offset; 625 626 alpha_mb(); 627 628 tmpioh = ioh + off; 629 offset = tmpioh & 3; 630 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 631 (0 << CHIP_SIZE_SHIFT)); 632 val = *port; 633 rval = ((val) >> (8 * offset)) & 0xff; 634 635 return rval; 636 } 637 638 inline u_int16_t 639 __C(CHIP,_io_read_2)(v, ioh, off) 640 void *v; 641 bus_space_handle_t ioh; 642 bus_size_t off; 643 { 644 register bus_space_handle_t tmpioh; 645 register u_int32_t *port, val; 646 register u_int16_t rval; 647 register int offset; 648 649 alpha_mb(); 650 651 tmpioh = ioh + off; 652 offset = tmpioh & 3; 653 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 654 (1 << CHIP_SIZE_SHIFT)); 655 val = *port; 656 rval = ((val) >> (8 * offset)) & 0xffff; 657 658 return rval; 659 } 660 661 inline u_int32_t 662 __C(CHIP,_io_read_4)(v, ioh, off) 663 void *v; 664 bus_space_handle_t ioh; 665 bus_size_t off; 666 { 667 register bus_space_handle_t tmpioh; 668 register u_int32_t *port, val; 669 register u_int32_t rval; 670 register int offset; 671 672 alpha_mb(); 673 674 tmpioh = ioh + off; 675 offset = tmpioh & 3; 676 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 677 (3 << CHIP_SIZE_SHIFT)); 678 val = *port; 679 #if 0 680 rval = ((val) >> (8 * offset)) & 0xffffffff; 681 #else 682 rval = val; 683 #endif 684 685 return rval; 686 } 687 688 inline u_int64_t 689 __C(CHIP,_io_read_8)(v, ioh, off) 690 void *v; 691 bus_space_handle_t ioh; 692 bus_size_t off; 693 { 694 695 /* XXX XXX XXX */ 696 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 697 } 698 699 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 700 void \ 701 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 702 void *v; \ 703 bus_space_handle_t h; \ 704 bus_size_t o, c; \ 705 TYPE *a; \ 706 { \ 707 \ 708 while (c-- > 0) { \ 709 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 710 BUS_SPACE_BARRIER_READ); \ 711 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 712 } \ 713 } 714 CHIP_io_read_multi_N(1,u_int8_t) 715 CHIP_io_read_multi_N(2,u_int16_t) 716 CHIP_io_read_multi_N(4,u_int32_t) 717 CHIP_io_read_multi_N(8,u_int64_t) 718 719 #define CHIP_io_read_region_N(BYTES,TYPE) \ 720 void \ 721 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 722 void *v; \ 723 bus_space_handle_t h; \ 724 bus_size_t o, c; \ 725 TYPE *a; \ 726 { \ 727 \ 728 while (c-- > 0) { \ 729 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 730 o += sizeof *a; \ 731 } \ 732 } 733 CHIP_io_read_region_N(1,u_int8_t) 734 CHIP_io_read_region_N(2,u_int16_t) 735 CHIP_io_read_region_N(4,u_int32_t) 736 CHIP_io_read_region_N(8,u_int64_t) 737 738 inline void 739 __C(CHIP,_io_write_1)(v, ioh, off, val) 740 void *v; 741 bus_space_handle_t ioh; 742 bus_size_t off; 743 u_int8_t val; 744 { 745 register bus_space_handle_t tmpioh; 746 register u_int32_t *port, nval; 747 register int offset; 748 749 tmpioh = ioh + off; 750 offset = tmpioh & 3; 751 nval = val << (8 * offset); 752 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 753 (0 << CHIP_SIZE_SHIFT)); 754 *port = nval; 755 alpha_mb(); 756 } 757 758 inline void 759 __C(CHIP,_io_write_2)(v, ioh, off, val) 760 void *v; 761 bus_space_handle_t ioh; 762 bus_size_t off; 763 u_int16_t val; 764 { 765 register bus_space_handle_t tmpioh; 766 register u_int32_t *port, nval; 767 register int offset; 768 769 tmpioh = ioh + off; 770 offset = tmpioh & 3; 771 nval = val << (8 * offset); 772 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 773 (1 << CHIP_SIZE_SHIFT)); 774 *port = nval; 775 alpha_mb(); 776 } 777 778 inline void 779 __C(CHIP,_io_write_4)(v, ioh, off, val) 780 void *v; 781 bus_space_handle_t ioh; 782 bus_size_t off; 783 u_int32_t val; 784 { 785 register bus_space_handle_t tmpioh; 786 register u_int32_t *port, nval; 787 register int offset; 788 789 tmpioh = ioh + off; 790 offset = tmpioh & 3; 791 nval = val /*<< (8 * offset)*/; 792 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 793 (3 << CHIP_SIZE_SHIFT)); 794 *port = nval; 795 alpha_mb(); 796 } 797 798 inline void 799 __C(CHIP,_io_write_8)(v, ioh, off, val) 800 void *v; 801 bus_space_handle_t ioh; 802 bus_size_t off; 803 u_int64_t val; 804 { 805 806 /* XXX XXX XXX */ 807 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 808 alpha_mb(); 809 } 810 811 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 812 void \ 813 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 814 void *v; \ 815 bus_space_handle_t h; \ 816 bus_size_t o, c; \ 817 const TYPE *a; \ 818 { \ 819 \ 820 while (c-- > 0) { \ 821 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 822 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 823 BUS_SPACE_BARRIER_WRITE); \ 824 } \ 825 } 826 CHIP_io_write_multi_N(1,u_int8_t) 827 CHIP_io_write_multi_N(2,u_int16_t) 828 CHIP_io_write_multi_N(4,u_int32_t) 829 CHIP_io_write_multi_N(8,u_int64_t) 830 831 #define CHIP_io_write_region_N(BYTES,TYPE) \ 832 void \ 833 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 834 void *v; \ 835 bus_space_handle_t h; \ 836 bus_size_t o, c; \ 837 const TYPE *a; \ 838 { \ 839 \ 840 while (c-- > 0) { \ 841 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 842 o += sizeof *a; \ 843 } \ 844 } 845 CHIP_io_write_region_N(1,u_int8_t) 846 CHIP_io_write_region_N(2,u_int16_t) 847 CHIP_io_write_region_N(4,u_int32_t) 848 CHIP_io_write_region_N(8,u_int64_t) 849 850 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 851 void \ 852 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 853 void *v; \ 854 bus_space_handle_t h; \ 855 bus_size_t o, c; \ 856 TYPE val; \ 857 { \ 858 \ 859 while (c-- > 0) { \ 860 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 861 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 862 BUS_SPACE_BARRIER_WRITE); \ 863 } \ 864 } 865 CHIP_io_set_multi_N(1,u_int8_t) 866 CHIP_io_set_multi_N(2,u_int16_t) 867 CHIP_io_set_multi_N(4,u_int32_t) 868 CHIP_io_set_multi_N(8,u_int64_t) 869 870 #define CHIP_io_set_region_N(BYTES,TYPE) \ 871 void \ 872 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 873 void *v; \ 874 bus_space_handle_t h; \ 875 bus_size_t o, c; \ 876 TYPE val; \ 877 { \ 878 \ 879 while (c-- > 0) { \ 880 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 881 o += sizeof val; \ 882 } \ 883 } 884 CHIP_io_set_region_N(1,u_int8_t) 885 CHIP_io_set_region_N(2,u_int16_t) 886 CHIP_io_set_region_N(4,u_int32_t) 887 CHIP_io_set_region_N(8,u_int64_t) 888 889 #define CHIP_io_copy_region_N(BYTES) \ 890 void \ 891 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 892 void *v; \ 893 bus_space_handle_t h1, h2; \ 894 bus_size_t o1, o2, c; \ 895 { \ 896 bus_size_t o; \ 897 \ 898 if ((h1 + o1) >= (h2 + o2)) { \ 899 /* src after dest: copy forward */ \ 900 for (o = 0; c != 0; c--, o += BYTES) \ 901 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 902 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 903 } else { \ 904 /* dest after src: copy backwards */ \ 905 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 906 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 907 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 908 } \ 909 } 910 CHIP_io_copy_region_N(1) 911 CHIP_io_copy_region_N(2) 912 CHIP_io_copy_region_N(4) 913 CHIP_io_copy_region_N(8) 914
Indexes created Wed Oct 15 16:09:53 GMT 2025