pci_swiz_bus_io_chipdep.c revision 1.32.20.2
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.32.20.2 2004/09/18 14:31:12 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE Sparse I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/cdefs.h> 86 __KERNEL_RCSID(1, "$NetBSD: pci_swiz_bus_io_chipdep.c,v 1.32.20.2 2004/09/18 14:31:12 skrll Exp $"); 87 88 #include <sys/extent.h> 89 90 #define __C(A,B) __CONCAT(A,B) 91 #define __S(S) __STRING(S) 92 93 /* mapping/unmapping */ 94 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 95 bus_space_handle_t *, int)); 96 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 97 bus_size_t, int)); 98 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 99 bus_size_t, bus_size_t, bus_space_handle_t *)); 100 101 int __C(CHIP,_io_translate) __P((void *, bus_addr_t, bus_size_t, 102 int, struct alpha_bus_space_translation *)); 103 int __C(CHIP,_io_get_window) __P((void *, int, 104 struct alpha_bus_space_translation *)); 105 106 /* allocation/deallocation */ 107 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 108 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 109 bus_space_handle_t *)); 110 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 111 bus_size_t)); 112 113 /* get kernel virtual address */ 114 void * __C(CHIP,_io_vaddr) __P((void *, bus_space_handle_t)); 115 116 /* mmap for user */ 117 paddr_t __C(CHIP,_io_mmap) __P((void *, bus_addr_t, off_t, int, int)); 118 119 /* barrier */ 120 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 121 bus_size_t, bus_size_t, int)); 122 123 /* read (single) */ 124 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 125 bus_size_t)); 126 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 127 bus_size_t)); 128 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 129 bus_size_t)); 130 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 131 bus_size_t)); 132 133 /* read multiple */ 134 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int8_t *, bus_size_t)); 136 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int16_t *, bus_size_t)); 138 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int32_t *, bus_size_t)); 140 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int64_t *, bus_size_t)); 142 143 /* read region */ 144 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int8_t *, bus_size_t)); 146 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int16_t *, bus_size_t)); 148 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 149 bus_size_t, u_int32_t *, bus_size_t)); 150 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int64_t *, bus_size_t)); 152 153 /* write (single) */ 154 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 155 bus_size_t, u_int8_t)); 156 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int16_t)); 158 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 159 bus_size_t, u_int32_t)); 160 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 161 bus_size_t, u_int64_t)); 162 163 /* write multiple */ 164 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int8_t *, bus_size_t)); 166 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int16_t *, bus_size_t)); 168 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 169 bus_size_t, const u_int32_t *, bus_size_t)); 170 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int64_t *, bus_size_t)); 172 173 /* write region */ 174 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 175 bus_size_t, const u_int8_t *, bus_size_t)); 176 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int16_t *, bus_size_t)); 178 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 179 bus_size_t, const u_int32_t *, bus_size_t)); 180 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 181 bus_size_t, const u_int64_t *, bus_size_t)); 182 183 /* set multiple */ 184 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int8_t, bus_size_t)); 186 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int16_t, bus_size_t)); 188 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 189 bus_size_t, u_int32_t, bus_size_t)); 190 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int64_t, bus_size_t)); 192 193 /* set region */ 194 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 195 bus_size_t, u_int8_t, bus_size_t)); 196 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int16_t, bus_size_t)); 198 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 199 bus_size_t, u_int32_t, bus_size_t)); 200 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 201 bus_size_t, u_int64_t, bus_size_t)); 202 203 /* copy */ 204 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 205 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 206 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 208 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 209 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 210 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 211 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 212 213 #ifndef CHIP_IO_EX_STORE 214 static long 215 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 216 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 217 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 218 #endif 219 220 #ifndef CHIP_ADDR_SHIFT 221 #define CHIP_ADDR_SHIFT 5 222 #endif 223 224 #ifndef CHIP_SIZE_SHIFT 225 #define CHIP_SIZE_SHIFT 3 226 #endif 227 228 void 229 __C(CHIP,_bus_io_init)(t, v) 230 bus_space_tag_t t; 231 void *v; 232 { 233 struct extent *ex; 234 235 /* 236 * Initialize the bus space tag. 237 */ 238 239 /* cookie */ 240 t->abs_cookie = v; 241 242 /* mapping/unmapping */ 243 t->abs_map = __C(CHIP,_io_map); 244 t->abs_unmap = __C(CHIP,_io_unmap); 245 t->abs_subregion = __C(CHIP,_io_subregion); 246 247 t->abs_translate = __C(CHIP,_io_translate); 248 t->abs_get_window = __C(CHIP,_io_get_window); 249 250 /* allocation/deallocation */ 251 t->abs_alloc = __C(CHIP,_io_alloc); 252 t->abs_free = __C(CHIP,_io_free); 253 254 /* get kernel virtual address */ 255 t->abs_vaddr = __C(CHIP,_io_vaddr); 256 257 /* mmap for user */ 258 t->abs_mmap = __C(CHIP,_io_mmap); 259 260 /* barrier */ 261 t->abs_barrier = __C(CHIP,_io_barrier); 262 263 /* read (single) */ 264 t->abs_r_1 = __C(CHIP,_io_read_1); 265 t->abs_r_2 = __C(CHIP,_io_read_2); 266 t->abs_r_4 = __C(CHIP,_io_read_4); 267 t->abs_r_8 = __C(CHIP,_io_read_8); 268 269 /* read multiple */ 270 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 271 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 272 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 273 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 274 275 /* read region */ 276 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 277 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 278 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 279 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 280 281 /* write (single) */ 282 t->abs_w_1 = __C(CHIP,_io_write_1); 283 t->abs_w_2 = __C(CHIP,_io_write_2); 284 t->abs_w_4 = __C(CHIP,_io_write_4); 285 t->abs_w_8 = __C(CHIP,_io_write_8); 286 287 /* write multiple */ 288 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 289 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 290 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 291 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 292 293 /* write region */ 294 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 295 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 296 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 297 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 298 299 /* set multiple */ 300 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 301 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 302 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 303 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 304 305 /* set region */ 306 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 307 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 308 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 309 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 310 311 /* copy */ 312 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 313 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 314 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 315 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 316 317 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 318 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 319 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 320 EX_NOWAIT); 321 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 322 323 #ifdef CHIP_IO_W1_BUS_START 324 #ifdef EXTENT_DEBUG 325 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 326 CHIP_IO_W1_BUS_END(v)); 327 #endif 328 extent_free(ex, CHIP_IO_W1_BUS_START(v), 329 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 330 #endif 331 #ifdef CHIP_IO_W2_BUS_START 332 #ifdef EXTENT_DEBUG 333 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 334 CHIP_IO_W2_BUS_END(v)); 335 #endif 336 extent_free(ex, CHIP_IO_W2_BUS_START(v), 337 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 338 #endif 339 340 #ifdef EXTENT_DEBUG 341 extent_print(ex); 342 #endif 343 CHIP_IO_EXTENT(v) = ex; 344 } 345 346 int 347 __C(CHIP,_io_translate)(v, ioaddr, iolen, flags, abst) 348 void *v; 349 bus_addr_t ioaddr; 350 bus_size_t iolen; 351 int flags; 352 struct alpha_bus_space_translation *abst; 353 { 354 bus_addr_t ioend = ioaddr + (iolen - 1); 355 int linear = flags & BUS_SPACE_MAP_LINEAR; 356 357 /* 358 * Can't map i/o space linearly. 359 */ 360 if (linear) 361 return (EOPNOTSUPP); 362 363 #ifdef CHIP_IO_W1_BUS_START 364 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 365 ioend <= CHIP_IO_W1_BUS_END(v)) 366 return (__C(CHIP,_io_get_window)(v, 0, abst)); 367 #endif 368 369 #ifdef CHIP_IO_W2_BUS_START 370 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 371 ioend <= CHIP_IO_W2_BUS_END(v)) 372 return (__C(CHIP,_io_get_window)(v, 1, abst)); 373 #endif 374 375 #ifdef EXTENT_DEBUG 376 printf("\n"); 377 #ifdef CHIP_IO_W1_BUS_START 378 printf("%s: window[1]=0x%lx-0x%lx\n", 379 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 380 CHIP_IO_W1_BUS_END(v)); 381 #endif 382 #ifdef CHIP_IO_W2_BUS_START 383 printf("%s: window[2]=0x%lx-0x%lx\n", 384 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 385 CHIP_IO_W2_BUS_END(v)); 386 #endif 387 #endif /* EXTENT_DEBUG */ 388 /* No translation. */ 389 return (EINVAL); 390 } 391 392 int 393 __C(CHIP,_io_get_window)(v, window, abst) 394 void *v; 395 int window; 396 struct alpha_bus_space_translation *abst; 397 { 398 399 switch (window) { 400 #ifdef CHIP_IO_W1_BUS_START 401 case 0: 402 abst->abst_bus_start = CHIP_IO_W1_BUS_START(v); 403 abst->abst_bus_end = CHIP_IO_W1_BUS_END(v); 404 abst->abst_sys_start = CHIP_IO_W1_SYS_START(v); 405 abst->abst_sys_end = CHIP_IO_W1_SYS_END(v); 406 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 407 abst->abst_size_shift = CHIP_SIZE_SHIFT; 408 abst->abst_flags = 0; 409 break; 410 #endif 411 412 #ifdef CHIP_IO_W2_BUS_START 413 case 1: 414 abst->abst_bus_start = CHIP_IO_W2_BUS_START(v); 415 abst->abst_bus_end = CHIP_IO_W2_BUS_END(v); 416 abst->abst_sys_start = CHIP_IO_W2_SYS_START(v); 417 abst->abst_sys_end = CHIP_IO_W2_SYS_END(v); 418 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 419 abst->abst_size_shift = CHIP_SIZE_SHIFT; 420 abst->abst_flags = 0; 421 break; 422 #endif 423 424 default: 425 panic(__S(__C(CHIP,_io_get_window)) ": invalid window %d", 426 window); 427 } 428 429 return (0); 430 } 431 432 int 433 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct) 434 void *v; 435 bus_addr_t ioaddr; 436 bus_size_t iosize; 437 int flags; 438 bus_space_handle_t *iohp; 439 int acct; 440 { 441 struct alpha_bus_space_translation abst; 442 int error; 443 444 /* 445 * Get the translation for this address. 446 */ 447 error = __C(CHIP,_io_translate)(v, ioaddr, iosize, flags, &abst); 448 if (error) 449 return (error); 450 451 if (acct == 0) 452 goto mapit; 453 454 #ifdef EXTENT_DEBUG 455 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 456 #endif 457 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 458 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 459 if (error) { 460 #ifdef EXTENT_DEBUG 461 printf("io: allocation failed (%d)\n", error); 462 extent_print(CHIP_IO_EXTENT(v)); 463 #endif 464 return (error); 465 } 466 467 mapit: 468 *iohp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 469 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 470 471 return (0); 472 } 473 474 void 475 __C(CHIP,_io_unmap)(v, ioh, iosize, acct) 476 void *v; 477 bus_space_handle_t ioh; 478 bus_size_t iosize; 479 int acct; 480 { 481 bus_addr_t ioaddr; 482 int error; 483 484 if (acct == 0) 485 return; 486 487 #ifdef EXTENT_DEBUG 488 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 489 #endif 490 491 ioh = ALPHA_K0SEG_TO_PHYS(ioh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 492 493 #ifdef CHIP_IO_W1_BUS_START 494 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W1_SYS_START(v) && 495 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W1_SYS_END(v)) { 496 ioaddr = CHIP_IO_W1_BUS_START(v) + 497 (ioh - (CHIP_IO_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 498 } else 499 #endif 500 #ifdef CHIP_IO_W2_BUS_START 501 if ((ioh << CHIP_ADDR_SHIFT) >= CHIP_IO_W2_SYS_START(v) && 502 (ioh << CHIP_ADDR_SHIFT) <= CHIP_IO_W2_SYS_END(v)) { 503 ioaddr = CHIP_IO_W2_BUS_START(v) + 504 (ioh - (CHIP_IO_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 505 } else 506 #endif 507 { 508 printf("\n"); 509 #ifdef CHIP_IO_W1_BUS_START 510 printf("%s: sys window[1]=0x%lx-0x%lx\n", 511 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 512 CHIP_IO_W1_SYS_END(v)); 513 #endif 514 #ifdef CHIP_IO_W2_BUS_START 515 printf("%s: sys window[2]=0x%lx-0x%lx\n", 516 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 517 CHIP_IO_W2_SYS_END(v)); 518 #endif 519 panic("%s: don't know how to unmap %lx", 520 __S(__C(CHIP,_io_unmap)), (ioh << CHIP_ADDR_SHIFT)); 521 } 522 523 #ifdef EXTENT_DEBUG 524 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 525 #endif 526 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 527 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 528 if (error) { 529 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 530 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 531 error); 532 #ifdef EXTENT_DEBUG 533 extent_print(CHIP_IO_EXTENT(v)); 534 #endif 535 } 536 } 537 538 int 539 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 540 void *v; 541 bus_space_handle_t ioh, *nioh; 542 bus_size_t offset, size; 543 { 544 545 *nioh = ioh + offset; 546 return (0); 547 } 548 549 int 550 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 551 addrp, bshp) 552 void *v; 553 bus_addr_t rstart, rend, *addrp; 554 bus_size_t size, align, boundary; 555 int flags; 556 bus_space_handle_t *bshp; 557 { 558 struct alpha_bus_space_translation abst; 559 int linear = flags & BUS_SPACE_MAP_LINEAR; 560 bus_addr_t ioaddr; 561 int error; 562 563 /* 564 * Can't map i/o space linearly. 565 */ 566 if (linear) 567 return (EOPNOTSUPP); 568 569 /* 570 * Do the requested allocation. 571 */ 572 #ifdef EXTENT_DEBUG 573 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 574 #endif 575 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 576 size, align, boundary, 577 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 578 &ioaddr); 579 if (error) { 580 #ifdef EXTENT_DEBUG 581 printf("io: allocation failed (%d)\n", error); 582 extent_print(CHIP_IO_EXTENT(v)); 583 #endif 584 return (error); 585 } 586 587 #ifdef EXTENT_DEBUG 588 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 589 #endif 590 591 error = __C(CHIP,_io_translate)(v, ioaddr, size, flags, &abst); 592 if (error) { 593 (void) extent_free(CHIP_IO_EXTENT(v), ioaddr, size, 594 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 595 return (error); 596 } 597 598 *addrp = ioaddr; 599 *bshp = (ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start) >> 600 CHIP_ADDR_SHIFT) + (ioaddr - abst.abst_bus_start); 601 602 return (0); 603 } 604 605 void 606 __C(CHIP,_io_free)(v, bsh, size) 607 void *v; 608 bus_space_handle_t bsh; 609 bus_size_t size; 610 { 611 612 /* Unmap does all we need to do. */ 613 __C(CHIP,_io_unmap)(v, bsh, size, 1); 614 } 615 616 void * 617 __C(CHIP,_io_vaddr)(v, bsh) 618 void *v; 619 bus_space_handle_t bsh; 620 { 621 /* 622 * _io_translate() catches BUS_SPACE_MAP_LINEAR, 623 * so we shouldn't get here 624 */ 625 panic("_io_vaddr"); 626 } 627 628 paddr_t 629 __C(CHIP,_io_mmap)(v, addr, off, prot, flags) 630 void *v; 631 bus_addr_t addr; 632 off_t off; 633 int prot; 634 int flags; 635 { 636 637 /* Not supported for I/O space. */ 638 return (-1); 639 } 640 641 inline void 642 __C(CHIP,_io_barrier)(v, h, o, l, f) 643 void *v; 644 bus_space_handle_t h; 645 bus_size_t o, l; 646 int f; 647 { 648 649 if ((f & BUS_SPACE_BARRIER_READ) != 0) 650 alpha_mb(); 651 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 652 alpha_wmb(); 653 } 654 655 inline u_int8_t 656 __C(CHIP,_io_read_1)(v, ioh, off) 657 void *v; 658 bus_space_handle_t ioh; 659 bus_size_t off; 660 { 661 register bus_space_handle_t tmpioh; 662 register u_int32_t *port, val; 663 register u_int8_t rval; 664 register int offset; 665 666 alpha_mb(); 667 668 tmpioh = ioh + off; 669 offset = tmpioh & 3; 670 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 671 (0 << CHIP_SIZE_SHIFT)); 672 val = *port; 673 rval = ((val) >> (8 * offset)) & 0xff; 674 675 return rval; 676 } 677 678 inline u_int16_t 679 __C(CHIP,_io_read_2)(v, ioh, off) 680 void *v; 681 bus_space_handle_t ioh; 682 bus_size_t off; 683 { 684 register bus_space_handle_t tmpioh; 685 register u_int32_t *port, val; 686 register u_int16_t rval; 687 register int offset; 688 689 alpha_mb(); 690 691 tmpioh = ioh + off; 692 offset = tmpioh & 3; 693 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 694 (1 << CHIP_SIZE_SHIFT)); 695 val = *port; 696 rval = ((val) >> (8 * offset)) & 0xffff; 697 698 return rval; 699 } 700 701 inline u_int32_t 702 __C(CHIP,_io_read_4)(v, ioh, off) 703 void *v; 704 bus_space_handle_t ioh; 705 bus_size_t off; 706 { 707 register bus_space_handle_t tmpioh; 708 register u_int32_t *port, val; 709 register u_int32_t rval; 710 register int offset; 711 712 alpha_mb(); 713 714 tmpioh = ioh + off; 715 offset = tmpioh & 3; 716 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 717 (3 << CHIP_SIZE_SHIFT)); 718 val = *port; 719 #if 0 720 rval = ((val) >> (8 * offset)) & 0xffffffff; 721 #else 722 rval = val; 723 #endif 724 725 return rval; 726 } 727 728 inline u_int64_t 729 __C(CHIP,_io_read_8)(v, ioh, off) 730 void *v; 731 bus_space_handle_t ioh; 732 bus_size_t off; 733 { 734 735 /* XXX XXX XXX */ 736 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 737 } 738 739 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 740 void \ 741 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 742 void *v; \ 743 bus_space_handle_t h; \ 744 bus_size_t o, c; \ 745 TYPE *a; \ 746 { \ 747 \ 748 while (c-- > 0) { \ 749 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 750 BUS_SPACE_BARRIER_READ); \ 751 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 752 } \ 753 } 754 CHIP_io_read_multi_N(1,u_int8_t) 755 CHIP_io_read_multi_N(2,u_int16_t) 756 CHIP_io_read_multi_N(4,u_int32_t) 757 CHIP_io_read_multi_N(8,u_int64_t) 758 759 #define CHIP_io_read_region_N(BYTES,TYPE) \ 760 void \ 761 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 762 void *v; \ 763 bus_space_handle_t h; \ 764 bus_size_t o, c; \ 765 TYPE *a; \ 766 { \ 767 \ 768 while (c-- > 0) { \ 769 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 770 o += sizeof *a; \ 771 } \ 772 } 773 CHIP_io_read_region_N(1,u_int8_t) 774 CHIP_io_read_region_N(2,u_int16_t) 775 CHIP_io_read_region_N(4,u_int32_t) 776 CHIP_io_read_region_N(8,u_int64_t) 777 778 inline void 779 __C(CHIP,_io_write_1)(v, ioh, off, val) 780 void *v; 781 bus_space_handle_t ioh; 782 bus_size_t off; 783 u_int8_t val; 784 { 785 register bus_space_handle_t tmpioh; 786 register u_int32_t *port, nval; 787 register int offset; 788 789 tmpioh = ioh + off; 790 offset = tmpioh & 3; 791 nval = val << (8 * offset); 792 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 793 (0 << CHIP_SIZE_SHIFT)); 794 *port = nval; 795 alpha_mb(); 796 } 797 798 inline void 799 __C(CHIP,_io_write_2)(v, ioh, off, val) 800 void *v; 801 bus_space_handle_t ioh; 802 bus_size_t off; 803 u_int16_t val; 804 { 805 register bus_space_handle_t tmpioh; 806 register u_int32_t *port, nval; 807 register int offset; 808 809 tmpioh = ioh + off; 810 offset = tmpioh & 3; 811 nval = val << (8 * offset); 812 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 813 (1 << CHIP_SIZE_SHIFT)); 814 *port = nval; 815 alpha_mb(); 816 } 817 818 inline void 819 __C(CHIP,_io_write_4)(v, ioh, off, val) 820 void *v; 821 bus_space_handle_t ioh; 822 bus_size_t off; 823 u_int32_t val; 824 { 825 register bus_space_handle_t tmpioh; 826 register u_int32_t *port, nval; 827 register int offset; 828 829 tmpioh = ioh + off; 830 offset = tmpioh & 3; 831 nval = val /*<< (8 * offset)*/; 832 port = (u_int32_t *)((tmpioh << CHIP_ADDR_SHIFT) | 833 (3 << CHIP_SIZE_SHIFT)); 834 *port = nval; 835 alpha_mb(); 836 } 837 838 inline void 839 __C(CHIP,_io_write_8)(v, ioh, off, val) 840 void *v; 841 bus_space_handle_t ioh; 842 bus_size_t off; 843 u_int64_t val; 844 { 845 846 /* XXX XXX XXX */ 847 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 848 alpha_mb(); 849 } 850 851 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 852 void \ 853 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 854 void *v; \ 855 bus_space_handle_t h; \ 856 bus_size_t o, c; \ 857 const TYPE *a; \ 858 { \ 859 \ 860 while (c-- > 0) { \ 861 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 862 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 863 BUS_SPACE_BARRIER_WRITE); \ 864 } \ 865 } 866 CHIP_io_write_multi_N(1,u_int8_t) 867 CHIP_io_write_multi_N(2,u_int16_t) 868 CHIP_io_write_multi_N(4,u_int32_t) 869 CHIP_io_write_multi_N(8,u_int64_t) 870 871 #define CHIP_io_write_region_N(BYTES,TYPE) \ 872 void \ 873 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 874 void *v; \ 875 bus_space_handle_t h; \ 876 bus_size_t o, c; \ 877 const TYPE *a; \ 878 { \ 879 \ 880 while (c-- > 0) { \ 881 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 882 o += sizeof *a; \ 883 } \ 884 } 885 CHIP_io_write_region_N(1,u_int8_t) 886 CHIP_io_write_region_N(2,u_int16_t) 887 CHIP_io_write_region_N(4,u_int32_t) 888 CHIP_io_write_region_N(8,u_int64_t) 889 890 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 891 void \ 892 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 893 void *v; \ 894 bus_space_handle_t h; \ 895 bus_size_t o, c; \ 896 TYPE val; \ 897 { \ 898 \ 899 while (c-- > 0) { \ 900 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 901 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 902 BUS_SPACE_BARRIER_WRITE); \ 903 } \ 904 } 905 CHIP_io_set_multi_N(1,u_int8_t) 906 CHIP_io_set_multi_N(2,u_int16_t) 907 CHIP_io_set_multi_N(4,u_int32_t) 908 CHIP_io_set_multi_N(8,u_int64_t) 909 910 #define CHIP_io_set_region_N(BYTES,TYPE) \ 911 void \ 912 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 913 void *v; \ 914 bus_space_handle_t h; \ 915 bus_size_t o, c; \ 916 TYPE val; \ 917 { \ 918 \ 919 while (c-- > 0) { \ 920 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 921 o += sizeof val; \ 922 } \ 923 } 924 CHIP_io_set_region_N(1,u_int8_t) 925 CHIP_io_set_region_N(2,u_int16_t) 926 CHIP_io_set_region_N(4,u_int32_t) 927 CHIP_io_set_region_N(8,u_int64_t) 928 929 #define CHIP_io_copy_region_N(BYTES) \ 930 void \ 931 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 932 void *v; \ 933 bus_space_handle_t h1, h2; \ 934 bus_size_t o1, o2, c; \ 935 { \ 936 bus_size_t o; \ 937 \ 938 if ((h1 + o1) >= (h2 + o2)) { \ 939 /* src after dest: copy forward */ \ 940 for (o = 0; c != 0; c--, o += BYTES) \ 941 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 942 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 943 } else { \ 944 /* dest after src: copy backwards */ \ 945 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 946 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 947 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 948 } \ 949 } 950 CHIP_io_copy_region_N(1) 951 CHIP_io_copy_region_N(2) 952 CHIP_io_copy_region_N(4) 953 CHIP_io_copy_region_N(8) 954
Indexes created Mon Oct 13 16:09:52 GMT 2025