pci_swiz_bus_io_chipdep.c revision 1.4
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.4 1996/06/11 21:16:24 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #define __C(A,B) __CONCAT(A,B) 40 #define __S(S) __STRING(S) 41 42 int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, 43 bus_io_handle_t *)); 44 void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, 45 bus_io_size_t)); 46 int __C(CHIP,_io_subregion) __P((void *, bus_io_handle_t, 47 bus_io_size_t, bus_io_size_t, bus_io_handle_t *)); 48 u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, 49 bus_io_size_t)); 50 u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, 51 bus_io_size_t)); 52 u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, 53 bus_io_size_t)); 54 u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, 55 bus_io_size_t)); 56 void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t, 57 bus_io_size_t, u_int8_t *, bus_io_size_t)); 58 void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t, 59 bus_io_size_t, u_int16_t *, bus_io_size_t)); 60 void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t, 61 bus_io_size_t, u_int32_t *, bus_io_size_t)); 62 void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t, 63 bus_io_size_t, u_int64_t *, bus_io_size_t)); 64 void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, 65 bus_io_size_t, u_int8_t)); 66 void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, 67 bus_io_size_t, u_int16_t)); 68 void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, 69 bus_io_size_t, u_int32_t)); 70 void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, 71 bus_io_size_t, u_int64_t)); 72 void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t, 73 bus_io_size_t, const u_int8_t *, bus_io_size_t)); 74 void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t, 75 bus_io_size_t, const u_int16_t *, bus_io_size_t)); 76 void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t, 77 bus_io_size_t, const u_int32_t *, bus_io_size_t)); 78 void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t, 79 bus_io_size_t, const u_int64_t *, bus_io_size_t)); 80 81 void 82 __C(CHIP,_bus_io_init)(bc, iov) 83 bus_chipset_tag_t bc; 84 void *iov; 85 { 86 87 bc->bc_i_v = iov; 88 89 bc->bc_i_map = __C(CHIP,_io_map); 90 bc->bc_i_unmap = __C(CHIP,_io_unmap); 91 bc->bc_i_subregion = __C(CHIP,_io_subregion); 92 93 bc->bc_ir1 = __C(CHIP,_io_read_1); 94 bc->bc_ir2 = __C(CHIP,_io_read_2); 95 bc->bc_ir4 = __C(CHIP,_io_read_4); 96 bc->bc_ir8 = __C(CHIP,_io_read_8); 97 98 bc->bc_irm1 = __C(CHIP,_io_read_multi_1); 99 bc->bc_irm2 = __C(CHIP,_io_read_multi_2); 100 bc->bc_irm4 = __C(CHIP,_io_read_multi_4); 101 bc->bc_irm8 = __C(CHIP,_io_read_multi_8); 102 103 bc->bc_iw1 = __C(CHIP,_io_write_1); 104 bc->bc_iw2 = __C(CHIP,_io_write_2); 105 bc->bc_iw4 = __C(CHIP,_io_write_4); 106 bc->bc_iw8 = __C(CHIP,_io_write_8); 107 108 bc->bc_iwm1 = __C(CHIP,_io_write_multi_1); 109 bc->bc_iwm2 = __C(CHIP,_io_write_multi_2); 110 bc->bc_iwm4 = __C(CHIP,_io_write_multi_4); 111 bc->bc_iwm8 = __C(CHIP,_io_write_multi_8); 112 } 113 114 int 115 __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) 116 void *v; 117 bus_io_addr_t ioaddr; 118 bus_io_size_t iosize; 119 bus_io_handle_t *iohp; 120 { 121 122 *iohp = (phystok0seg(CHIP_IO_BASE) >> 5) + ioaddr; 123 return (0); 124 } 125 126 void 127 __C(CHIP,_io_unmap)(v, ioh, iosize) 128 void *v; 129 bus_io_handle_t ioh; 130 bus_io_size_t iosize; 131 { 132 133 /* XXX nothing to do. */ 134 } 135 136 int 137 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 138 void *v; 139 bus_io_handle_t ioh, *nioh; 140 bus_io_size_t offset, size; 141 { 142 143 *nioh = ioh + offset; 144 return (0); 145 } 146 147 u_int8_t 148 __C(CHIP,_io_read_1)(v, ioh, off) 149 void *v; 150 bus_io_handle_t ioh; 151 bus_io_size_t off; 152 { 153 register bus_io_handle_t tmpioh; 154 register u_int32_t *port, val; 155 register u_int8_t rval; 156 register int offset; 157 158 wbflush(); 159 160 tmpioh = ioh + off; 161 offset = tmpioh & 3; 162 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 163 val = *port; 164 rval = ((val) >> (8 * offset)) & 0xff; 165 166 return rval; 167 } 168 169 u_int16_t 170 __C(CHIP,_io_read_2)(v, ioh, off) 171 void *v; 172 bus_io_handle_t ioh; 173 bus_io_size_t off; 174 { 175 register bus_io_handle_t tmpioh; 176 register u_int32_t *port, val; 177 register u_int16_t rval; 178 register int offset; 179 180 wbflush(); 181 182 tmpioh = ioh + off; 183 offset = tmpioh & 3; 184 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 185 val = *port; 186 rval = ((val) >> (8 * offset)) & 0xffff; 187 188 return rval; 189 } 190 191 u_int32_t 192 __C(CHIP,_io_read_4)(v, ioh, off) 193 void *v; 194 bus_io_handle_t ioh; 195 bus_io_size_t off; 196 { 197 register bus_io_handle_t tmpioh; 198 register u_int32_t *port, val; 199 register u_int32_t rval; 200 register int offset; 201 202 wbflush(); 203 204 tmpioh = ioh + off; 205 offset = tmpioh & 3; 206 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 207 val = *port; 208 #if 0 209 rval = ((val) >> (8 * offset)) & 0xffffffff; 210 #else 211 rval = val; 212 #endif 213 214 return rval; 215 } 216 217 u_int64_t 218 __C(CHIP,_io_read_8)(v, ioh, off) 219 void *v; 220 bus_io_handle_t ioh; 221 bus_io_size_t off; 222 { 223 224 /* XXX XXX XXX */ 225 panic("%s not implemented\n", __S(__C(CHIP,_io_read_8))); 226 } 227 228 void 229 __C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count) 230 void *v; 231 bus_io_handle_t ioh; 232 bus_io_size_t off, count; 233 u_int8_t *addr; 234 { 235 register bus_io_handle_t tmpioh; 236 register u_int32_t *port, val; 237 register int offset; 238 239 wbflush(); 240 241 while (count--) { 242 tmpioh = ioh + off; 243 offset = tmpioh & 3; 244 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 245 val = *port; 246 *addr++ = ((val) >> (8 * offset)) & 0xff; 247 off++; 248 } 249 } 250 251 void 252 __C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count) 253 void *v; 254 bus_io_handle_t ioh; 255 bus_io_size_t off, count; 256 u_int16_t *addr; 257 { 258 register bus_io_handle_t tmpioh; 259 register u_int32_t *port, val; 260 register int offset; 261 262 wbflush(); 263 264 while (count--) { 265 tmpioh = ioh + off; 266 offset = tmpioh & 3; 267 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 268 val = *port; 269 *addr++ = ((val) >> (8 * offset)) & 0xffff; 270 off++; 271 } 272 } 273 274 void 275 __C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count) 276 void *v; 277 bus_io_handle_t ioh; 278 bus_io_size_t off, count; 279 u_int32_t *addr; 280 { 281 register bus_io_handle_t tmpioh; 282 register u_int32_t *port, val; 283 register int offset; 284 285 wbflush(); 286 287 while (count--) { 288 tmpioh = ioh + off; 289 offset = tmpioh & 3; 290 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 291 val = *port; 292 #if 0 293 *addr++ = ((val) >> (8 * offset)) & 0xffffffff; 294 #else 295 *addr++ = val; 296 #endif 297 off++; 298 } 299 } 300 301 void 302 __C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count) 303 void *v; 304 bus_io_handle_t ioh; 305 bus_io_size_t off, count; 306 u_int64_t *addr; 307 { 308 309 /* XXX XXX XXX */ 310 panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8))); 311 } 312 313 void 314 __C(CHIP,_io_write_1)(v, ioh, off, val) 315 void *v; 316 bus_io_handle_t ioh; 317 bus_io_size_t off; 318 u_int8_t val; 319 { 320 register bus_io_handle_t tmpioh; 321 register u_int32_t *port, nval; 322 register int offset; 323 324 tmpioh = ioh + off; 325 offset = tmpioh & 3; 326 nval = val << (8 * offset); 327 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 328 *port = nval; 329 wbflush(); 330 } 331 332 void 333 __C(CHIP,_io_write_2)(v, ioh, off, val) 334 void *v; 335 bus_io_handle_t ioh; 336 bus_io_size_t off; 337 u_int16_t val; 338 { 339 register bus_io_handle_t tmpioh; 340 register u_int32_t *port, nval; 341 register int offset; 342 343 tmpioh = ioh + off; 344 offset = tmpioh & 3; 345 nval = val << (8 * offset); 346 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 347 *port = nval; 348 wbflush(); 349 } 350 351 void 352 __C(CHIP,_io_write_4)(v, ioh, off, val) 353 void *v; 354 bus_io_handle_t ioh; 355 bus_io_size_t off; 356 u_int32_t val; 357 { 358 register bus_io_handle_t tmpioh; 359 register u_int32_t *port, nval; 360 register int offset; 361 362 tmpioh = ioh + off; 363 offset = tmpioh & 3; 364 nval = val /*<< (8 * offset)*/; 365 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 366 *port = nval; 367 wbflush(); 368 } 369 370 void 371 __C(CHIP,_io_write_8)(v, ioh, off, val) 372 void *v; 373 bus_io_handle_t ioh; 374 bus_io_size_t off; 375 u_int64_t val; 376 { 377 378 /* XXX XXX XXX */ 379 panic("%s not implemented\n", __S(__C(CHIP,_io_write_8))); 380 wbflush(); 381 } 382 383 void 384 __C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count) 385 void *v; 386 bus_io_handle_t ioh; 387 bus_io_size_t off, count; 388 const u_int8_t *addr; 389 { 390 register bus_io_handle_t tmpioh; 391 register u_int32_t *port, nval; 392 register int offset; 393 394 while (count--) { 395 tmpioh = ioh + off; 396 offset = tmpioh & 3; 397 nval = (*addr++) << (8 * offset); 398 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 399 *port = nval; 400 off++; 401 } 402 wbflush(); 403 } 404 405 void 406 __C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count) 407 void *v; 408 bus_io_handle_t ioh; 409 bus_io_size_t off, count; 410 const u_int16_t *addr; 411 { 412 register bus_io_handle_t tmpioh; 413 register u_int32_t *port, nval; 414 register int offset; 415 416 while (count--) { 417 tmpioh = ioh + off; 418 offset = tmpioh & 3; 419 nval = (*addr++) << (8 * offset); 420 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 421 *port = nval; 422 off++; 423 } 424 wbflush(); 425 } 426 427 void 428 __C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count) 429 void *v; 430 bus_io_handle_t ioh; 431 bus_io_size_t off, count; 432 const u_int32_t *addr; 433 { 434 register bus_io_handle_t tmpioh; 435 register u_int32_t *port, nval; 436 register int offset; 437 438 while (count--) { 439 tmpioh = ioh + off; 440 offset = tmpioh & 3; 441 nval = (*addr++) /*<< (8 * offset)*/; 442 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 443 *port = nval; 444 off++; 445 } 446 wbflush(); 447 } 448 449 void 450 __C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count) 451 void *v; 452 bus_io_handle_t ioh; 453 bus_io_size_t off, count; 454 const u_int64_t *addr; 455 { 456 457 /* XXX XXX XXX */ 458 panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8))); 459 } 460
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