pci_swiz_bus_io_chipdep.c revision 1.8
1 /* $NetBSD: pci_swiz_bus_io_chipdep.c,v 1.8 1996/10/13 03:00:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 32 * deal with only a single PCI interface chip in a machine. 33 * 34 * uses: 35 * CHIP name of the 'chip' it's being compiled for. 36 * CHIP_IO_BASE Sparse I/O space base to use. 37 */ 38 39 #define __C(A,B) __CONCAT(A,B) 40 #define __S(S) __STRING(S) 41 42 int __C(CHIP,_io_map) __P((void *, bus_io_addr_t, bus_io_size_t, 43 bus_io_handle_t *)); 44 void __C(CHIP,_io_unmap) __P((void *, bus_io_handle_t, 45 bus_io_size_t)); 46 int __C(CHIP,_io_subregion) __P((void *, bus_io_handle_t, 47 bus_io_size_t, bus_io_size_t, bus_io_handle_t *)); 48 u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_io_handle_t, 49 bus_io_size_t)); 50 u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_io_handle_t, 51 bus_io_size_t)); 52 u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_io_handle_t, 53 bus_io_size_t)); 54 u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_io_handle_t, 55 bus_io_size_t)); 56 void __C(CHIP,_io_read_multi_1) __P((void *, bus_io_handle_t, 57 bus_io_size_t, u_int8_t *, bus_io_size_t)); 58 void __C(CHIP,_io_read_multi_2) __P((void *, bus_io_handle_t, 59 bus_io_size_t, u_int16_t *, bus_io_size_t)); 60 void __C(CHIP,_io_read_multi_4) __P((void *, bus_io_handle_t, 61 bus_io_size_t, u_int32_t *, bus_io_size_t)); 62 void __C(CHIP,_io_read_multi_8) __P((void *, bus_io_handle_t, 63 bus_io_size_t, u_int64_t *, bus_io_size_t)); 64 void __C(CHIP,_io_write_1) __P((void *, bus_io_handle_t, 65 bus_io_size_t, u_int8_t)); 66 void __C(CHIP,_io_write_2) __P((void *, bus_io_handle_t, 67 bus_io_size_t, u_int16_t)); 68 void __C(CHIP,_io_write_4) __P((void *, bus_io_handle_t, 69 bus_io_size_t, u_int32_t)); 70 void __C(CHIP,_io_write_8) __P((void *, bus_io_handle_t, 71 bus_io_size_t, u_int64_t)); 72 void __C(CHIP,_io_write_multi_1) __P((void *, bus_io_handle_t, 73 bus_io_size_t, const u_int8_t *, bus_io_size_t)); 74 void __C(CHIP,_io_write_multi_2) __P((void *, bus_io_handle_t, 75 bus_io_size_t, const u_int16_t *, bus_io_size_t)); 76 void __C(CHIP,_io_write_multi_4) __P((void *, bus_io_handle_t, 77 bus_io_size_t, const u_int32_t *, bus_io_size_t)); 78 void __C(CHIP,_io_write_multi_8) __P((void *, bus_io_handle_t, 79 bus_io_size_t, const u_int64_t *, bus_io_size_t)); 80 81 void 82 __C(CHIP,_bus_io_init)(bc, iov) 83 bus_chipset_tag_t bc; 84 void *iov; 85 { 86 87 bc->bc_i_v = iov; 88 89 bc->bc_i_map = __C(CHIP,_io_map); 90 bc->bc_i_unmap = __C(CHIP,_io_unmap); 91 bc->bc_i_subregion = __C(CHIP,_io_subregion); 92 93 bc->bc_ir1 = __C(CHIP,_io_read_1); 94 bc->bc_ir2 = __C(CHIP,_io_read_2); 95 bc->bc_ir4 = __C(CHIP,_io_read_4); 96 bc->bc_ir8 = __C(CHIP,_io_read_8); 97 98 bc->bc_irm1 = __C(CHIP,_io_read_multi_1); 99 bc->bc_irm2 = __C(CHIP,_io_read_multi_2); 100 bc->bc_irm4 = __C(CHIP,_io_read_multi_4); 101 bc->bc_irm8 = __C(CHIP,_io_read_multi_8); 102 103 bc->bc_iw1 = __C(CHIP,_io_write_1); 104 bc->bc_iw2 = __C(CHIP,_io_write_2); 105 bc->bc_iw4 = __C(CHIP,_io_write_4); 106 bc->bc_iw8 = __C(CHIP,_io_write_8); 107 108 bc->bc_iwm1 = __C(CHIP,_io_write_multi_1); 109 bc->bc_iwm2 = __C(CHIP,_io_write_multi_2); 110 bc->bc_iwm4 = __C(CHIP,_io_write_multi_4); 111 bc->bc_iwm8 = __C(CHIP,_io_write_multi_8); 112 } 113 114 int 115 __C(CHIP,_io_map)(v, ioaddr, iosize, iohp) 116 void *v; 117 bus_io_addr_t ioaddr; 118 bus_io_size_t iosize; 119 bus_io_handle_t *iohp; 120 { 121 122 #ifdef CHIP_IO_W1_START 123 if (ioaddr >= CHIP_IO_W1_START(v) && 124 ioaddr <= CHIP_IO_W1_END(v)) { 125 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_BASE(v)) >> 5) + 126 (ioaddr & CHIP_IO_W1_MASK(v)); 127 } else 128 #endif 129 #ifdef CHIP_IO_W2_START 130 if (ioaddr >= CHIP_IO_W2_START(v) && 131 ioaddr <= CHIP_IO_W2_END(v)) { 132 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_BASE(v)) >> 5) + 133 (ioaddr & CHIP_IO_W2_MASK(v)); 134 } else 135 #endif 136 { 137 printf("\n"); 138 #ifdef CHIP_IO_W1_START 139 printf("%s: window[1]=0x%lx-0x%lx\n", 140 __S(__C(CHIP,_io_map)), CHIP_IO_W1_START(v), 141 CHIP_IO_W1_END(v)-1); 142 #endif 143 #ifdef CHIP_IO_W2_START 144 printf("%s: window[2]=0x%lx-0x%lx\n", 145 __S(__C(CHIP,_io_map)), CHIP_IO_W2_START(v), 146 CHIP_IO_W2_END(v)-1); 147 #endif 148 panic("%s: don't know how to map %lx non-cacheable\n", 149 __S(__C(CHIP,_io_map)), ioaddr); 150 } 151 152 return (0); 153 } 154 155 void 156 __C(CHIP,_io_unmap)(v, ioh, iosize) 157 void *v; 158 bus_io_handle_t ioh; 159 bus_io_size_t iosize; 160 { 161 162 /* XXX nothing to do. */ 163 } 164 165 int 166 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 167 void *v; 168 bus_io_handle_t ioh, *nioh; 169 bus_io_size_t offset, size; 170 { 171 172 *nioh = ioh + offset; 173 return (0); 174 } 175 176 u_int8_t 177 __C(CHIP,_io_read_1)(v, ioh, off) 178 void *v; 179 bus_io_handle_t ioh; 180 bus_io_size_t off; 181 { 182 register bus_io_handle_t tmpioh; 183 register u_int32_t *port, val; 184 register u_int8_t rval; 185 register int offset; 186 187 alpha_mb(); 188 189 tmpioh = ioh + off; 190 offset = tmpioh & 3; 191 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 192 val = *port; 193 rval = ((val) >> (8 * offset)) & 0xff; 194 195 return rval; 196 } 197 198 u_int16_t 199 __C(CHIP,_io_read_2)(v, ioh, off) 200 void *v; 201 bus_io_handle_t ioh; 202 bus_io_size_t off; 203 { 204 register bus_io_handle_t tmpioh; 205 register u_int32_t *port, val; 206 register u_int16_t rval; 207 register int offset; 208 209 alpha_mb(); 210 211 tmpioh = ioh + off; 212 offset = tmpioh & 3; 213 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 214 val = *port; 215 rval = ((val) >> (8 * offset)) & 0xffff; 216 217 return rval; 218 } 219 220 u_int32_t 221 __C(CHIP,_io_read_4)(v, ioh, off) 222 void *v; 223 bus_io_handle_t ioh; 224 bus_io_size_t off; 225 { 226 register bus_io_handle_t tmpioh; 227 register u_int32_t *port, val; 228 register u_int32_t rval; 229 register int offset; 230 231 alpha_mb(); 232 233 tmpioh = ioh + off; 234 offset = tmpioh & 3; 235 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 236 val = *port; 237 #if 0 238 rval = ((val) >> (8 * offset)) & 0xffffffff; 239 #else 240 rval = val; 241 #endif 242 243 return rval; 244 } 245 246 u_int64_t 247 __C(CHIP,_io_read_8)(v, ioh, off) 248 void *v; 249 bus_io_handle_t ioh; 250 bus_io_size_t off; 251 { 252 253 /* XXX XXX XXX */ 254 panic("%s not implemented\n", __S(__C(CHIP,_io_read_8))); 255 } 256 257 void 258 __C(CHIP,_io_read_multi_1)(v, ioh, off, addr, count) 259 void *v; 260 bus_io_handle_t ioh; 261 bus_io_size_t off, count; 262 u_int8_t *addr; 263 { 264 register bus_io_handle_t tmpioh; 265 register u_int32_t *port, val; 266 register int offset; 267 268 alpha_mb(); 269 270 while (count--) { 271 tmpioh = ioh + off; 272 offset = tmpioh & 3; 273 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 274 val = *port; 275 *addr++ = ((val) >> (8 * offset)) & 0xff; 276 off++; 277 } 278 } 279 280 void 281 __C(CHIP,_io_read_multi_2)(v, ioh, off, addr, count) 282 void *v; 283 bus_io_handle_t ioh; 284 bus_io_size_t off, count; 285 u_int16_t *addr; 286 { 287 register bus_io_handle_t tmpioh; 288 register u_int32_t *port, val; 289 register int offset; 290 291 alpha_mb(); 292 293 while (count--) { 294 tmpioh = ioh + off; 295 offset = tmpioh & 3; 296 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 297 val = *port; 298 *addr++ = ((val) >> (8 * offset)) & 0xffff; 299 off++; 300 } 301 } 302 303 void 304 __C(CHIP,_io_read_multi_4)(v, ioh, off, addr, count) 305 void *v; 306 bus_io_handle_t ioh; 307 bus_io_size_t off, count; 308 u_int32_t *addr; 309 { 310 register bus_io_handle_t tmpioh; 311 register u_int32_t *port, val; 312 register int offset; 313 314 alpha_mb(); 315 316 while (count--) { 317 tmpioh = ioh + off; 318 offset = tmpioh & 3; 319 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 320 val = *port; 321 #if 0 322 *addr++ = ((val) >> (8 * offset)) & 0xffffffff; 323 #else 324 *addr++ = val; 325 #endif 326 off++; 327 } 328 } 329 330 void 331 __C(CHIP,_io_read_multi_8)(v, ioh, off, addr, count) 332 void *v; 333 bus_io_handle_t ioh; 334 bus_io_size_t off, count; 335 u_int64_t *addr; 336 { 337 338 /* XXX XXX XXX */ 339 panic("%s not implemented\n", __S(__C(CHIP,_io_read_multi_8))); 340 } 341 342 void 343 __C(CHIP,_io_write_1)(v, ioh, off, val) 344 void *v; 345 bus_io_handle_t ioh; 346 bus_io_size_t off; 347 u_int8_t val; 348 { 349 register bus_io_handle_t tmpioh; 350 register u_int32_t *port, nval; 351 register int offset; 352 353 tmpioh = ioh + off; 354 offset = tmpioh & 3; 355 nval = val << (8 * offset); 356 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 357 *port = nval; 358 alpha_mb(); 359 } 360 361 void 362 __C(CHIP,_io_write_2)(v, ioh, off, val) 363 void *v; 364 bus_io_handle_t ioh; 365 bus_io_size_t off; 366 u_int16_t val; 367 { 368 register bus_io_handle_t tmpioh; 369 register u_int32_t *port, nval; 370 register int offset; 371 372 tmpioh = ioh + off; 373 offset = tmpioh & 3; 374 nval = val << (8 * offset); 375 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 376 *port = nval; 377 alpha_mb(); 378 } 379 380 void 381 __C(CHIP,_io_write_4)(v, ioh, off, val) 382 void *v; 383 bus_io_handle_t ioh; 384 bus_io_size_t off; 385 u_int32_t val; 386 { 387 register bus_io_handle_t tmpioh; 388 register u_int32_t *port, nval; 389 register int offset; 390 391 tmpioh = ioh + off; 392 offset = tmpioh & 3; 393 nval = val /*<< (8 * offset)*/; 394 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 395 *port = nval; 396 alpha_mb(); 397 } 398 399 void 400 __C(CHIP,_io_write_8)(v, ioh, off, val) 401 void *v; 402 bus_io_handle_t ioh; 403 bus_io_size_t off; 404 u_int64_t val; 405 { 406 407 /* XXX XXX XXX */ 408 panic("%s not implemented\n", __S(__C(CHIP,_io_write_8))); 409 alpha_mb(); 410 } 411 412 void 413 __C(CHIP,_io_write_multi_1)(v, ioh, off, addr, count) 414 void *v; 415 bus_io_handle_t ioh; 416 bus_io_size_t off, count; 417 const u_int8_t *addr; 418 { 419 register bus_io_handle_t tmpioh; 420 register u_int32_t *port, nval; 421 register int offset; 422 423 while (count--) { 424 tmpioh = ioh + off; 425 offset = tmpioh & 3; 426 nval = (*addr++) << (8 * offset); 427 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 428 *port = nval; 429 off++; 430 } 431 alpha_mb(); 432 } 433 434 void 435 __C(CHIP,_io_write_multi_2)(v, ioh, off, addr, count) 436 void *v; 437 bus_io_handle_t ioh; 438 bus_io_size_t off, count; 439 const u_int16_t *addr; 440 { 441 register bus_io_handle_t tmpioh; 442 register u_int32_t *port, nval; 443 register int offset; 444 445 while (count--) { 446 tmpioh = ioh + off; 447 offset = tmpioh & 3; 448 nval = (*addr++) << (8 * offset); 449 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 450 *port = nval; 451 off++; 452 } 453 alpha_mb(); 454 } 455 456 void 457 __C(CHIP,_io_write_multi_4)(v, ioh, off, addr, count) 458 void *v; 459 bus_io_handle_t ioh; 460 bus_io_size_t off, count; 461 const u_int32_t *addr; 462 { 463 register bus_io_handle_t tmpioh; 464 register u_int32_t *port, nval; 465 register int offset; 466 467 while (count--) { 468 tmpioh = ioh + off; 469 offset = tmpioh & 3; 470 nval = (*addr++) /*<< (8 * offset)*/; 471 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 472 *port = nval; 473 off++; 474 } 475 alpha_mb(); 476 } 477 478 void 479 __C(CHIP,_io_write_multi_8)(v, ioh, off, addr, count) 480 void *v; 481 bus_io_handle_t ioh; 482 bus_io_size_t off, count; 483 const u_int64_t *addr; 484 { 485 486 /* XXX XXX XXX */ 487 panic("%s not implemented\n", __S(__C(CHIP,_io_write_multi_8))); 488 } 489
Indexes created Tue Oct 14 08:09:56 GMT 2025