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sio_pic.c revision 1.30
      1  1.30   thorpej /* $NetBSD: sio_pic.c,v 1.30 2001/07/27 00:25:21 thorpej Exp $ */
      2  1.20   thorpej 
      3  1.20   thorpej /*-
      4  1.28   thorpej  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
      5  1.20   thorpej  * All rights reserved.
      6  1.20   thorpej  *
      7  1.20   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8  1.20   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  1.20   thorpej  * NASA Ames Research Center.
     10  1.20   thorpej  *
     11  1.20   thorpej  * Redistribution and use in source and binary forms, with or without
     12  1.20   thorpej  * modification, are permitted provided that the following conditions
     13  1.20   thorpej  * are met:
     14  1.20   thorpej  * 1. Redistributions of source code must retain the above copyright
     15  1.20   thorpej  *    notice, this list of conditions and the following disclaimer.
     16  1.20   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17  1.20   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18  1.20   thorpej  *    documentation and/or other materials provided with the distribution.
     19  1.20   thorpej  * 3. All advertising materials mentioning features or use of this software
     20  1.20   thorpej  *    must display the following acknowledgement:
     21  1.20   thorpej  *	This product includes software developed by the NetBSD
     22  1.20   thorpej  *	Foundation, Inc. and its contributors.
     23  1.20   thorpej  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24  1.20   thorpej  *    contributors may be used to endorse or promote products derived
     25  1.20   thorpej  *    from this software without specific prior written permission.
     26  1.20   thorpej  *
     27  1.20   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28  1.20   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29  1.20   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30  1.20   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31  1.20   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  1.20   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  1.20   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  1.20   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  1.20   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  1.20   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  1.20   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     38  1.20   thorpej  */
     39   1.1       cgd 
     40   1.1       cgd /*
     41   1.6       cgd  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
     42   1.1       cgd  * All rights reserved.
     43   1.1       cgd  *
     44   1.1       cgd  * Author: Chris G. Demetriou
     45   1.1       cgd  *
     46   1.1       cgd  * Permission to use, copy, modify and distribute this software and
     47   1.1       cgd  * its documentation is hereby granted, provided that both the copyright
     48   1.1       cgd  * notice and this permission notice appear in all copies of the
     49   1.1       cgd  * software, derivative works or modified versions, and any portions
     50   1.1       cgd  * thereof, and that both notices appear in supporting documentation.
     51   1.1       cgd  *
     52   1.1       cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     53   1.1       cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     54   1.1       cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     55   1.1       cgd  *
     56   1.1       cgd  * Carnegie Mellon requests users of this software to return to
     57   1.1       cgd  *
     58   1.1       cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     59   1.1       cgd  *  School of Computer Science
     60   1.1       cgd  *  Carnegie Mellon University
     61   1.1       cgd  *  Pittsburgh PA 15213-3890
     62   1.1       cgd  *
     63   1.1       cgd  * any improvements or extensions that they make and grant Carnegie the
     64   1.1       cgd  * rights to redistribute these changes.
     65   1.1       cgd  */
     66  1.17       cgd 
     67  1.18       cgd #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     68  1.18       cgd 
     69  1.30   thorpej __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.30 2001/07/27 00:25:21 thorpej Exp $");
     70   1.1       cgd 
     71   1.1       cgd #include <sys/param.h>
     72   1.1       cgd #include <sys/systm.h>
     73   1.1       cgd #include <sys/device.h>
     74   1.1       cgd #include <sys/malloc.h>
     75   1.1       cgd #include <sys/syslog.h>
     76   1.1       cgd 
     77   1.4       cgd #include <machine/intr.h>
     78   1.4       cgd #include <machine/bus.h>
     79   1.4       cgd 
     80  1.20   thorpej #include <dev/pci/pcireg.h>
     81  1.20   thorpej #include <dev/pci/pcivar.h>
     82  1.20   thorpej #include <dev/pci/pcidevs.h>
     83  1.20   thorpej 
     84  1.28   thorpej #include <dev/pci/cy82c693reg.h>
     85  1.28   thorpej #include <dev/pci/cy82c693var.h>
     86  1.28   thorpej 
     87   1.2       cgd #include <dev/isa/isareg.h>
     88   1.1       cgd #include <dev/isa/isavar.h>
     89   1.2       cgd #include <alpha/pci/siovar.h>
     90   1.2       cgd 
     91   1.2       cgd #include "sio.h"
     92   1.1       cgd 
     93   1.1       cgd /*
     94   1.1       cgd  * To add to the long history of wonderful PROM console traits,
     95   1.1       cgd  * AlphaStation PROMs don't reset themselves completely on boot!
     96   1.1       cgd  * Therefore, if an interrupt was turned on when the kernel was
     97   1.1       cgd  * started, we're not going to EVER turn it off...  I don't know
     98   1.1       cgd  * what will happen if new interrupts (that the PROM console doesn't
     99   1.1       cgd  * want) are turned on.  I'll burn that bridge when I come to it.
    100   1.1       cgd  */
    101   1.1       cgd #define	BROKEN_PROM_CONSOLE
    102   1.1       cgd 
    103   1.2       cgd /*
    104   1.2       cgd  * Private functions and variables.
    105   1.2       cgd  */
    106   1.4       cgd 
    107  1.14       cgd bus_space_tag_t sio_iot;
    108  1.20   thorpej pci_chipset_tag_t sio_pc;
    109  1.28   thorpej bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2;
    110   1.1       cgd 
    111   1.1       cgd #define	ICU_LEN		16		/* number of ISA IRQs */
    112   1.1       cgd 
    113  1.16       cgd static struct alpha_shared_intr *sio_intr;
    114   1.1       cgd 
    115   1.1       cgd #ifndef STRAY_MAX
    116   1.1       cgd #define	STRAY_MAX	5
    117   1.1       cgd #endif
    118   1.1       cgd 
    119   1.1       cgd #ifdef BROKEN_PROM_CONSOLE
    120   1.1       cgd /*
    121   1.1       cgd  * If prom console is broken, must remember the initial interrupt
    122   1.1       cgd  * settings and enforce them.  WHEE!
    123   1.1       cgd  */
    124  1.29   thorpej #define	INITIALLY_ENABLED(irq)						\
    125  1.29   thorpej 	((initial_ocw1[(irq) / 8] & (1 << ((irq) % 8))) == 0)
    126  1.29   thorpej #define	INITIALLY_LEVEL_TRIGGERED(irq)					\
    127  1.29   thorpej 	((initial_elcr[(irq) / 8] & (1 << ((irq) % 8))) != 0)
    128   1.1       cgd u_int8_t initial_ocw1[2];
    129   1.1       cgd u_int8_t initial_elcr[2];
    130  1.29   thorpej #else
    131  1.29   thorpej #define	INITIALLY_ENABLED(irq)		((irq) == 2 ? 1 : 0)
    132  1.29   thorpej #define	INITIALLY_LEVEL_TRIGGERED(irq)	0
    133   1.1       cgd #endif
    134   1.1       cgd 
    135  1.20   thorpej void		sio_setirqstat __P((int, int, int));
    136  1.20   thorpej 
    137  1.20   thorpej u_int8_t	(*sio_read_elcr) __P((int));
    138  1.20   thorpej void		(*sio_write_elcr) __P((int, u_int8_t));
    139  1.24      ross static void	specific_eoi __P((int));
    140  1.25   mycroft #ifdef BROKEN_PROM_CONSOLE
    141  1.25   mycroft void		sio_intr_shutdown __P((void *));
    142  1.25   mycroft #endif
    143  1.20   thorpej 
    144  1.20   thorpej /******************** i82378 SIO ELCR functions ********************/
    145  1.20   thorpej 
    146  1.20   thorpej int		i82378_setup_elcr __P((void));
    147  1.20   thorpej u_int8_t	i82378_read_elcr __P((int));
    148  1.20   thorpej void		i82378_write_elcr __P((int, u_int8_t));
    149  1.20   thorpej 
    150  1.28   thorpej bus_space_handle_t sio_ioh_elcr;
    151  1.28   thorpej 
    152  1.20   thorpej int
    153  1.20   thorpej i82378_setup_elcr()
    154  1.20   thorpej {
    155  1.20   thorpej 	int rv;
    156  1.20   thorpej 
    157  1.20   thorpej 	/*
    158  1.20   thorpej 	 * We could probe configuration space to see that there's
    159  1.20   thorpej 	 * actually an SIO present, but we are using this as a
    160  1.20   thorpej 	 * fall-back in case nothing else matches.
    161  1.20   thorpej 	 */
    162  1.20   thorpej 
    163  1.20   thorpej 	rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr);
    164  1.20   thorpej 
    165  1.20   thorpej 	if (rv == 0) {
    166  1.20   thorpej 		sio_read_elcr = i82378_read_elcr;
    167  1.20   thorpej 		sio_write_elcr = i82378_write_elcr;
    168  1.20   thorpej 	}
    169  1.20   thorpej 
    170  1.20   thorpej 	return (rv);
    171  1.20   thorpej }
    172  1.20   thorpej 
    173  1.20   thorpej u_int8_t
    174  1.20   thorpej i82378_read_elcr(elcr)
    175  1.20   thorpej 	int elcr;
    176  1.20   thorpej {
    177  1.20   thorpej 
    178  1.20   thorpej 	return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr));
    179  1.20   thorpej }
    180  1.20   thorpej 
    181  1.20   thorpej void
    182  1.20   thorpej i82378_write_elcr(elcr, val)
    183  1.20   thorpej 	int elcr;
    184  1.20   thorpej 	u_int8_t val;
    185  1.20   thorpej {
    186  1.20   thorpej 
    187  1.20   thorpej 	bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val);
    188  1.20   thorpej }
    189  1.20   thorpej 
    190  1.20   thorpej /******************** Cypress CY82C693 ELCR functions ********************/
    191  1.20   thorpej 
    192  1.20   thorpej int		cy82c693_setup_elcr __P((void));
    193  1.20   thorpej u_int8_t	cy82c693_read_elcr __P((int));
    194  1.20   thorpej void		cy82c693_write_elcr __P((int, u_int8_t));
    195  1.20   thorpej 
    196  1.28   thorpej const struct cy82c693_handle *sio_cy82c693_handle;
    197  1.28   thorpej 
    198  1.20   thorpej int
    199  1.20   thorpej cy82c693_setup_elcr()
    200  1.20   thorpej {
    201  1.20   thorpej 	int device, maxndevs;
    202  1.20   thorpej 	pcitag_t tag;
    203  1.20   thorpej 	pcireg_t id;
    204  1.20   thorpej 
    205  1.20   thorpej 	/*
    206  1.20   thorpej 	 * Search PCI configuration space for a Cypress CY82C693.
    207  1.20   thorpej 	 *
    208  1.20   thorpej 	 * Note we can make some assumptions about our bus number
    209  1.20   thorpej 	 * here, because:
    210  1.20   thorpej 	 *
    211  1.20   thorpej 	 *	(1) there can be at most one ISA/EISA bridge per PCI bus, and
    212  1.20   thorpej 	 *
    213  1.20   thorpej 	 *	(2) any ISA/EISA bridges must be attached to primary PCI
    214  1.20   thorpej 	 *	    busses (i.e. bus zero).
    215  1.20   thorpej 	 */
    216  1.20   thorpej 
    217  1.20   thorpej 	maxndevs = pci_bus_maxdevs(sio_pc, 0);
    218  1.20   thorpej 
    219  1.20   thorpej 	for (device = 0; device < maxndevs; device++) {
    220  1.20   thorpej 		tag = pci_make_tag(sio_pc, 0, device, 0);
    221  1.20   thorpej 		id = pci_conf_read(sio_pc, tag, PCI_ID_REG);
    222  1.20   thorpej 
    223  1.20   thorpej 		/* Invalid vendor ID value? */
    224  1.20   thorpej 		if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    225  1.20   thorpej 			continue;
    226  1.20   thorpej 		/* XXX Not invalid, but we've done this ~forever. */
    227  1.20   thorpej 		if (PCI_VENDOR(id) == 0)
    228  1.20   thorpej 			continue;
    229  1.20   thorpej 
    230  1.20   thorpej 		if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ ||
    231  1.20   thorpej 		    PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693)
    232  1.20   thorpej 			continue;
    233  1.20   thorpej 
    234  1.20   thorpej 		/*
    235  1.20   thorpej 		 * Found one!
    236  1.20   thorpej 		 */
    237  1.20   thorpej 
    238  1.20   thorpej #if 0
    239  1.20   thorpej 		printf("cy82c693_setup_elcr: found 82C693 at device %d\n",
    240  1.20   thorpej 		    device);
    241  1.20   thorpej #endif
    242  1.20   thorpej 
    243  1.28   thorpej 		sio_cy82c693_handle = cy82c693_init(sio_iot);
    244  1.20   thorpej 		sio_read_elcr = cy82c693_read_elcr;
    245  1.20   thorpej 		sio_write_elcr = cy82c693_write_elcr;
    246  1.20   thorpej 
    247  1.20   thorpej 		return (0);
    248  1.20   thorpej 	}
    249  1.20   thorpej 
    250  1.20   thorpej 	/*
    251  1.20   thorpej 	 * Didn't find a CY82C693.
    252  1.20   thorpej 	 */
    253  1.20   thorpej 	return (ENODEV);
    254  1.20   thorpej }
    255  1.20   thorpej 
    256  1.20   thorpej u_int8_t
    257  1.20   thorpej cy82c693_read_elcr(elcr)
    258  1.20   thorpej 	int elcr;
    259  1.20   thorpej {
    260  1.20   thorpej 
    261  1.28   thorpej 	return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr));
    262  1.20   thorpej }
    263  1.20   thorpej 
    264  1.20   thorpej void
    265  1.20   thorpej cy82c693_write_elcr(elcr, val)
    266  1.20   thorpej 	int elcr;
    267  1.20   thorpej 	u_int8_t val;
    268  1.20   thorpej {
    269  1.20   thorpej 
    270  1.28   thorpej 	cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val);
    271  1.20   thorpej }
    272  1.20   thorpej 
    273  1.20   thorpej /******************** ELCR access function configuration ********************/
    274  1.20   thorpej 
    275  1.20   thorpej /*
    276  1.20   thorpej  * Put the Intel SIO at the end, so we fall back on it if we don't
    277  1.20   thorpej  * find anything else.  If any of the non-Intel functions find a
    278  1.20   thorpej  * matching device, but are unable to map it for whatever reason,
    279  1.20   thorpej  * they should panic.
    280  1.20   thorpej  */
    281  1.20   thorpej 
    282  1.20   thorpej int (*sio_elcr_setup_funcs[]) __P((void)) = {
    283  1.20   thorpej 	cy82c693_setup_elcr,
    284  1.20   thorpej 	i82378_setup_elcr,
    285  1.20   thorpej 	NULL,
    286  1.20   thorpej };
    287  1.20   thorpej 
    288  1.20   thorpej /******************** Shared SIO/Cypress functions ********************/
    289  1.15       cgd 
    290   1.1       cgd void
    291   1.1       cgd sio_setirqstat(irq, enabled, type)
    292   1.1       cgd 	int irq, enabled;
    293   1.3   mycroft 	int type;
    294   1.1       cgd {
    295   1.1       cgd 	u_int8_t ocw1[2], elcr[2];
    296   1.1       cgd 	int icu, bit;
    297   1.1       cgd 
    298   1.1       cgd #if 0
    299  1.13  christos 	printf("sio_setirqstat: irq %d: %s, %s\n", irq,
    300   1.1       cgd 	    enabled ? "enabled" : "disabled", isa_intr_typename(type));
    301   1.1       cgd #endif
    302   1.1       cgd 
    303   1.1       cgd 	icu = irq / 8;
    304   1.1       cgd 	bit = irq % 8;
    305   1.1       cgd 
    306  1.14       cgd 	ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
    307  1.14       cgd 	ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
    308  1.20   thorpej 	elcr[0] = (*sio_read_elcr)(0);				/* XXX */
    309  1.20   thorpej 	elcr[1] = (*sio_read_elcr)(1);				/* XXX */
    310   1.1       cgd 
    311   1.1       cgd 	/*
    312   1.1       cgd 	 * interrupt enable: set bit to mask (disable) interrupt.
    313   1.1       cgd 	 */
    314   1.1       cgd 	if (enabled)
    315   1.1       cgd 		ocw1[icu] &= ~(1 << bit);
    316   1.1       cgd 	else
    317   1.1       cgd 		ocw1[icu] |= 1 << bit;
    318   1.1       cgd 
    319   1.1       cgd 	/*
    320   1.1       cgd 	 * interrupt type select: set bit to get level-triggered.
    321   1.1       cgd 	 */
    322   1.3   mycroft 	if (type == IST_LEVEL)
    323   1.1       cgd 		elcr[icu] |= 1 << bit;
    324   1.1       cgd 	else
    325   1.1       cgd 		elcr[icu] &= ~(1 << bit);
    326   1.1       cgd 
    327   1.1       cgd #ifdef not_here
    328   1.1       cgd 	/* see the init function... */
    329   1.1       cgd 	ocw1[0] &= ~0x04;		/* always enable IRQ2 on first PIC */
    330   1.1       cgd 	elcr[0] &= ~0x07;		/* IRQ[0-2] must be edge-triggered */
    331   1.1       cgd 	elcr[1] &= ~0x21;		/* IRQ[13,8] must be edge-triggered */
    332   1.1       cgd #endif
    333   1.1       cgd 
    334  1.14       cgd 	bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
    335  1.14       cgd 	bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
    336  1.20   thorpej 	(*sio_write_elcr)(0, elcr[0]);				/* XXX */
    337  1.20   thorpej 	(*sio_write_elcr)(1, elcr[1]);				/* XXX */
    338   1.1       cgd }
    339   1.1       cgd 
    340   1.1       cgd void
    341  1.20   thorpej sio_intr_setup(pc, iot)
    342  1.20   thorpej 	pci_chipset_tag_t pc;
    343  1.14       cgd 	bus_space_tag_t iot;
    344   1.1       cgd {
    345  1.27   thorpej 	char *cp;
    346   1.1       cgd 	int i;
    347   1.1       cgd 
    348  1.14       cgd 	sio_iot = iot;
    349  1.20   thorpej 	sio_pc = pc;
    350   1.4       cgd 
    351  1.28   thorpej 	if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
    352  1.28   thorpej 	    bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
    353  1.20   thorpej 		panic("sio_intr_setup: can't map ICU I/O ports");
    354  1.20   thorpej 
    355  1.20   thorpej 	for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++)
    356  1.20   thorpej 		if ((*sio_elcr_setup_funcs[i])() == 0)
    357  1.20   thorpej 			break;
    358  1.20   thorpej 	if (sio_elcr_setup_funcs[i] == NULL)
    359  1.20   thorpej 		panic("sio_intr_setup: can't map ELCR");
    360   1.2       cgd 
    361   1.1       cgd #ifdef BROKEN_PROM_CONSOLE
    362   1.1       cgd 	/*
    363  1.25   mycroft 	 * Remember the initial values, so we can restore them later.
    364   1.1       cgd 	 */
    365  1.14       cgd 	initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
    366  1.14       cgd 	initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
    367  1.20   thorpej 	initial_elcr[0] = (*sio_read_elcr)(0);			/* XXX */
    368  1.20   thorpej 	initial_elcr[1] = (*sio_read_elcr)(1);			/* XXX */
    369  1.25   mycroft 	shutdownhook_establish(sio_intr_shutdown, 0);
    370   1.1       cgd #endif
    371   1.1       cgd 
    372  1.27   thorpej 	sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8);
    373  1.16       cgd 
    374   1.1       cgd 	/*
    375   1.1       cgd 	 * set up initial values for interrupt enables.
    376   1.1       cgd 	 */
    377   1.1       cgd 	for (i = 0; i < ICU_LEN; i++) {
    378  1.16       cgd 		alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
    379  1.16       cgd 
    380  1.27   thorpej 		cp = alpha_shared_intr_string(sio_intr, i);
    381  1.27   thorpej 		sprintf(cp, "irq %d", i);
    382  1.27   thorpej 		evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i),
    383  1.27   thorpej 		    EVCNT_TYPE_INTR, NULL, "isa", cp);
    384  1.27   thorpej 
    385   1.1       cgd 		switch (i) {
    386   1.1       cgd 		case 0:
    387   1.1       cgd 		case 1:
    388   1.1       cgd 		case 8:
    389   1.1       cgd 		case 13:
    390   1.1       cgd 			/*
    391   1.1       cgd 			 * IRQs 0, 1, 8, and 13 must always be
    392   1.1       cgd 			 * edge-triggered.
    393   1.1       cgd 			 */
    394  1.29   thorpej 			if (INITIALLY_LEVEL_TRIGGERED(i))
    395  1.29   thorpej 				printf("sio_intr_setup: %d level-triggered\n",
    396  1.29   thorpej 				    i);
    397  1.29   thorpej 			sio_setirqstat(i, INITIALLY_ENABLED(i), IST_EDGE);
    398  1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    399  1.16       cgd 			    IST_EDGE);
    400  1.24      ross 			specific_eoi(i);
    401   1.1       cgd 			break;
    402   1.1       cgd 
    403   1.1       cgd 		case 2:
    404   1.1       cgd 			/*
    405   1.1       cgd 			 * IRQ 2 must be edge-triggered, and should be
    406   1.1       cgd 			 * enabled (otherwise IRQs 8-15 are ignored).
    407   1.1       cgd 			 */
    408   1.3   mycroft 			sio_setirqstat(i, 1, IST_EDGE);
    409  1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    410  1.16       cgd 			    IST_UNUSABLE);
    411   1.1       cgd 			break;
    412   1.1       cgd 
    413   1.1       cgd 		default:
    414   1.1       cgd 			/*
    415   1.1       cgd 			 * Otherwise, disable the IRQ and set its
    416   1.1       cgd 			 * type to (effectively) "unknown."
    417   1.1       cgd 			 */
    418  1.29   thorpej 			sio_setirqstat(i, INITIALLY_ENABLED(i),
    419  1.29   thorpej 			    INITIALLY_LEVEL_TRIGGERED(i) ?
    420  1.29   thorpej 			    IST_LEVEL : IST_NONE);
    421  1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    422  1.29   thorpej 			    INITIALLY_LEVEL_TRIGGERED(i) ?
    423  1.29   thorpej 			    IST_LEVEL : IST_NONE);
    424  1.24      ross 			specific_eoi(i);
    425   1.1       cgd 			break;
    426   1.1       cgd 		}
    427   1.1       cgd 	}
    428   1.1       cgd }
    429   1.1       cgd 
    430  1.25   mycroft #ifdef BROKEN_PROM_CONSOLE
    431  1.25   mycroft void
    432  1.25   mycroft sio_intr_shutdown(arg)
    433  1.25   mycroft 	void *arg;
    434  1.25   mycroft {
    435  1.25   mycroft 	/*
    436  1.25   mycroft 	 * Restore the initial values, to make the PROM happy.
    437  1.25   mycroft 	 */
    438  1.25   mycroft 	bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]);
    439  1.25   mycroft 	bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]);
    440  1.25   mycroft 	(*sio_write_elcr)(0, initial_elcr[0]);			/* XXX */
    441  1.25   mycroft 	(*sio_write_elcr)(1, initial_elcr[1]);			/* XXX */
    442  1.25   mycroft }
    443  1.25   mycroft #endif
    444  1.25   mycroft 
    445   1.4       cgd const char *
    446   1.4       cgd sio_intr_string(v, irq)
    447   1.4       cgd 	void *v;
    448   1.4       cgd 	int irq;
    449   1.4       cgd {
    450   1.7       cgd 	static char irqstr[12];		/* 8 + 2 + NULL + sanity */
    451   1.4       cgd 
    452   1.4       cgd 	if (irq == 0 || irq >= ICU_LEN || irq == 2)
    453  1.16       cgd 		panic("sio_intr_string: bogus isa irq 0x%x\n", irq);
    454   1.4       cgd 
    455  1.13  christos 	sprintf(irqstr, "isa irq %d", irq);
    456   1.4       cgd 	return (irqstr);
    457  1.26       cgd }
    458  1.26       cgd 
    459  1.26       cgd const struct evcnt *
    460  1.26       cgd sio_intr_evcnt(v, irq)
    461  1.26       cgd 	void *v;
    462  1.26       cgd 	int irq;
    463  1.26       cgd {
    464  1.26       cgd 
    465  1.27   thorpej 	if (irq == 0 || irq >= ICU_LEN || irq == 2)
    466  1.27   thorpej 		panic("sio_intr_evcnt: bogus isa irq 0x%x\n", irq);
    467  1.27   thorpej 
    468  1.27   thorpej 	return (alpha_shared_intr_evcnt(sio_intr, irq));
    469   1.4       cgd }
    470   1.4       cgd 
    471   1.1       cgd void *
    472  1.16       cgd sio_intr_establish(v, irq, type, level, fn, arg)
    473  1.16       cgd 	void *v, *arg;
    474   1.4       cgd         int irq;
    475   1.3   mycroft         int type;
    476   1.3   mycroft         int level;
    477  1.16       cgd         int (*fn)(void *);
    478   1.1       cgd {
    479  1.16       cgd 	void *cookie;
    480   1.1       cgd 
    481   1.3   mycroft 	if (irq > ICU_LEN || type == IST_NONE)
    482   1.1       cgd 		panic("sio_intr_establish: bogus irq or type");
    483   1.1       cgd 
    484  1.16       cgd 	cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn,
    485  1.16       cgd 	    arg, "isa irq");
    486   1.1       cgd 
    487  1.30   thorpej 	if (cookie != NULL &&
    488  1.30   thorpej 	    alpha_shared_intr_firstactive(sio_intr, irq)) {
    489  1.30   thorpej 		scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL);
    490  1.30   thorpej 		sio_setirqstat(irq, 1,
    491  1.16       cgd 		    alpha_shared_intr_get_sharetype(sio_intr, irq));
    492  1.30   thorpej 	}
    493   1.1       cgd 
    494  1.16       cgd 	return (cookie);
    495   1.1       cgd }
    496   1.1       cgd 
    497   1.1       cgd void
    498   1.4       cgd sio_intr_disestablish(v, cookie)
    499   1.4       cgd 	void *v;
    500   1.4       cgd 	void *cookie;
    501   1.1       cgd {
    502  1.22   thorpej 	struct alpha_shared_intrhand *ih = cookie;
    503  1.23   thorpej 	int s, ist, irq = ih->ih_num;
    504   1.1       cgd 
    505  1.22   thorpej 	s = splhigh();
    506   1.1       cgd 
    507  1.22   thorpej 	/* Remove it from the link. */
    508  1.22   thorpej 	alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq");
    509  1.22   thorpej 
    510  1.22   thorpej 	/*
    511  1.22   thorpej 	 * Decide if we should disable the interrupt.  We must ensure
    512  1.22   thorpej 	 * that:
    513  1.22   thorpej 	 *
    514  1.22   thorpej 	 *	- An initially-enabled interrupt is never disabled.
    515  1.22   thorpej 	 *	- An initially-LT interrupt is never untyped.
    516  1.22   thorpej 	 */
    517  1.22   thorpej 	if (alpha_shared_intr_isactive(sio_intr, irq) == 0) {
    518  1.23   thorpej 		/*
    519  1.23   thorpej 		 * IRQs 0, 1, 8, and 13 must always be edge-triggered
    520  1.23   thorpej 		 * (see setup).
    521  1.23   thorpej 		 */
    522  1.23   thorpej 		switch (irq) {
    523  1.23   thorpej 		case 0:
    524  1.23   thorpej 		case 1:
    525  1.23   thorpej 		case 8:
    526  1.23   thorpej 		case 13:
    527  1.23   thorpej 			/*
    528  1.23   thorpej 			 * If the interrupt was initially level-triggered
    529  1.23   thorpej 			 * a warning was printed in setup.
    530  1.23   thorpej 			 */
    531  1.23   thorpej 			ist = IST_EDGE;
    532  1.23   thorpej 			break;
    533  1.23   thorpej 
    534  1.23   thorpej 		default:
    535  1.29   thorpej 			ist = INITIALLY_LEVEL_TRIGGERED(irq) ?
    536  1.29   thorpej 			    IST_LEVEL : IST_NONE;
    537  1.23   thorpej 			break;
    538  1.23   thorpej 		}
    539  1.29   thorpej 		sio_setirqstat(irq, INITIALLY_ENABLED(irq), ist);
    540  1.22   thorpej 		alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist);
    541  1.30   thorpej 
    542  1.30   thorpej 		/* Release our SCB vector. */
    543  1.30   thorpej 		scb_free(0x800 + SCB_IDXTOVEC(irq));
    544  1.22   thorpej 	}
    545  1.22   thorpej 
    546  1.22   thorpej 	splx(s);
    547   1.1       cgd }
    548   1.1       cgd 
    549   1.1       cgd void
    550  1.30   thorpej sio_iointr(arg, vec)
    551  1.30   thorpej 	void *arg;
    552  1.10       cgd 	unsigned long vec;
    553   1.1       cgd {
    554  1.16       cgd 	int irq;
    555   1.1       cgd 
    556  1.30   thorpej 	irq = SCB_VECTOIDX(vec - 0x800);
    557  1.30   thorpej 
    558   1.1       cgd #ifdef DIAGNOSTIC
    559   1.1       cgd 	if (irq > ICU_LEN || irq < 0)
    560   1.1       cgd 		panic("sio_iointr: irq out of range (%d)", irq);
    561   1.2       cgd #endif
    562   1.2       cgd 
    563  1.16       cgd 	if (!alpha_shared_intr_dispatch(sio_intr, irq))
    564  1.16       cgd 		alpha_shared_intr_stray(sio_intr, irq, "isa irq");
    565   1.1       cgd 
    566   1.1       cgd 	/*
    567   1.1       cgd 	 * Some versions of the machines which use the SIO
    568   1.1       cgd 	 * (or is it some PALcode revisions on those machines?)
    569   1.1       cgd 	 * require the non-specific EOI to be fed to the PIC(s)
    570   1.1       cgd 	 * by the interrupt handler.
    571   1.1       cgd 	 */
    572  1.24      ross 	specific_eoi(irq);
    573  1.21      matt }
    574  1.21      matt 
    575  1.21      matt #define	LEGAL_IRQ(x)	((x) >= 0 && (x) < ICU_LEN && (x) != 2)
    576  1.21      matt 
    577  1.21      matt int
    578  1.21      matt sio_intr_alloc(v, mask, type, irq)
    579  1.21      matt 	void *v;
    580  1.21      matt 	int mask;
    581  1.21      matt 	int type;
    582  1.21      matt 	int *irq;
    583  1.21      matt {
    584  1.21      matt 	int i, tmp, bestirq, count;
    585  1.21      matt 	struct alpha_shared_intrhand **p, *q;
    586  1.21      matt 
    587  1.21      matt 	if (type == IST_NONE)
    588  1.21      matt 		panic("intr_alloc: bogus type");
    589  1.21      matt 
    590  1.21      matt 	bestirq = -1;
    591  1.21      matt 	count = -1;
    592  1.21      matt 
    593  1.21      matt 	/* some interrupts should never be dynamically allocated */
    594  1.21      matt 	mask &= 0xdef8;
    595  1.21      matt 
    596  1.21      matt 	/*
    597  1.21      matt 	 * XXX some interrupts will be used later (6 for fdc, 12 for pms).
    598  1.21      matt 	 * the right answer is to do "breadth-first" searching of devices.
    599  1.21      matt 	 */
    600  1.21      matt 	mask &= 0xefbf;
    601  1.21      matt 
    602  1.21      matt 	for (i = 0; i < ICU_LEN; i++) {
    603  1.21      matt 		if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
    604  1.21      matt 			continue;
    605  1.21      matt 
    606  1.21      matt 		switch(sio_intr[i].intr_sharetype) {
    607  1.21      matt 		case IST_NONE:
    608  1.21      matt 			/*
    609  1.21      matt 			 * if nothing's using the irq, just return it
    610  1.21      matt 			 */
    611  1.21      matt 			*irq = i;
    612  1.21      matt 			return (0);
    613  1.21      matt 
    614  1.21      matt 		case IST_EDGE:
    615  1.21      matt 		case IST_LEVEL:
    616  1.21      matt 			if (type != sio_intr[i].intr_sharetype)
    617  1.21      matt 				continue;
    618  1.21      matt 			/*
    619  1.21      matt 			 * if the irq is shareable, count the number of other
    620  1.21      matt 			 * handlers, and if it's smaller than the last irq like
    621  1.21      matt 			 * this, remember it
    622  1.21      matt 			 *
    623  1.21      matt 			 * XXX We should probably also consider the
    624  1.21      matt 			 * interrupt level and stick IPL_TTY with other
    625  1.21      matt 			 * IPL_TTY, etc.
    626  1.21      matt 			 */
    627  1.21      matt 			for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0;
    628  1.21      matt 			     (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++)
    629  1.21      matt 				;
    630  1.21      matt 			if ((bestirq == -1) || (count > tmp)) {
    631  1.21      matt 				bestirq = i;
    632  1.21      matt 				count = tmp;
    633  1.21      matt 			}
    634  1.21      matt 			break;
    635  1.21      matt 
    636  1.21      matt 		case IST_PULSE:
    637  1.21      matt 			/* this just isn't shareable */
    638  1.21      matt 			continue;
    639  1.21      matt 		}
    640  1.21      matt 	}
    641  1.21      matt 
    642  1.21      matt 	if (bestirq == -1)
    643  1.21      matt 		return (1);
    644  1.21      matt 
    645  1.21      matt 	*irq = bestirq;
    646  1.21      matt 
    647  1.21      matt 	return (0);
    648  1.24      ross }
    649  1.24      ross 
    650  1.24      ross static void
    651  1.24      ross specific_eoi(irq)
    652  1.24      ross 	int irq;
    653  1.24      ross {
    654  1.24      ross 	if (irq > 7)
    655  1.24      ross 		bus_space_write_1(sio_iot,
    656  1.24      ross 		    sio_ioh_icu2, 0, 0x20 | (irq & 0x07));	/* XXX */
    657  1.24      ross 	bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq));
    658   1.1       cgd }
    659