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sio_pic.c revision 1.42.10.1
      1  1.42.10.1     rmind /* $NetBSD: sio_pic.c,v 1.42.10.1 2014/05/18 17:44:53 rmind Exp $ */
      2       1.20   thorpej 
      3       1.20   thorpej /*-
      4       1.28   thorpej  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
      5       1.20   thorpej  * All rights reserved.
      6       1.20   thorpej  *
      7       1.20   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8       1.20   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9       1.20   thorpej  * NASA Ames Research Center.
     10       1.20   thorpej  *
     11       1.20   thorpej  * Redistribution and use in source and binary forms, with or without
     12       1.20   thorpej  * modification, are permitted provided that the following conditions
     13       1.20   thorpej  * are met:
     14       1.20   thorpej  * 1. Redistributions of source code must retain the above copyright
     15       1.20   thorpej  *    notice, this list of conditions and the following disclaimer.
     16       1.20   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17       1.20   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18       1.20   thorpej  *    documentation and/or other materials provided with the distribution.
     19       1.20   thorpej  *
     20       1.20   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21       1.20   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22       1.20   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23       1.20   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24       1.20   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25       1.20   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26       1.20   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27       1.20   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28       1.20   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29       1.20   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30       1.20   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     31       1.20   thorpej  */
     32        1.1       cgd 
     33        1.1       cgd /*
     34        1.6       cgd  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
     35        1.1       cgd  * All rights reserved.
     36        1.1       cgd  *
     37        1.1       cgd  * Author: Chris G. Demetriou
     38       1.42      matt  *
     39        1.1       cgd  * Permission to use, copy, modify and distribute this software and
     40        1.1       cgd  * its documentation is hereby granted, provided that both the copyright
     41        1.1       cgd  * notice and this permission notice appear in all copies of the
     42        1.1       cgd  * software, derivative works or modified versions, and any portions
     43        1.1       cgd  * thereof, and that both notices appear in supporting documentation.
     44       1.42      matt  *
     45       1.42      matt  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     46       1.42      matt  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     47        1.1       cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     48       1.42      matt  *
     49        1.1       cgd  * Carnegie Mellon requests users of this software to return to
     50        1.1       cgd  *
     51        1.1       cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     52        1.1       cgd  *  School of Computer Science
     53        1.1       cgd  *  Carnegie Mellon University
     54        1.1       cgd  *  Pittsburgh PA 15213-3890
     55        1.1       cgd  *
     56        1.1       cgd  * any improvements or extensions that they make and grant Carnegie the
     57        1.1       cgd  * rights to redistribute these changes.
     58        1.1       cgd  */
     59       1.17       cgd 
     60       1.18       cgd #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     61       1.18       cgd 
     62  1.42.10.1     rmind __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.42.10.1 2014/05/18 17:44:53 rmind Exp $");
     63        1.1       cgd 
     64        1.1       cgd #include <sys/param.h>
     65        1.1       cgd #include <sys/systm.h>
     66        1.1       cgd #include <sys/device.h>
     67        1.1       cgd #include <sys/malloc.h>
     68        1.1       cgd #include <sys/syslog.h>
     69        1.1       cgd 
     70        1.4       cgd #include <machine/intr.h>
     71       1.41    dyoung #include <sys/bus.h>
     72        1.4       cgd 
     73       1.20   thorpej #include <dev/pci/pcireg.h>
     74       1.20   thorpej #include <dev/pci/pcivar.h>
     75       1.20   thorpej #include <dev/pci/pcidevs.h>
     76       1.20   thorpej 
     77       1.28   thorpej #include <dev/pci/cy82c693reg.h>
     78       1.28   thorpej #include <dev/pci/cy82c693var.h>
     79       1.28   thorpej 
     80        1.2       cgd #include <dev/isa/isareg.h>
     81        1.1       cgd #include <dev/isa/isavar.h>
     82        1.2       cgd #include <alpha/pci/siovar.h>
     83        1.2       cgd 
     84        1.2       cgd #include "sio.h"
     85        1.1       cgd 
     86        1.1       cgd /*
     87        1.1       cgd  * To add to the long history of wonderful PROM console traits,
     88        1.1       cgd  * AlphaStation PROMs don't reset themselves completely on boot!
     89        1.1       cgd  * Therefore, if an interrupt was turned on when the kernel was
     90        1.1       cgd  * started, we're not going to EVER turn it off...  I don't know
     91        1.1       cgd  * what will happen if new interrupts (that the PROM console doesn't
     92        1.1       cgd  * want) are turned on.  I'll burn that bridge when I come to it.
     93        1.1       cgd  */
     94        1.1       cgd #define	BROKEN_PROM_CONSOLE
     95        1.1       cgd 
     96        1.2       cgd /*
     97        1.2       cgd  * Private functions and variables.
     98        1.2       cgd  */
     99        1.4       cgd 
    100       1.14       cgd bus_space_tag_t sio_iot;
    101       1.20   thorpej pci_chipset_tag_t sio_pc;
    102       1.28   thorpej bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2;
    103        1.1       cgd 
    104        1.1       cgd #define	ICU_LEN		16		/* number of ISA IRQs */
    105        1.1       cgd 
    106       1.16       cgd static struct alpha_shared_intr *sio_intr;
    107        1.1       cgd 
    108        1.1       cgd #ifndef STRAY_MAX
    109        1.1       cgd #define	STRAY_MAX	5
    110        1.1       cgd #endif
    111        1.1       cgd 
    112        1.1       cgd #ifdef BROKEN_PROM_CONSOLE
    113        1.1       cgd /*
    114        1.1       cgd  * If prom console is broken, must remember the initial interrupt
    115        1.1       cgd  * settings and enforce them.  WHEE!
    116        1.1       cgd  */
    117       1.42      matt uint8_t initial_ocw1[2];
    118       1.42      matt uint8_t initial_elcr[2];
    119        1.1       cgd #endif
    120        1.1       cgd 
    121       1.37       dsl void		sio_setirqstat(int, int, int);
    122       1.20   thorpej 
    123       1.42      matt uint8_t	(*sio_read_elcr)(int);
    124       1.42      matt void		(*sio_write_elcr)(int, uint8_t);
    125       1.37       dsl static void	specific_eoi(int);
    126       1.25   mycroft #ifdef BROKEN_PROM_CONSOLE
    127       1.37       dsl void		sio_intr_shutdown(void *);
    128       1.25   mycroft #endif
    129       1.20   thorpej 
    130       1.20   thorpej /******************** i82378 SIO ELCR functions ********************/
    131       1.20   thorpej 
    132       1.37       dsl int		i82378_setup_elcr(void);
    133       1.42      matt uint8_t	i82378_read_elcr(int);
    134       1.42      matt void		i82378_write_elcr(int, uint8_t);
    135       1.20   thorpej 
    136       1.28   thorpej bus_space_handle_t sio_ioh_elcr;
    137       1.28   thorpej 
    138       1.20   thorpej int
    139       1.42      matt i82378_setup_elcr(void)
    140       1.20   thorpej {
    141       1.20   thorpej 	int rv;
    142       1.20   thorpej 
    143       1.20   thorpej 	/*
    144       1.20   thorpej 	 * We could probe configuration space to see that there's
    145       1.20   thorpej 	 * actually an SIO present, but we are using this as a
    146       1.20   thorpej 	 * fall-back in case nothing else matches.
    147       1.20   thorpej 	 */
    148       1.20   thorpej 
    149       1.20   thorpej 	rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr);
    150       1.20   thorpej 
    151       1.20   thorpej 	if (rv == 0) {
    152       1.20   thorpej 		sio_read_elcr = i82378_read_elcr;
    153       1.20   thorpej 		sio_write_elcr = i82378_write_elcr;
    154       1.20   thorpej 	}
    155       1.20   thorpej 
    156       1.20   thorpej 	return (rv);
    157       1.20   thorpej }
    158       1.20   thorpej 
    159       1.42      matt uint8_t
    160       1.38       dsl i82378_read_elcr(int elcr)
    161       1.20   thorpej {
    162       1.20   thorpej 
    163       1.20   thorpej 	return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr));
    164       1.20   thorpej }
    165       1.20   thorpej 
    166       1.20   thorpej void
    167       1.42      matt i82378_write_elcr(int elcr, uint8_t val)
    168       1.20   thorpej {
    169       1.20   thorpej 
    170       1.20   thorpej 	bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val);
    171       1.20   thorpej }
    172       1.20   thorpej 
    173       1.20   thorpej /******************** Cypress CY82C693 ELCR functions ********************/
    174       1.20   thorpej 
    175       1.37       dsl int		cy82c693_setup_elcr(void);
    176       1.42      matt uint8_t	cy82c693_read_elcr(int);
    177       1.42      matt void		cy82c693_write_elcr(int, uint8_t);
    178       1.20   thorpej 
    179       1.28   thorpej const struct cy82c693_handle *sio_cy82c693_handle;
    180       1.28   thorpej 
    181       1.20   thorpej int
    182       1.42      matt cy82c693_setup_elcr(void)
    183       1.20   thorpej {
    184       1.20   thorpej 	int device, maxndevs;
    185       1.20   thorpej 	pcitag_t tag;
    186       1.20   thorpej 	pcireg_t id;
    187       1.20   thorpej 
    188       1.20   thorpej 	/*
    189       1.20   thorpej 	 * Search PCI configuration space for a Cypress CY82C693.
    190       1.20   thorpej 	 *
    191       1.20   thorpej 	 * Note we can make some assumptions about our bus number
    192       1.20   thorpej 	 * here, because:
    193       1.20   thorpej 	 *
    194       1.20   thorpej 	 *	(1) there can be at most one ISA/EISA bridge per PCI bus, and
    195       1.20   thorpej 	 *
    196       1.20   thorpej 	 *	(2) any ISA/EISA bridges must be attached to primary PCI
    197       1.20   thorpej 	 *	    busses (i.e. bus zero).
    198       1.20   thorpej 	 */
    199       1.20   thorpej 
    200       1.20   thorpej 	maxndevs = pci_bus_maxdevs(sio_pc, 0);
    201       1.20   thorpej 
    202       1.20   thorpej 	for (device = 0; device < maxndevs; device++) {
    203       1.20   thorpej 		tag = pci_make_tag(sio_pc, 0, device, 0);
    204       1.20   thorpej 		id = pci_conf_read(sio_pc, tag, PCI_ID_REG);
    205       1.20   thorpej 
    206       1.20   thorpej 		/* Invalid vendor ID value? */
    207       1.20   thorpej 		if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    208       1.20   thorpej 			continue;
    209       1.20   thorpej 		/* XXX Not invalid, but we've done this ~forever. */
    210       1.20   thorpej 		if (PCI_VENDOR(id) == 0)
    211       1.20   thorpej 			continue;
    212       1.20   thorpej 
    213       1.20   thorpej 		if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ ||
    214       1.20   thorpej 		    PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693)
    215       1.20   thorpej 			continue;
    216       1.20   thorpej 
    217       1.20   thorpej 		/*
    218       1.20   thorpej 		 * Found one!
    219       1.20   thorpej 		 */
    220       1.20   thorpej 
    221       1.20   thorpej #if 0
    222       1.20   thorpej 		printf("cy82c693_setup_elcr: found 82C693 at device %d\n",
    223       1.20   thorpej 		    device);
    224       1.20   thorpej #endif
    225       1.20   thorpej 
    226       1.28   thorpej 		sio_cy82c693_handle = cy82c693_init(sio_iot);
    227       1.20   thorpej 		sio_read_elcr = cy82c693_read_elcr;
    228       1.20   thorpej 		sio_write_elcr = cy82c693_write_elcr;
    229       1.20   thorpej 
    230       1.20   thorpej 		return (0);
    231       1.20   thorpej 	}
    232       1.20   thorpej 
    233       1.20   thorpej 	/*
    234       1.20   thorpej 	 * Didn't find a CY82C693.
    235       1.20   thorpej 	 */
    236       1.20   thorpej 	return (ENODEV);
    237       1.20   thorpej }
    238       1.20   thorpej 
    239       1.42      matt uint8_t
    240       1.38       dsl cy82c693_read_elcr(int elcr)
    241       1.20   thorpej {
    242       1.20   thorpej 
    243       1.28   thorpej 	return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr));
    244       1.20   thorpej }
    245       1.20   thorpej 
    246       1.20   thorpej void
    247       1.42      matt cy82c693_write_elcr(int elcr, uint8_t val)
    248       1.20   thorpej {
    249       1.20   thorpej 
    250       1.28   thorpej 	cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val);
    251       1.20   thorpej }
    252       1.20   thorpej 
    253       1.20   thorpej /******************** ELCR access function configuration ********************/
    254       1.20   thorpej 
    255       1.20   thorpej /*
    256       1.20   thorpej  * Put the Intel SIO at the end, so we fall back on it if we don't
    257       1.20   thorpej  * find anything else.  If any of the non-Intel functions find a
    258       1.20   thorpej  * matching device, but are unable to map it for whatever reason,
    259       1.20   thorpej  * they should panic.
    260       1.20   thorpej  */
    261       1.20   thorpej 
    262       1.42      matt int (*const sio_elcr_setup_funcs[])(void) = {
    263       1.20   thorpej 	cy82c693_setup_elcr,
    264       1.20   thorpej 	i82378_setup_elcr,
    265       1.20   thorpej 	NULL,
    266       1.20   thorpej };
    267       1.20   thorpej 
    268       1.20   thorpej /******************** Shared SIO/Cypress functions ********************/
    269       1.15       cgd 
    270        1.1       cgd void
    271       1.39       dsl sio_setirqstat(int irq, int enabled, int type)
    272        1.1       cgd {
    273       1.42      matt 	uint8_t ocw1[2], elcr[2];
    274        1.1       cgd 	int icu, bit;
    275        1.1       cgd 
    276        1.1       cgd #if 0
    277       1.13  christos 	printf("sio_setirqstat: irq %d: %s, %s\n", irq,
    278        1.1       cgd 	    enabled ? "enabled" : "disabled", isa_intr_typename(type));
    279        1.1       cgd #endif
    280        1.1       cgd 
    281        1.1       cgd 	icu = irq / 8;
    282        1.1       cgd 	bit = irq % 8;
    283        1.1       cgd 
    284       1.14       cgd 	ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
    285       1.14       cgd 	ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
    286       1.20   thorpej 	elcr[0] = (*sio_read_elcr)(0);				/* XXX */
    287       1.20   thorpej 	elcr[1] = (*sio_read_elcr)(1);				/* XXX */
    288        1.1       cgd 
    289        1.1       cgd 	/*
    290        1.1       cgd 	 * interrupt enable: set bit to mask (disable) interrupt.
    291        1.1       cgd 	 */
    292        1.1       cgd 	if (enabled)
    293        1.1       cgd 		ocw1[icu] &= ~(1 << bit);
    294        1.1       cgd 	else
    295        1.1       cgd 		ocw1[icu] |= 1 << bit;
    296        1.1       cgd 
    297        1.1       cgd 	/*
    298        1.1       cgd 	 * interrupt type select: set bit to get level-triggered.
    299        1.1       cgd 	 */
    300        1.3   mycroft 	if (type == IST_LEVEL)
    301        1.1       cgd 		elcr[icu] |= 1 << bit;
    302        1.1       cgd 	else
    303        1.1       cgd 		elcr[icu] &= ~(1 << bit);
    304        1.1       cgd 
    305        1.1       cgd #ifdef not_here
    306        1.1       cgd 	/* see the init function... */
    307        1.1       cgd 	ocw1[0] &= ~0x04;		/* always enable IRQ2 on first PIC */
    308        1.1       cgd 	elcr[0] &= ~0x07;		/* IRQ[0-2] must be edge-triggered */
    309        1.1       cgd 	elcr[1] &= ~0x21;		/* IRQ[13,8] must be edge-triggered */
    310        1.1       cgd #endif
    311        1.1       cgd 
    312       1.14       cgd 	bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
    313       1.14       cgd 	bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
    314       1.20   thorpej 	(*sio_write_elcr)(0, elcr[0]);				/* XXX */
    315       1.20   thorpej 	(*sio_write_elcr)(1, elcr[1]);				/* XXX */
    316        1.1       cgd }
    317        1.1       cgd 
    318        1.1       cgd void
    319       1.38       dsl sio_intr_setup(pci_chipset_tag_t pc, bus_space_tag_t iot)
    320        1.1       cgd {
    321       1.27   thorpej 	char *cp;
    322        1.1       cgd 	int i;
    323        1.1       cgd 
    324       1.14       cgd 	sio_iot = iot;
    325       1.20   thorpej 	sio_pc = pc;
    326        1.4       cgd 
    327       1.28   thorpej 	if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
    328       1.28   thorpej 	    bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
    329       1.20   thorpej 		panic("sio_intr_setup: can't map ICU I/O ports");
    330       1.20   thorpej 
    331       1.20   thorpej 	for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++)
    332       1.20   thorpej 		if ((*sio_elcr_setup_funcs[i])() == 0)
    333       1.20   thorpej 			break;
    334       1.20   thorpej 	if (sio_elcr_setup_funcs[i] == NULL)
    335       1.20   thorpej 		panic("sio_intr_setup: can't map ELCR");
    336        1.2       cgd 
    337        1.1       cgd #ifdef BROKEN_PROM_CONSOLE
    338        1.1       cgd 	/*
    339       1.25   mycroft 	 * Remember the initial values, so we can restore them later.
    340        1.1       cgd 	 */
    341       1.14       cgd 	initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
    342       1.14       cgd 	initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
    343       1.20   thorpej 	initial_elcr[0] = (*sio_read_elcr)(0);			/* XXX */
    344       1.20   thorpej 	initial_elcr[1] = (*sio_read_elcr)(1);			/* XXX */
    345       1.25   mycroft 	shutdownhook_establish(sio_intr_shutdown, 0);
    346        1.1       cgd #endif
    347        1.1       cgd 
    348  1.42.10.1     rmind #define PCI_SIO_IRQ_STR	8
    349  1.42.10.1     rmind 	sio_intr = alpha_shared_intr_alloc(ICU_LEN, PCI_SIO_IRQ_STR);
    350       1.16       cgd 
    351        1.1       cgd 	/*
    352        1.1       cgd 	 * set up initial values for interrupt enables.
    353        1.1       cgd 	 */
    354        1.1       cgd 	for (i = 0; i < ICU_LEN; i++) {
    355       1.16       cgd 		alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
    356       1.16       cgd 
    357       1.27   thorpej 		cp = alpha_shared_intr_string(sio_intr, i);
    358  1.42.10.1     rmind 		snprintf(cp, PCI_SIO_IRQ_STR, "irq %d", i);
    359       1.27   thorpej 		evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i),
    360       1.27   thorpej 		    EVCNT_TYPE_INTR, NULL, "isa", cp);
    361       1.27   thorpej 
    362        1.1       cgd 		switch (i) {
    363        1.1       cgd 		case 0:
    364        1.1       cgd 		case 1:
    365        1.1       cgd 		case 8:
    366        1.1       cgd 		case 13:
    367        1.1       cgd 			/*
    368        1.1       cgd 			 * IRQs 0, 1, 8, and 13 must always be
    369        1.1       cgd 			 * edge-triggered.
    370        1.1       cgd 			 */
    371       1.32   mycroft 			sio_setirqstat(i, 0, IST_EDGE);
    372       1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    373       1.16       cgd 			    IST_EDGE);
    374       1.24      ross 			specific_eoi(i);
    375        1.1       cgd 			break;
    376        1.1       cgd 
    377        1.1       cgd 		case 2:
    378        1.1       cgd 			/*
    379        1.1       cgd 			 * IRQ 2 must be edge-triggered, and should be
    380        1.1       cgd 			 * enabled (otherwise IRQs 8-15 are ignored).
    381        1.1       cgd 			 */
    382        1.3   mycroft 			sio_setirqstat(i, 1, IST_EDGE);
    383       1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    384       1.16       cgd 			    IST_UNUSABLE);
    385        1.1       cgd 			break;
    386        1.1       cgd 
    387        1.1       cgd 		default:
    388        1.1       cgd 			/*
    389        1.1       cgd 			 * Otherwise, disable the IRQ and set its
    390        1.1       cgd 			 * type to (effectively) "unknown."
    391        1.1       cgd 			 */
    392       1.32   mycroft 			sio_setirqstat(i, 0, IST_NONE);
    393       1.16       cgd 			alpha_shared_intr_set_dfltsharetype(sio_intr, i,
    394       1.32   mycroft 			    IST_NONE);
    395       1.24      ross 			specific_eoi(i);
    396        1.1       cgd 			break;
    397        1.1       cgd 		}
    398        1.1       cgd 	}
    399        1.1       cgd }
    400        1.1       cgd 
    401       1.25   mycroft #ifdef BROKEN_PROM_CONSOLE
    402       1.25   mycroft void
    403       1.38       dsl sio_intr_shutdown(void *arg)
    404       1.25   mycroft {
    405       1.25   mycroft 	/*
    406       1.25   mycroft 	 * Restore the initial values, to make the PROM happy.
    407       1.25   mycroft 	 */
    408       1.25   mycroft 	bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]);
    409       1.25   mycroft 	bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]);
    410       1.25   mycroft 	(*sio_write_elcr)(0, initial_elcr[0]);			/* XXX */
    411       1.25   mycroft 	(*sio_write_elcr)(1, initial_elcr[1]);			/* XXX */
    412       1.25   mycroft }
    413       1.25   mycroft #endif
    414       1.25   mycroft 
    415        1.4       cgd const char *
    416  1.42.10.1     rmind sio_intr_string(void *v, int irq, char *buf, size_t len)
    417        1.4       cgd {
    418        1.4       cgd 	if (irq == 0 || irq >= ICU_LEN || irq == 2)
    419  1.42.10.1     rmind 		panic("%s: bogus isa irq 0x%x", __func__, irq);
    420        1.4       cgd 
    421  1.42.10.1     rmind 	snprintf(buf, len, "isa irq %d", irq);
    422  1.42.10.1     rmind 	return buf;
    423       1.26       cgd }
    424       1.26       cgd 
    425       1.26       cgd const struct evcnt *
    426       1.38       dsl sio_intr_evcnt(void *v, int irq)
    427       1.26       cgd {
    428       1.26       cgd 
    429       1.27   thorpej 	if (irq == 0 || irq >= ICU_LEN || irq == 2)
    430  1.42.10.1     rmind 		panic("%s: bogus isa irq 0x%x", __func__, irq);
    431       1.27   thorpej 
    432       1.27   thorpej 	return (alpha_shared_intr_evcnt(sio_intr, irq));
    433        1.4       cgd }
    434        1.4       cgd 
    435        1.1       cgd void *
    436       1.40       dsl sio_intr_establish(void *v, int irq, int type, int level, int (*fn)(void *), void *arg)
    437        1.1       cgd {
    438       1.16       cgd 	void *cookie;
    439        1.1       cgd 
    440        1.3   mycroft 	if (irq > ICU_LEN || type == IST_NONE)
    441        1.1       cgd 		panic("sio_intr_establish: bogus irq or type");
    442        1.1       cgd 
    443       1.16       cgd 	cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn,
    444       1.16       cgd 	    arg, "isa irq");
    445        1.1       cgd 
    446       1.30   thorpej 	if (cookie != NULL &&
    447       1.30   thorpej 	    alpha_shared_intr_firstactive(sio_intr, irq)) {
    448       1.35        ad 		scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL,
    449       1.35        ad 		    level);
    450       1.30   thorpej 		sio_setirqstat(irq, 1,
    451       1.16       cgd 		    alpha_shared_intr_get_sharetype(sio_intr, irq));
    452       1.30   thorpej 	}
    453        1.1       cgd 
    454       1.16       cgd 	return (cookie);
    455        1.1       cgd }
    456        1.1       cgd 
    457        1.1       cgd void
    458       1.38       dsl sio_intr_disestablish(void *v, void *cookie)
    459        1.1       cgd {
    460       1.22   thorpej 	struct alpha_shared_intrhand *ih = cookie;
    461       1.23   thorpej 	int s, ist, irq = ih->ih_num;
    462        1.1       cgd 
    463       1.22   thorpej 	s = splhigh();
    464        1.1       cgd 
    465       1.22   thorpej 	/* Remove it from the link. */
    466       1.22   thorpej 	alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq");
    467       1.22   thorpej 
    468       1.22   thorpej 	/*
    469       1.22   thorpej 	 * Decide if we should disable the interrupt.  We must ensure
    470       1.22   thorpej 	 * that:
    471       1.22   thorpej 	 *
    472       1.22   thorpej 	 *	- An initially-enabled interrupt is never disabled.
    473       1.22   thorpej 	 *	- An initially-LT interrupt is never untyped.
    474       1.22   thorpej 	 */
    475       1.22   thorpej 	if (alpha_shared_intr_isactive(sio_intr, irq) == 0) {
    476       1.23   thorpej 		/*
    477       1.23   thorpej 		 * IRQs 0, 1, 8, and 13 must always be edge-triggered
    478       1.23   thorpej 		 * (see setup).
    479       1.23   thorpej 		 */
    480       1.23   thorpej 		switch (irq) {
    481       1.23   thorpej 		case 0:
    482       1.23   thorpej 		case 1:
    483       1.23   thorpej 		case 8:
    484       1.23   thorpej 		case 13:
    485       1.23   thorpej 			/*
    486       1.23   thorpej 			 * If the interrupt was initially level-triggered
    487       1.23   thorpej 			 * a warning was printed in setup.
    488       1.23   thorpej 			 */
    489       1.23   thorpej 			ist = IST_EDGE;
    490       1.23   thorpej 			break;
    491       1.23   thorpej 
    492       1.23   thorpej 		default:
    493       1.32   mycroft 			ist = IST_NONE;
    494       1.23   thorpej 			break;
    495       1.23   thorpej 		}
    496       1.32   mycroft 		sio_setirqstat(irq, 0, ist);
    497       1.22   thorpej 		alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist);
    498       1.30   thorpej 
    499       1.30   thorpej 		/* Release our SCB vector. */
    500       1.30   thorpej 		scb_free(0x800 + SCB_IDXTOVEC(irq));
    501       1.22   thorpej 	}
    502       1.22   thorpej 
    503       1.22   thorpej 	splx(s);
    504        1.1       cgd }
    505        1.1       cgd 
    506        1.1       cgd void
    507       1.38       dsl sio_iointr(void *arg, unsigned long vec)
    508        1.1       cgd {
    509       1.16       cgd 	int irq;
    510        1.1       cgd 
    511       1.30   thorpej 	irq = SCB_VECTOIDX(vec - 0x800);
    512       1.30   thorpej 
    513        1.1       cgd #ifdef DIAGNOSTIC
    514        1.1       cgd 	if (irq > ICU_LEN || irq < 0)
    515        1.1       cgd 		panic("sio_iointr: irq out of range (%d)", irq);
    516        1.2       cgd #endif
    517        1.2       cgd 
    518       1.16       cgd 	if (!alpha_shared_intr_dispatch(sio_intr, irq))
    519       1.16       cgd 		alpha_shared_intr_stray(sio_intr, irq, "isa irq");
    520       1.33   thorpej 	else
    521       1.33   thorpej 		alpha_shared_intr_reset_strays(sio_intr, irq);
    522        1.1       cgd 
    523        1.1       cgd 	/*
    524        1.1       cgd 	 * Some versions of the machines which use the SIO
    525        1.1       cgd 	 * (or is it some PALcode revisions on those machines?)
    526        1.1       cgd 	 * require the non-specific EOI to be fed to the PIC(s)
    527        1.1       cgd 	 * by the interrupt handler.
    528        1.1       cgd 	 */
    529       1.24      ross 	specific_eoi(irq);
    530       1.21      matt }
    531       1.21      matt 
    532       1.21      matt #define	LEGAL_IRQ(x)	((x) >= 0 && (x) < ICU_LEN && (x) != 2)
    533       1.21      matt 
    534       1.21      matt int
    535       1.38       dsl sio_intr_alloc(void *v, int mask, int type, int *irq)
    536       1.21      matt {
    537       1.21      matt 	int i, tmp, bestirq, count;
    538       1.21      matt 	struct alpha_shared_intrhand **p, *q;
    539       1.21      matt 
    540       1.21      matt 	if (type == IST_NONE)
    541       1.21      matt 		panic("intr_alloc: bogus type");
    542       1.21      matt 
    543       1.21      matt 	bestirq = -1;
    544       1.21      matt 	count = -1;
    545       1.21      matt 
    546       1.21      matt 	/* some interrupts should never be dynamically allocated */
    547       1.21      matt 	mask &= 0xdef8;
    548       1.21      matt 
    549       1.21      matt 	/*
    550       1.21      matt 	 * XXX some interrupts will be used later (6 for fdc, 12 for pms).
    551       1.21      matt 	 * the right answer is to do "breadth-first" searching of devices.
    552       1.21      matt 	 */
    553       1.21      matt 	mask &= 0xefbf;
    554       1.21      matt 
    555       1.21      matt 	for (i = 0; i < ICU_LEN; i++) {
    556       1.21      matt 		if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
    557       1.21      matt 			continue;
    558       1.21      matt 
    559       1.21      matt 		switch(sio_intr[i].intr_sharetype) {
    560       1.21      matt 		case IST_NONE:
    561       1.21      matt 			/*
    562       1.21      matt 			 * if nothing's using the irq, just return it
    563       1.21      matt 			 */
    564       1.21      matt 			*irq = i;
    565       1.21      matt 			return (0);
    566       1.21      matt 
    567       1.21      matt 		case IST_EDGE:
    568       1.21      matt 		case IST_LEVEL:
    569       1.21      matt 			if (type != sio_intr[i].intr_sharetype)
    570       1.21      matt 				continue;
    571       1.21      matt 			/*
    572       1.21      matt 			 * if the irq is shareable, count the number of other
    573       1.21      matt 			 * handlers, and if it's smaller than the last irq like
    574       1.21      matt 			 * this, remember it
    575       1.21      matt 			 *
    576       1.21      matt 			 * XXX We should probably also consider the
    577       1.21      matt 			 * interrupt level and stick IPL_TTY with other
    578       1.21      matt 			 * IPL_TTY, etc.
    579       1.21      matt 			 */
    580       1.21      matt 			for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0;
    581       1.21      matt 			     (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++)
    582       1.21      matt 				;
    583       1.21      matt 			if ((bestirq == -1) || (count > tmp)) {
    584       1.21      matt 				bestirq = i;
    585       1.21      matt 				count = tmp;
    586       1.21      matt 			}
    587       1.21      matt 			break;
    588       1.21      matt 
    589       1.21      matt 		case IST_PULSE:
    590       1.21      matt 			/* this just isn't shareable */
    591       1.21      matt 			continue;
    592       1.21      matt 		}
    593       1.21      matt 	}
    594       1.21      matt 
    595       1.21      matt 	if (bestirq == -1)
    596       1.21      matt 		return (1);
    597       1.21      matt 
    598       1.21      matt 	*irq = bestirq;
    599       1.21      matt 
    600       1.21      matt 	return (0);
    601       1.24      ross }
    602       1.24      ross 
    603       1.24      ross static void
    604       1.38       dsl specific_eoi(int irq)
    605       1.24      ross {
    606       1.24      ross 	if (irq > 7)
    607       1.24      ross 		bus_space_write_1(sio_iot,
    608       1.32   mycroft 		    sio_ioh_icu2, 0, 0x60 | (irq & 0x07));	/* XXX */
    609       1.32   mycroft 	bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq));
    610        1.1       cgd }
    611