sio_pic.c revision 1.26
1 /* $NetBSD: sio_pic.c,v 1.26 2000/06/04 19:14:26 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.26 2000/06/04 19:14:26 cgd Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 #include <sys/syslog.h> 76 77 #include <machine/intr.h> 78 #include <machine/bus.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/isa/isareg.h> 85 #include <dev/isa/isavar.h> 86 #include <alpha/pci/siovar.h> 87 88 #ifndef EVCNT_COUNTERS 89 #include <machine/intrcnt.h> 90 #endif 91 92 #include "sio.h" 93 94 /* 95 * To add to the long history of wonderful PROM console traits, 96 * AlphaStation PROMs don't reset themselves completely on boot! 97 * Therefore, if an interrupt was turned on when the kernel was 98 * started, we're not going to EVER turn it off... I don't know 99 * what will happen if new interrupts (that the PROM console doesn't 100 * want) are turned on. I'll burn that bridge when I come to it. 101 */ 102 #define BROKEN_PROM_CONSOLE 103 104 /* 105 * Private functions and variables. 106 */ 107 108 bus_space_tag_t sio_iot; 109 pci_chipset_tag_t sio_pc; 110 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2, sio_ioh_elcr; 111 112 #define ICU_LEN 16 /* number of ISA IRQs */ 113 114 static struct alpha_shared_intr *sio_intr; 115 #ifdef EVCNT_COUNTERS 116 struct evcnt sio_intr_evcnt; 117 #endif 118 119 #ifndef STRAY_MAX 120 #define STRAY_MAX 5 121 #endif 122 123 #ifdef BROKEN_PROM_CONSOLE 124 /* 125 * If prom console is broken, must remember the initial interrupt 126 * settings and enforce them. WHEE! 127 */ 128 u_int8_t initial_ocw1[2]; 129 u_int8_t initial_elcr[2]; 130 #endif 131 132 void sio_setirqstat __P((int, int, int)); 133 134 u_int8_t (*sio_read_elcr) __P((int)); 135 void (*sio_write_elcr) __P((int, u_int8_t)); 136 static void specific_eoi __P((int)); 137 #ifdef BROKEN_PROM_CONSOLE 138 void sio_intr_shutdown __P((void *)); 139 #endif 140 141 /******************** i82378 SIO ELCR functions ********************/ 142 143 int i82378_setup_elcr __P((void)); 144 u_int8_t i82378_read_elcr __P((int)); 145 void i82378_write_elcr __P((int, u_int8_t)); 146 147 int 148 i82378_setup_elcr() 149 { 150 int rv; 151 152 /* 153 * We could probe configuration space to see that there's 154 * actually an SIO present, but we are using this as a 155 * fall-back in case nothing else matches. 156 */ 157 158 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 159 160 if (rv == 0) { 161 sio_read_elcr = i82378_read_elcr; 162 sio_write_elcr = i82378_write_elcr; 163 } 164 165 return (rv); 166 } 167 168 u_int8_t 169 i82378_read_elcr(elcr) 170 int elcr; 171 { 172 173 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 174 } 175 176 void 177 i82378_write_elcr(elcr, val) 178 int elcr; 179 u_int8_t val; 180 { 181 182 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 183 } 184 185 /******************** Cypress CY82C693 ELCR functions ********************/ 186 187 int cy82c693_setup_elcr __P((void)); 188 u_int8_t cy82c693_read_elcr __P((int)); 189 void cy82c693_write_elcr __P((int, u_int8_t)); 190 191 int 192 cy82c693_setup_elcr() 193 { 194 int device, maxndevs; 195 pcitag_t tag; 196 pcireg_t id; 197 198 /* 199 * Search PCI configuration space for a Cypress CY82C693. 200 * 201 * Note we can make some assumptions about our bus number 202 * here, because: 203 * 204 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 205 * 206 * (2) any ISA/EISA bridges must be attached to primary PCI 207 * busses (i.e. bus zero). 208 */ 209 210 maxndevs = pci_bus_maxdevs(sio_pc, 0); 211 212 for (device = 0; device < maxndevs; device++) { 213 tag = pci_make_tag(sio_pc, 0, device, 0); 214 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 215 216 /* Invalid vendor ID value? */ 217 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 218 continue; 219 /* XXX Not invalid, but we've done this ~forever. */ 220 if (PCI_VENDOR(id) == 0) 221 continue; 222 223 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 224 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 225 continue; 226 227 /* 228 * Found one! 229 */ 230 231 #if 0 232 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 233 device); 234 #endif 235 236 /* 237 * The CY82C693's ELCR registers are accessed indirectly 238 * via (IO_ICU1 + 2) (address) and (IO_ICU1 + 3) (data). 239 */ 240 sio_ioh_elcr = sio_ioh_icu1; 241 242 sio_read_elcr = cy82c693_read_elcr; 243 sio_write_elcr = cy82c693_write_elcr; 244 245 return (0); 246 } 247 248 /* 249 * Didn't find a CY82C693. 250 */ 251 return (ENODEV); 252 } 253 254 u_int8_t 255 cy82c693_read_elcr(elcr) 256 int elcr; 257 { 258 259 bus_space_write_1(sio_iot, sio_ioh_elcr, 0x02, 0x03 + elcr); 260 return (bus_space_read_1(sio_iot, sio_ioh_elcr, 0x03)); 261 } 262 263 void 264 cy82c693_write_elcr(elcr, val) 265 int elcr; 266 u_int8_t val; 267 { 268 269 bus_space_write_1(sio_iot, sio_ioh_elcr, 0x02, 0x03 + elcr); 270 bus_space_write_1(sio_iot, sio_ioh_elcr, 0x03, val); 271 } 272 273 /******************** ELCR access function configuration ********************/ 274 275 /* 276 * Put the Intel SIO at the end, so we fall back on it if we don't 277 * find anything else. If any of the non-Intel functions find a 278 * matching device, but are unable to map it for whatever reason, 279 * they should panic. 280 */ 281 282 int (*sio_elcr_setup_funcs[]) __P((void)) = { 283 cy82c693_setup_elcr, 284 i82378_setup_elcr, 285 NULL, 286 }; 287 288 /******************** Shared SIO/Cypress functions ********************/ 289 290 void 291 sio_setirqstat(irq, enabled, type) 292 int irq, enabled; 293 int type; 294 { 295 u_int8_t ocw1[2], elcr[2]; 296 int icu, bit; 297 298 #if 0 299 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 300 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 301 #endif 302 303 icu = irq / 8; 304 bit = irq % 8; 305 306 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 307 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 308 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 309 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 310 311 /* 312 * interrupt enable: set bit to mask (disable) interrupt. 313 */ 314 if (enabled) 315 ocw1[icu] &= ~(1 << bit); 316 else 317 ocw1[icu] |= 1 << bit; 318 319 /* 320 * interrupt type select: set bit to get level-triggered. 321 */ 322 if (type == IST_LEVEL) 323 elcr[icu] |= 1 << bit; 324 else 325 elcr[icu] &= ~(1 << bit); 326 327 #ifdef not_here 328 /* see the init function... */ 329 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 330 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 331 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 332 #endif 333 334 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 335 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 336 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 337 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 338 } 339 340 void 341 sio_intr_setup(pc, iot) 342 pci_chipset_tag_t pc; 343 bus_space_tag_t iot; 344 { 345 int i; 346 347 sio_iot = iot; 348 sio_pc = pc; 349 350 if (bus_space_map(sio_iot, IO_ICU1, IO_ICUSIZE, 0, &sio_ioh_icu1) || 351 bus_space_map(sio_iot, IO_ICU2, IO_ICUSIZE, 0, &sio_ioh_icu2)) 352 panic("sio_intr_setup: can't map ICU I/O ports"); 353 354 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 355 if ((*sio_elcr_setup_funcs[i])() == 0) 356 break; 357 if (sio_elcr_setup_funcs[i] == NULL) 358 panic("sio_intr_setup: can't map ELCR"); 359 360 #ifdef BROKEN_PROM_CONSOLE 361 /* 362 * Remember the initial values, so we can restore them later. 363 */ 364 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 365 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 366 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 367 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 368 shutdownhook_establish(sio_intr_shutdown, 0); 369 #endif 370 371 sio_intr = alpha_shared_intr_alloc(ICU_LEN); 372 373 /* 374 * set up initial values for interrupt enables. 375 */ 376 for (i = 0; i < ICU_LEN; i++) { 377 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 378 379 switch (i) { 380 case 0: 381 case 1: 382 case 8: 383 case 13: 384 /* 385 * IRQs 0, 1, 8, and 13 must always be 386 * edge-triggered. 387 */ 388 sio_setirqstat(i, 0, IST_EDGE); 389 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 390 IST_EDGE); 391 specific_eoi(i); 392 break; 393 394 case 2: 395 /* 396 * IRQ 2 must be edge-triggered, and should be 397 * enabled (otherwise IRQs 8-15 are ignored). 398 */ 399 sio_setirqstat(i, 1, IST_EDGE); 400 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 401 IST_UNUSABLE); 402 break; 403 404 default: 405 /* 406 * Otherwise, disable the IRQ and set its 407 * type to (effectively) "unknown." 408 */ 409 sio_setirqstat(i, 0, IST_NONE); 410 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 411 IST_NONE); 412 specific_eoi(i); 413 break; 414 } 415 } 416 } 417 418 #ifdef BROKEN_PROM_CONSOLE 419 void 420 sio_intr_shutdown(arg) 421 void *arg; 422 { 423 /* 424 * Restore the initial values, to make the PROM happy. 425 */ 426 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 427 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 428 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 429 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 430 } 431 #endif 432 433 const char * 434 sio_intr_string(v, irq) 435 void *v; 436 int irq; 437 { 438 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 439 440 if (irq == 0 || irq >= ICU_LEN || irq == 2) 441 panic("sio_intr_string: bogus isa irq 0x%x\n", irq); 442 443 sprintf(irqstr, "isa irq %d", irq); 444 return (irqstr); 445 } 446 447 const struct evcnt * 448 sio_intr_evcnt(v, irq) 449 void *v; 450 int irq; 451 { 452 453 /* XXX for now, no evcnt parent reported */ 454 return (NULL); 455 } 456 457 void * 458 sio_intr_establish(v, irq, type, level, fn, arg) 459 void *v, *arg; 460 int irq; 461 int type; 462 int level; 463 int (*fn)(void *); 464 { 465 void *cookie; 466 467 if (irq > ICU_LEN || type == IST_NONE) 468 panic("sio_intr_establish: bogus irq or type"); 469 470 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 471 arg, "isa irq"); 472 473 if (cookie) 474 sio_setirqstat(irq, alpha_shared_intr_isactive(sio_intr, irq), 475 alpha_shared_intr_get_sharetype(sio_intr, irq)); 476 477 return (cookie); 478 } 479 480 void 481 sio_intr_disestablish(v, cookie) 482 void *v; 483 void *cookie; 484 { 485 struct alpha_shared_intrhand *ih = cookie; 486 int s, ist, irq = ih->ih_num; 487 488 s = splhigh(); 489 490 /* Remove it from the link. */ 491 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 492 493 /* 494 * Decide if we should disable the interrupt. We must ensure 495 * that: 496 * 497 * - An initially-enabled interrupt is never disabled. 498 * - An initially-LT interrupt is never untyped. 499 */ 500 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 501 /* 502 * IRQs 0, 1, 8, and 13 must always be edge-triggered 503 * (see setup). 504 */ 505 switch (irq) { 506 case 0: 507 case 1: 508 case 8: 509 case 13: 510 /* 511 * If the interrupt was initially level-triggered 512 * a warning was printed in setup. 513 */ 514 ist = IST_EDGE; 515 break; 516 517 default: 518 ist = IST_NONE; 519 break; 520 } 521 sio_setirqstat(irq, 0, ist); 522 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 523 } 524 525 splx(s); 526 } 527 528 void 529 sio_iointr(framep, vec) 530 void *framep; 531 unsigned long vec; 532 { 533 int irq; 534 535 irq = (vec - 0x800) >> 4; 536 #ifdef DIAGNOSTIC 537 if (irq > ICU_LEN || irq < 0) 538 panic("sio_iointr: irq out of range (%d)", irq); 539 #endif 540 541 #ifdef EVCNT_COUNTERS 542 sio_intr_evcnt.ev_count++; 543 #else 544 #ifdef DEBUG 545 if (ICU_LEN != INTRCNT_ISA_IRQ_LEN) 546 panic("sio interrupt counter sizes inconsistent"); 547 #endif 548 intrcnt[INTRCNT_ISA_IRQ + irq]++; 549 #endif 550 551 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 552 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 553 554 /* 555 * Some versions of the machines which use the SIO 556 * (or is it some PALcode revisions on those machines?) 557 * require the non-specific EOI to be fed to the PIC(s) 558 * by the interrupt handler. 559 */ 560 specific_eoi(irq); 561 } 562 563 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 564 565 int 566 sio_intr_alloc(v, mask, type, irq) 567 void *v; 568 int mask; 569 int type; 570 int *irq; 571 { 572 int i, tmp, bestirq, count; 573 struct alpha_shared_intrhand **p, *q; 574 575 if (type == IST_NONE) 576 panic("intr_alloc: bogus type"); 577 578 bestirq = -1; 579 count = -1; 580 581 /* some interrupts should never be dynamically allocated */ 582 mask &= 0xdef8; 583 584 /* 585 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 586 * the right answer is to do "breadth-first" searching of devices. 587 */ 588 mask &= 0xefbf; 589 590 for (i = 0; i < ICU_LEN; i++) { 591 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 592 continue; 593 594 switch(sio_intr[i].intr_sharetype) { 595 case IST_NONE: 596 /* 597 * if nothing's using the irq, just return it 598 */ 599 *irq = i; 600 return (0); 601 602 case IST_EDGE: 603 case IST_LEVEL: 604 if (type != sio_intr[i].intr_sharetype) 605 continue; 606 /* 607 * if the irq is shareable, count the number of other 608 * handlers, and if it's smaller than the last irq like 609 * this, remember it 610 * 611 * XXX We should probably also consider the 612 * interrupt level and stick IPL_TTY with other 613 * IPL_TTY, etc. 614 */ 615 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 616 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 617 ; 618 if ((bestirq == -1) || (count > tmp)) { 619 bestirq = i; 620 count = tmp; 621 } 622 break; 623 624 case IST_PULSE: 625 /* this just isn't shareable */ 626 continue; 627 } 628 } 629 630 if (bestirq == -1) 631 return (1); 632 633 *irq = bestirq; 634 635 return (0); 636 } 637 638 static void 639 specific_eoi(irq) 640 int irq; 641 { 642 if (irq > 7) 643 bus_space_write_1(sio_iot, 644 sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */ 645 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); 646 } 647
Indexes created Thu Oct 16 14:10:15 GMT 2025