sio_pic.c revision 1.35.16.1
1 /* $NetBSD: sio_pic.c,v 1.35.16.1 2008/05/18 12:31:24 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.35.16.1 2008/05/18 12:31:24 yamt Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/malloc.h> 68 #include <sys/syslog.h> 69 70 #include <machine/intr.h> 71 #include <machine/bus.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/cy82c693reg.h> 78 #include <dev/pci/cy82c693var.h> 79 80 #include <dev/isa/isareg.h> 81 #include <dev/isa/isavar.h> 82 #include <alpha/pci/siovar.h> 83 84 #include "sio.h" 85 86 /* 87 * To add to the long history of wonderful PROM console traits, 88 * AlphaStation PROMs don't reset themselves completely on boot! 89 * Therefore, if an interrupt was turned on when the kernel was 90 * started, we're not going to EVER turn it off... I don't know 91 * what will happen if new interrupts (that the PROM console doesn't 92 * want) are turned on. I'll burn that bridge when I come to it. 93 */ 94 #define BROKEN_PROM_CONSOLE 95 96 /* 97 * Private functions and variables. 98 */ 99 100 bus_space_tag_t sio_iot; 101 pci_chipset_tag_t sio_pc; 102 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 103 104 #define ICU_LEN 16 /* number of ISA IRQs */ 105 106 static struct alpha_shared_intr *sio_intr; 107 108 #ifndef STRAY_MAX 109 #define STRAY_MAX 5 110 #endif 111 112 #ifdef BROKEN_PROM_CONSOLE 113 /* 114 * If prom console is broken, must remember the initial interrupt 115 * settings and enforce them. WHEE! 116 */ 117 u_int8_t initial_ocw1[2]; 118 u_int8_t initial_elcr[2]; 119 #endif 120 121 void sio_setirqstat __P((int, int, int)); 122 123 u_int8_t (*sio_read_elcr) __P((int)); 124 void (*sio_write_elcr) __P((int, u_int8_t)); 125 static void specific_eoi __P((int)); 126 #ifdef BROKEN_PROM_CONSOLE 127 void sio_intr_shutdown __P((void *)); 128 #endif 129 130 /******************** i82378 SIO ELCR functions ********************/ 131 132 int i82378_setup_elcr __P((void)); 133 u_int8_t i82378_read_elcr __P((int)); 134 void i82378_write_elcr __P((int, u_int8_t)); 135 136 bus_space_handle_t sio_ioh_elcr; 137 138 int 139 i82378_setup_elcr() 140 { 141 int rv; 142 143 /* 144 * We could probe configuration space to see that there's 145 * actually an SIO present, but we are using this as a 146 * fall-back in case nothing else matches. 147 */ 148 149 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 150 151 if (rv == 0) { 152 sio_read_elcr = i82378_read_elcr; 153 sio_write_elcr = i82378_write_elcr; 154 } 155 156 return (rv); 157 } 158 159 u_int8_t 160 i82378_read_elcr(elcr) 161 int elcr; 162 { 163 164 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 165 } 166 167 void 168 i82378_write_elcr(elcr, val) 169 int elcr; 170 u_int8_t val; 171 { 172 173 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 174 } 175 176 /******************** Cypress CY82C693 ELCR functions ********************/ 177 178 int cy82c693_setup_elcr __P((void)); 179 u_int8_t cy82c693_read_elcr __P((int)); 180 void cy82c693_write_elcr __P((int, u_int8_t)); 181 182 const struct cy82c693_handle *sio_cy82c693_handle; 183 184 int 185 cy82c693_setup_elcr() 186 { 187 int device, maxndevs; 188 pcitag_t tag; 189 pcireg_t id; 190 191 /* 192 * Search PCI configuration space for a Cypress CY82C693. 193 * 194 * Note we can make some assumptions about our bus number 195 * here, because: 196 * 197 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 198 * 199 * (2) any ISA/EISA bridges must be attached to primary PCI 200 * busses (i.e. bus zero). 201 */ 202 203 maxndevs = pci_bus_maxdevs(sio_pc, 0); 204 205 for (device = 0; device < maxndevs; device++) { 206 tag = pci_make_tag(sio_pc, 0, device, 0); 207 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 208 209 /* Invalid vendor ID value? */ 210 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 211 continue; 212 /* XXX Not invalid, but we've done this ~forever. */ 213 if (PCI_VENDOR(id) == 0) 214 continue; 215 216 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 217 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 218 continue; 219 220 /* 221 * Found one! 222 */ 223 224 #if 0 225 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 226 device); 227 #endif 228 229 sio_cy82c693_handle = cy82c693_init(sio_iot); 230 sio_read_elcr = cy82c693_read_elcr; 231 sio_write_elcr = cy82c693_write_elcr; 232 233 return (0); 234 } 235 236 /* 237 * Didn't find a CY82C693. 238 */ 239 return (ENODEV); 240 } 241 242 u_int8_t 243 cy82c693_read_elcr(elcr) 244 int elcr; 245 { 246 247 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 248 } 249 250 void 251 cy82c693_write_elcr(elcr, val) 252 int elcr; 253 u_int8_t val; 254 { 255 256 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 257 } 258 259 /******************** ELCR access function configuration ********************/ 260 261 /* 262 * Put the Intel SIO at the end, so we fall back on it if we don't 263 * find anything else. If any of the non-Intel functions find a 264 * matching device, but are unable to map it for whatever reason, 265 * they should panic. 266 */ 267 268 int (*sio_elcr_setup_funcs[]) __P((void)) = { 269 cy82c693_setup_elcr, 270 i82378_setup_elcr, 271 NULL, 272 }; 273 274 /******************** Shared SIO/Cypress functions ********************/ 275 276 void 277 sio_setirqstat(irq, enabled, type) 278 int irq, enabled; 279 int type; 280 { 281 u_int8_t ocw1[2], elcr[2]; 282 int icu, bit; 283 284 #if 0 285 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 286 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 287 #endif 288 289 icu = irq / 8; 290 bit = irq % 8; 291 292 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 293 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 294 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 295 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 296 297 /* 298 * interrupt enable: set bit to mask (disable) interrupt. 299 */ 300 if (enabled) 301 ocw1[icu] &= ~(1 << bit); 302 else 303 ocw1[icu] |= 1 << bit; 304 305 /* 306 * interrupt type select: set bit to get level-triggered. 307 */ 308 if (type == IST_LEVEL) 309 elcr[icu] |= 1 << bit; 310 else 311 elcr[icu] &= ~(1 << bit); 312 313 #ifdef not_here 314 /* see the init function... */ 315 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 316 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 317 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 318 #endif 319 320 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 321 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 322 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 323 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 324 } 325 326 void 327 sio_intr_setup(pc, iot) 328 pci_chipset_tag_t pc; 329 bus_space_tag_t iot; 330 { 331 char *cp; 332 int i; 333 334 sio_iot = iot; 335 sio_pc = pc; 336 337 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 338 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 339 panic("sio_intr_setup: can't map ICU I/O ports"); 340 341 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 342 if ((*sio_elcr_setup_funcs[i])() == 0) 343 break; 344 if (sio_elcr_setup_funcs[i] == NULL) 345 panic("sio_intr_setup: can't map ELCR"); 346 347 #ifdef BROKEN_PROM_CONSOLE 348 /* 349 * Remember the initial values, so we can restore them later. 350 */ 351 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 352 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 353 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 354 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 355 shutdownhook_establish(sio_intr_shutdown, 0); 356 #endif 357 358 sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8); 359 360 /* 361 * set up initial values for interrupt enables. 362 */ 363 for (i = 0; i < ICU_LEN; i++) { 364 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 365 366 cp = alpha_shared_intr_string(sio_intr, i); 367 sprintf(cp, "irq %d", i); 368 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 369 EVCNT_TYPE_INTR, NULL, "isa", cp); 370 371 switch (i) { 372 case 0: 373 case 1: 374 case 8: 375 case 13: 376 /* 377 * IRQs 0, 1, 8, and 13 must always be 378 * edge-triggered. 379 */ 380 sio_setirqstat(i, 0, IST_EDGE); 381 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 382 IST_EDGE); 383 specific_eoi(i); 384 break; 385 386 case 2: 387 /* 388 * IRQ 2 must be edge-triggered, and should be 389 * enabled (otherwise IRQs 8-15 are ignored). 390 */ 391 sio_setirqstat(i, 1, IST_EDGE); 392 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 393 IST_UNUSABLE); 394 break; 395 396 default: 397 /* 398 * Otherwise, disable the IRQ and set its 399 * type to (effectively) "unknown." 400 */ 401 sio_setirqstat(i, 0, IST_NONE); 402 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 403 IST_NONE); 404 specific_eoi(i); 405 break; 406 } 407 } 408 } 409 410 #ifdef BROKEN_PROM_CONSOLE 411 void 412 sio_intr_shutdown(arg) 413 void *arg; 414 { 415 /* 416 * Restore the initial values, to make the PROM happy. 417 */ 418 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 419 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 420 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 421 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 422 } 423 #endif 424 425 const char * 426 sio_intr_string(v, irq) 427 void *v; 428 int irq; 429 { 430 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 431 432 if (irq == 0 || irq >= ICU_LEN || irq == 2) 433 panic("sio_intr_string: bogus isa irq 0x%x", irq); 434 435 sprintf(irqstr, "isa irq %d", irq); 436 return (irqstr); 437 } 438 439 const struct evcnt * 440 sio_intr_evcnt(v, irq) 441 void *v; 442 int irq; 443 { 444 445 if (irq == 0 || irq >= ICU_LEN || irq == 2) 446 panic("sio_intr_evcnt: bogus isa irq 0x%x", irq); 447 448 return (alpha_shared_intr_evcnt(sio_intr, irq)); 449 } 450 451 void * 452 sio_intr_establish(v, irq, type, level, fn, arg) 453 void *v, *arg; 454 int irq; 455 int type; 456 int level; 457 int (*fn)(void *); 458 { 459 void *cookie; 460 461 if (irq > ICU_LEN || type == IST_NONE) 462 panic("sio_intr_establish: bogus irq or type"); 463 464 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 465 arg, "isa irq"); 466 467 if (cookie != NULL && 468 alpha_shared_intr_firstactive(sio_intr, irq)) { 469 scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL, 470 level); 471 sio_setirqstat(irq, 1, 472 alpha_shared_intr_get_sharetype(sio_intr, irq)); 473 } 474 475 return (cookie); 476 } 477 478 void 479 sio_intr_disestablish(v, cookie) 480 void *v; 481 void *cookie; 482 { 483 struct alpha_shared_intrhand *ih = cookie; 484 int s, ist, irq = ih->ih_num; 485 486 s = splhigh(); 487 488 /* Remove it from the link. */ 489 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 490 491 /* 492 * Decide if we should disable the interrupt. We must ensure 493 * that: 494 * 495 * - An initially-enabled interrupt is never disabled. 496 * - An initially-LT interrupt is never untyped. 497 */ 498 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 499 /* 500 * IRQs 0, 1, 8, and 13 must always be edge-triggered 501 * (see setup). 502 */ 503 switch (irq) { 504 case 0: 505 case 1: 506 case 8: 507 case 13: 508 /* 509 * If the interrupt was initially level-triggered 510 * a warning was printed in setup. 511 */ 512 ist = IST_EDGE; 513 break; 514 515 default: 516 ist = IST_NONE; 517 break; 518 } 519 sio_setirqstat(irq, 0, ist); 520 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 521 522 /* Release our SCB vector. */ 523 scb_free(0x800 + SCB_IDXTOVEC(irq)); 524 } 525 526 splx(s); 527 } 528 529 void 530 sio_iointr(arg, vec) 531 void *arg; 532 unsigned long vec; 533 { 534 int irq; 535 536 irq = SCB_VECTOIDX(vec - 0x800); 537 538 #ifdef DIAGNOSTIC 539 if (irq > ICU_LEN || irq < 0) 540 panic("sio_iointr: irq out of range (%d)", irq); 541 #endif 542 543 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 544 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 545 else 546 alpha_shared_intr_reset_strays(sio_intr, irq); 547 548 /* 549 * Some versions of the machines which use the SIO 550 * (or is it some PALcode revisions on those machines?) 551 * require the non-specific EOI to be fed to the PIC(s) 552 * by the interrupt handler. 553 */ 554 specific_eoi(irq); 555 } 556 557 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 558 559 int 560 sio_intr_alloc(v, mask, type, irq) 561 void *v; 562 int mask; 563 int type; 564 int *irq; 565 { 566 int i, tmp, bestirq, count; 567 struct alpha_shared_intrhand **p, *q; 568 569 if (type == IST_NONE) 570 panic("intr_alloc: bogus type"); 571 572 bestirq = -1; 573 count = -1; 574 575 /* some interrupts should never be dynamically allocated */ 576 mask &= 0xdef8; 577 578 /* 579 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 580 * the right answer is to do "breadth-first" searching of devices. 581 */ 582 mask &= 0xefbf; 583 584 for (i = 0; i < ICU_LEN; i++) { 585 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 586 continue; 587 588 switch(sio_intr[i].intr_sharetype) { 589 case IST_NONE: 590 /* 591 * if nothing's using the irq, just return it 592 */ 593 *irq = i; 594 return (0); 595 596 case IST_EDGE: 597 case IST_LEVEL: 598 if (type != sio_intr[i].intr_sharetype) 599 continue; 600 /* 601 * if the irq is shareable, count the number of other 602 * handlers, and if it's smaller than the last irq like 603 * this, remember it 604 * 605 * XXX We should probably also consider the 606 * interrupt level and stick IPL_TTY with other 607 * IPL_TTY, etc. 608 */ 609 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 610 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 611 ; 612 if ((bestirq == -1) || (count > tmp)) { 613 bestirq = i; 614 count = tmp; 615 } 616 break; 617 618 case IST_PULSE: 619 /* this just isn't shareable */ 620 continue; 621 } 622 } 623 624 if (bestirq == -1) 625 return (1); 626 627 *irq = bestirq; 628 629 return (0); 630 } 631 632 static void 633 specific_eoi(irq) 634 int irq; 635 { 636 if (irq > 7) 637 bus_space_write_1(sio_iot, 638 sio_ioh_icu2, 0, 0x60 | (irq & 0x07)); /* XXX */ 639 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq)); 640 } 641
Indexes created Thu Oct 16 14:10:15 GMT 2025