sio_pic.c revision 1.42.6.1
1 /* $NetBSD: sio_pic.c,v 1.42.6.1 2014/08/20 00:02:41 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.42.6.1 2014/08/20 00:02:41 tls Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/malloc.h> 68 #include <sys/syslog.h> 69 70 #include <machine/intr.h> 71 #include <sys/bus.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/cy82c693reg.h> 78 #include <dev/pci/cy82c693var.h> 79 80 #include <dev/isa/isareg.h> 81 #include <dev/isa/isavar.h> 82 #include <alpha/pci/siovar.h> 83 84 #include "sio.h" 85 86 /* 87 * To add to the long history of wonderful PROM console traits, 88 * AlphaStation PROMs don't reset themselves completely on boot! 89 * Therefore, if an interrupt was turned on when the kernel was 90 * started, we're not going to EVER turn it off... I don't know 91 * what will happen if new interrupts (that the PROM console doesn't 92 * want) are turned on. I'll burn that bridge when I come to it. 93 */ 94 #define BROKEN_PROM_CONSOLE 95 96 /* 97 * Private functions and variables. 98 */ 99 100 bus_space_tag_t sio_iot; 101 pci_chipset_tag_t sio_pc; 102 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 103 104 #define ICU_LEN 16 /* number of ISA IRQs */ 105 106 static struct alpha_shared_intr *sio_intr; 107 108 #ifndef STRAY_MAX 109 #define STRAY_MAX 5 110 #endif 111 112 #ifdef BROKEN_PROM_CONSOLE 113 /* 114 * If prom console is broken, must remember the initial interrupt 115 * settings and enforce them. WHEE! 116 */ 117 uint8_t initial_ocw1[2]; 118 uint8_t initial_elcr[2]; 119 #endif 120 121 void sio_setirqstat(int, int, int); 122 123 uint8_t (*sio_read_elcr)(int); 124 void (*sio_write_elcr)(int, uint8_t); 125 static void specific_eoi(int); 126 #ifdef BROKEN_PROM_CONSOLE 127 void sio_intr_shutdown(void *); 128 #endif 129 130 /******************** i82378 SIO ELCR functions ********************/ 131 132 int i82378_setup_elcr(void); 133 uint8_t i82378_read_elcr(int); 134 void i82378_write_elcr(int, uint8_t); 135 136 bus_space_handle_t sio_ioh_elcr; 137 138 int 139 i82378_setup_elcr(void) 140 { 141 int rv; 142 143 /* 144 * We could probe configuration space to see that there's 145 * actually an SIO present, but we are using this as a 146 * fall-back in case nothing else matches. 147 */ 148 149 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 150 151 if (rv == 0) { 152 sio_read_elcr = i82378_read_elcr; 153 sio_write_elcr = i82378_write_elcr; 154 } 155 156 return (rv); 157 } 158 159 uint8_t 160 i82378_read_elcr(int elcr) 161 { 162 163 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 164 } 165 166 void 167 i82378_write_elcr(int elcr, uint8_t val) 168 { 169 170 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 171 } 172 173 /******************** Cypress CY82C693 ELCR functions ********************/ 174 175 int cy82c693_setup_elcr(void); 176 uint8_t cy82c693_read_elcr(int); 177 void cy82c693_write_elcr(int, uint8_t); 178 179 const struct cy82c693_handle *sio_cy82c693_handle; 180 181 int 182 cy82c693_setup_elcr(void) 183 { 184 int device, maxndevs; 185 pcitag_t tag; 186 pcireg_t id; 187 188 /* 189 * Search PCI configuration space for a Cypress CY82C693. 190 * 191 * Note we can make some assumptions about our bus number 192 * here, because: 193 * 194 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 195 * 196 * (2) any ISA/EISA bridges must be attached to primary PCI 197 * busses (i.e. bus zero). 198 */ 199 200 maxndevs = pci_bus_maxdevs(sio_pc, 0); 201 202 for (device = 0; device < maxndevs; device++) { 203 tag = pci_make_tag(sio_pc, 0, device, 0); 204 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 205 206 /* Invalid vendor ID value? */ 207 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 208 continue; 209 /* XXX Not invalid, but we've done this ~forever. */ 210 if (PCI_VENDOR(id) == 0) 211 continue; 212 213 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 214 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 215 continue; 216 217 /* 218 * Found one! 219 */ 220 221 #if 0 222 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 223 device); 224 #endif 225 226 sio_cy82c693_handle = cy82c693_init(sio_iot); 227 sio_read_elcr = cy82c693_read_elcr; 228 sio_write_elcr = cy82c693_write_elcr; 229 230 return (0); 231 } 232 233 /* 234 * Didn't find a CY82C693. 235 */ 236 return (ENODEV); 237 } 238 239 uint8_t 240 cy82c693_read_elcr(int elcr) 241 { 242 243 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 244 } 245 246 void 247 cy82c693_write_elcr(int elcr, uint8_t val) 248 { 249 250 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 251 } 252 253 /******************** ELCR access function configuration ********************/ 254 255 /* 256 * Put the Intel SIO at the end, so we fall back on it if we don't 257 * find anything else. If any of the non-Intel functions find a 258 * matching device, but are unable to map it for whatever reason, 259 * they should panic. 260 */ 261 262 int (*const sio_elcr_setup_funcs[])(void) = { 263 cy82c693_setup_elcr, 264 i82378_setup_elcr, 265 NULL, 266 }; 267 268 /******************** Shared SIO/Cypress functions ********************/ 269 270 void 271 sio_setirqstat(int irq, int enabled, int type) 272 { 273 uint8_t ocw1[2], elcr[2]; 274 int icu, bit; 275 276 #if 0 277 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 278 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 279 #endif 280 281 icu = irq / 8; 282 bit = irq % 8; 283 284 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 285 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 286 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 287 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 288 289 /* 290 * interrupt enable: set bit to mask (disable) interrupt. 291 */ 292 if (enabled) 293 ocw1[icu] &= ~(1 << bit); 294 else 295 ocw1[icu] |= 1 << bit; 296 297 /* 298 * interrupt type select: set bit to get level-triggered. 299 */ 300 if (type == IST_LEVEL) 301 elcr[icu] |= 1 << bit; 302 else 303 elcr[icu] &= ~(1 << bit); 304 305 #ifdef not_here 306 /* see the init function... */ 307 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 308 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 309 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 310 #endif 311 312 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 313 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 314 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 315 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 316 } 317 318 void 319 sio_intr_setup(pci_chipset_tag_t pc, bus_space_tag_t iot) 320 { 321 char *cp; 322 int i; 323 324 sio_iot = iot; 325 sio_pc = pc; 326 327 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 328 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 329 panic("sio_intr_setup: can't map ICU I/O ports"); 330 331 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 332 if ((*sio_elcr_setup_funcs[i])() == 0) 333 break; 334 if (sio_elcr_setup_funcs[i] == NULL) 335 panic("sio_intr_setup: can't map ELCR"); 336 337 #ifdef BROKEN_PROM_CONSOLE 338 /* 339 * Remember the initial values, so we can restore them later. 340 */ 341 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 342 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 343 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 344 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 345 shutdownhook_establish(sio_intr_shutdown, 0); 346 #endif 347 348 #define PCI_SIO_IRQ_STR 8 349 sio_intr = alpha_shared_intr_alloc(ICU_LEN, PCI_SIO_IRQ_STR); 350 351 /* 352 * set up initial values for interrupt enables. 353 */ 354 for (i = 0; i < ICU_LEN; i++) { 355 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 356 357 cp = alpha_shared_intr_string(sio_intr, i); 358 snprintf(cp, PCI_SIO_IRQ_STR, "irq %d", i); 359 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 360 EVCNT_TYPE_INTR, NULL, "isa", cp); 361 362 switch (i) { 363 case 0: 364 case 1: 365 case 8: 366 case 13: 367 /* 368 * IRQs 0, 1, 8, and 13 must always be 369 * edge-triggered. 370 */ 371 sio_setirqstat(i, 0, IST_EDGE); 372 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 373 IST_EDGE); 374 specific_eoi(i); 375 break; 376 377 case 2: 378 /* 379 * IRQ 2 must be edge-triggered, and should be 380 * enabled (otherwise IRQs 8-15 are ignored). 381 */ 382 sio_setirqstat(i, 1, IST_EDGE); 383 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 384 IST_UNUSABLE); 385 break; 386 387 default: 388 /* 389 * Otherwise, disable the IRQ and set its 390 * type to (effectively) "unknown." 391 */ 392 sio_setirqstat(i, 0, IST_NONE); 393 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 394 IST_NONE); 395 specific_eoi(i); 396 break; 397 } 398 } 399 } 400 401 #ifdef BROKEN_PROM_CONSOLE 402 void 403 sio_intr_shutdown(void *arg) 404 { 405 /* 406 * Restore the initial values, to make the PROM happy. 407 */ 408 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 409 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 410 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 411 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 412 } 413 #endif 414 415 const char * 416 sio_intr_string(void *v, int irq, char *buf, size_t len) 417 { 418 if (irq == 0 || irq >= ICU_LEN || irq == 2) 419 panic("%s: bogus isa irq 0x%x", __func__, irq); 420 421 snprintf(buf, len, "isa irq %d", irq); 422 return buf; 423 } 424 425 const struct evcnt * 426 sio_intr_evcnt(void *v, int irq) 427 { 428 429 if (irq == 0 || irq >= ICU_LEN || irq == 2) 430 panic("%s: bogus isa irq 0x%x", __func__, irq); 431 432 return (alpha_shared_intr_evcnt(sio_intr, irq)); 433 } 434 435 void * 436 sio_intr_establish(void *v, int irq, int type, int level, int (*fn)(void *), void *arg) 437 { 438 void *cookie; 439 440 if (irq > ICU_LEN || type == IST_NONE) 441 panic("sio_intr_establish: bogus irq or type"); 442 443 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 444 arg, "isa irq"); 445 446 if (cookie != NULL && 447 alpha_shared_intr_firstactive(sio_intr, irq)) { 448 scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL, 449 level); 450 sio_setirqstat(irq, 1, 451 alpha_shared_intr_get_sharetype(sio_intr, irq)); 452 } 453 454 return (cookie); 455 } 456 457 void 458 sio_intr_disestablish(void *v, void *cookie) 459 { 460 struct alpha_shared_intrhand *ih = cookie; 461 int s, ist, irq = ih->ih_num; 462 463 s = splhigh(); 464 465 /* Remove it from the link. */ 466 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 467 468 /* 469 * Decide if we should disable the interrupt. We must ensure 470 * that: 471 * 472 * - An initially-enabled interrupt is never disabled. 473 * - An initially-LT interrupt is never untyped. 474 */ 475 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 476 /* 477 * IRQs 0, 1, 8, and 13 must always be edge-triggered 478 * (see setup). 479 */ 480 switch (irq) { 481 case 0: 482 case 1: 483 case 8: 484 case 13: 485 /* 486 * If the interrupt was initially level-triggered 487 * a warning was printed in setup. 488 */ 489 ist = IST_EDGE; 490 break; 491 492 default: 493 ist = IST_NONE; 494 break; 495 } 496 sio_setirqstat(irq, 0, ist); 497 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 498 499 /* Release our SCB vector. */ 500 scb_free(0x800 + SCB_IDXTOVEC(irq)); 501 } 502 503 splx(s); 504 } 505 506 void 507 sio_iointr(void *arg, unsigned long vec) 508 { 509 int irq; 510 511 irq = SCB_VECTOIDX(vec - 0x800); 512 513 #ifdef DIAGNOSTIC 514 if (irq > ICU_LEN || irq < 0) 515 panic("sio_iointr: irq out of range (%d)", irq); 516 #endif 517 518 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 519 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 520 else 521 alpha_shared_intr_reset_strays(sio_intr, irq); 522 523 /* 524 * Some versions of the machines which use the SIO 525 * (or is it some PALcode revisions on those machines?) 526 * require the non-specific EOI to be fed to the PIC(s) 527 * by the interrupt handler. 528 */ 529 specific_eoi(irq); 530 } 531 532 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 533 534 int 535 sio_intr_alloc(void *v, int mask, int type, int *irq) 536 { 537 int i, tmp, bestirq, count; 538 struct alpha_shared_intrhand **p, *q; 539 540 if (type == IST_NONE) 541 panic("intr_alloc: bogus type"); 542 543 bestirq = -1; 544 count = -1; 545 546 /* some interrupts should never be dynamically allocated */ 547 mask &= 0xdef8; 548 549 /* 550 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 551 * the right answer is to do "breadth-first" searching of devices. 552 */ 553 mask &= 0xefbf; 554 555 for (i = 0; i < ICU_LEN; i++) { 556 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 557 continue; 558 559 switch(sio_intr[i].intr_sharetype) { 560 case IST_NONE: 561 /* 562 * if nothing's using the irq, just return it 563 */ 564 *irq = i; 565 return (0); 566 567 case IST_EDGE: 568 case IST_LEVEL: 569 if (type != sio_intr[i].intr_sharetype) 570 continue; 571 /* 572 * if the irq is shareable, count the number of other 573 * handlers, and if it's smaller than the last irq like 574 * this, remember it 575 * 576 * XXX We should probably also consider the 577 * interrupt level and stick IPL_TTY with other 578 * IPL_TTY, etc. 579 */ 580 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 581 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 582 ; 583 if ((bestirq == -1) || (count > tmp)) { 584 bestirq = i; 585 count = tmp; 586 } 587 break; 588 589 case IST_PULSE: 590 /* this just isn't shareable */ 591 continue; 592 } 593 } 594 595 if (bestirq == -1) 596 return (1); 597 598 *irq = bestirq; 599 600 return (0); 601 } 602 603 static void 604 specific_eoi(int irq) 605 { 606 if (irq > 7) 607 bus_space_write_1(sio_iot, 608 sio_ioh_icu2, 0, 0x60 | (irq & 0x07)); /* XXX */ 609 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq)); 610 } 611
Indexes created Fri Oct 17 09:09:57 GMT 2025