tsc.c revision 1.16 1 1.16 dsl /* $NetBSD: tsc.c,v 1.16 2009/03/14 21:04:02 dsl Exp $ */
2 1.1 ross
3 1.1 ross /*-
4 1.1 ross * Copyright (c) 1999 by Ross Harvey. All rights reserved.
5 1.1 ross *
6 1.1 ross * Redistribution and use in source and binary forms, with or without
7 1.1 ross * modification, are permitted provided that the following conditions
8 1.1 ross * are met:
9 1.1 ross * 1. Redistributions of source code must retain the above copyright
10 1.1 ross * notice, this list of conditions and the following disclaimer.
11 1.1 ross * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ross * notice, this list of conditions and the following disclaimer in the
13 1.1 ross * documentation and/or other materials provided with the distribution.
14 1.1 ross * 3. All advertising materials mentioning features or use of this software
15 1.1 ross * must display the following acknowledgement:
16 1.1 ross * This product includes software developed by Ross Harvey.
17 1.1 ross * 4. The name of Ross Harvey may not be used to endorse or promote products
18 1.1 ross * derived from this software without specific prior written permission.
19 1.1 ross *
20 1.1 ross * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
21 1.1 ross * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 1.1 ross * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
23 1.1 ross * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
24 1.1 ross * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 1.1 ross * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 1.1 ross * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 1.1 ross * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 1.1 ross * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 1.1 ross * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 1.1 ross * SUCH DAMAGE.
31 1.1 ross *
32 1.1 ross */
33 1.1 ross
34 1.1 ross #include "opt_dec_6600.h"
35 1.1 ross
36 1.1 ross #include <sys/cdefs.h>
37 1.1 ross
38 1.16 dsl __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.16 2009/03/14 21:04:02 dsl Exp $");
39 1.1 ross
40 1.1 ross #include <sys/param.h>
41 1.1 ross #include <sys/systm.h>
42 1.1 ross #include <sys/device.h>
43 1.1 ross #include <sys/malloc.h>
44 1.1 ross
45 1.1 ross #include <machine/autoconf.h>
46 1.1 ross #include <machine/rpb.h>
47 1.3 thorpej #include <machine/sysarch.h>
48 1.1 ross
49 1.1 ross #include <dev/isa/isareg.h>
50 1.1 ross #include <dev/isa/isavar.h>
51 1.1 ross #include <dev/pci/pcireg.h>
52 1.1 ross #include <dev/pci/pcivar.h>
53 1.1 ross #include <alpha/pci/tsreg.h>
54 1.1 ross #include <alpha/pci/tsvar.h>
55 1.1 ross
56 1.1 ross #ifdef DEC_6600
57 1.1 ross #include <alpha/pci/pci_6600.h>
58 1.1 ross #endif
59 1.1 ross
60 1.1 ross #define tsc() { Generate ctags(1) key. }
61 1.1 ross
62 1.14 dsl int tscmatch(struct device *, struct cfdata *, void *);
63 1.14 dsl void tscattach(struct device *, struct device *, void *);
64 1.1 ross
65 1.9 thorpej CFATTACH_DECL(tsc, sizeof(struct tsc_softc),
66 1.9 thorpej tscmatch, tscattach, NULL, NULL);
67 1.1 ross
68 1.1 ross extern struct cfdriver tsc_cd;
69 1.1 ross
70 1.1 ross struct tsp_config tsp_configuration[2];
71 1.1 ross
72 1.14 dsl static int tscprint(void *, const char *pnp);
73 1.1 ross
74 1.14 dsl int tspmatch(struct device *, struct cfdata *, void *);
75 1.14 dsl void tspattach(struct device *, struct device *, void *);
76 1.1 ross
77 1.9 thorpej CFATTACH_DECL(tsp, sizeof(struct tsp_softc),
78 1.9 thorpej tspmatch, tspattach, NULL, NULL);
79 1.1 ross
80 1.1 ross extern struct cfdriver tsp_cd;
81 1.1 ross
82 1.14 dsl static int tsp_bus_get_window(int, int,
83 1.14 dsl struct alpha_bus_space_translation *);
84 1.3 thorpej
85 1.1 ross /* There can be only one */
86 1.3 thorpej static int tscfound;
87 1.1 ross
88 1.3 thorpej /* Which hose is the display console connected to? */
89 1.3 thorpej int tsp_console_hose;
90 1.1 ross
91 1.1 ross int
92 1.15 dsl tscmatch(struct device *parent, struct cfdata *match, void *aux)
93 1.1 ross {
94 1.1 ross struct mainbus_attach_args *ma = aux;
95 1.1 ross
96 1.1 ross return cputype == ST_DEC_6600
97 1.1 ross && strcmp(ma->ma_name, tsc_cd.cd_name) == 0
98 1.1 ross && !tscfound;
99 1.1 ross }
100 1.1 ross
101 1.1 ross void tscattach(parent, self, aux)
102 1.1 ross struct device *parent, *self;
103 1.1 ross void *aux;
104 1.1 ross {
105 1.1 ross int i;
106 1.1 ross int nbus;
107 1.1 ross u_int64_t csc, aar;
108 1.1 ross struct tsp_attach_args tsp;
109 1.1 ross struct mainbus_attach_args *ma = aux;
110 1.1 ross
111 1.1 ross tscfound = 1;
112 1.1 ross
113 1.1 ross csc = LDQP(TS_C_CSC);
114 1.1 ross
115 1.1 ross nbus = 1 + (CSC_BC(csc) >= 2);
116 1.1 ross printf(": 21272 Core Logic Chipset, Cchip rev %d\n"
117 1.1 ross "%s%d: %c Dchips, %d memory bus%s of %d bytes\n",
118 1.1 ross (int)MISC_REV(LDQP(TS_C_MISC)),
119 1.1 ross ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)],
120 1.1 ross nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0));
121 1.1 ross printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot);
122 1.1 ross for(i = 0; i < 4; ++i) {
123 1.1 ross aar = LDQP(TS_C_AAR0 + i * TS_STEP);
124 1.1 ross printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf,
125 1.1 ross aar & AAR_SPLIT ? " (split)" : "");
126 1.1 ross }
127 1.1 ross printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf);
128 1.1 ross
129 1.6 thorpej memset(&tsp, 0, sizeof tsp);
130 1.1 ross tsp.tsp_name = "tsp";
131 1.1 ross config_found(self, &tsp, NULL);
132 1.1 ross
133 1.1 ross if(LDQP(TS_C_CSC) & CSC_P1P) {
134 1.1 ross ++tsp.tsp_slot;
135 1.1 ross config_found(self, &tsp, tscprint);
136 1.1 ross }
137 1.1 ross }
138 1.1 ross
139 1.1 ross static int
140 1.15 dsl tscprint(void *aux, const char *p)
141 1.1 ross {
142 1.1 ross register struct tsp_attach_args *tsp = aux;
143 1.1 ross
144 1.1 ross if(p)
145 1.10 thorpej aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p);
146 1.1 ross return UNCONF;
147 1.1 ross }
148 1.1 ross
149 1.1 ross #define tsp() { Generate ctags(1) key. }
150 1.1 ross
151 1.1 ross int
152 1.15 dsl tspmatch(struct device *parent, struct cfdata *match, void *aux)
153 1.1 ross {
154 1.1 ross struct tsp_attach_args *t = aux;
155 1.1 ross
156 1.1 ross return cputype == ST_DEC_6600
157 1.1 ross && strcmp(t->tsp_name, tsp_cd.cd_name) == 0;
158 1.1 ross }
159 1.1 ross
160 1.3 thorpej void
161 1.16 dsl tspattach(struct device *parent, struct device *self, void *aux)
162 1.1 ross {
163 1.1 ross struct pcibus_attach_args pba;
164 1.1 ross struct tsp_attach_args *t = aux;
165 1.1 ross struct tsp_config *pcp;
166 1.1 ross
167 1.1 ross printf("\n");
168 1.1 ross pcp = tsp_init(1, t->tsp_slot);
169 1.5 thorpej
170 1.1 ross tsp_dma_init(pcp);
171 1.5 thorpej
172 1.5 thorpej /*
173 1.5 thorpej * Do PCI memory initialization that needs to be deferred until
174 1.5 thorpej * malloc is safe. On the Tsunami, we need to do this after
175 1.5 thorpej * DMA is initialized, as well.
176 1.5 thorpej */
177 1.5 thorpej tsp_bus_mem_init2(&pcp->pc_memt, pcp);
178 1.5 thorpej
179 1.1 ross pci_6600_pickintr(pcp);
180 1.5 thorpej
181 1.1 ross pba.pba_iot = &pcp->pc_iot;
182 1.1 ross pba.pba_memt = &pcp->pc_memt;
183 1.1 ross pba.pba_dmat =
184 1.1 ross alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI);
185 1.11 fvdl pba.pba_dmat64 = NULL;
186 1.1 ross pba.pba_pc = &pcp->pc_pc;
187 1.1 ross pba.pba_bus = 0;
188 1.7 thorpej pba.pba_bridgetag = NULL;
189 1.2 thorpej pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
190 1.2 thorpej PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
191 1.12 drochner config_found_ia(self, "pcibus", &pba, pcibusprint);
192 1.1 ross }
193 1.1 ross
194 1.1 ross struct tsp_config *
195 1.16 dsl tsp_init(int mallocsafe, int n)
196 1.16 dsl /* n: Pchip number */
197 1.1 ross {
198 1.1 ross struct tsp_config *pcp;
199 1.1 ross
200 1.1 ross KASSERT((n | 1) == 1);
201 1.1 ross pcp = &tsp_configuration[n];
202 1.1 ross pcp->pc_pslot = n;
203 1.1 ross pcp->pc_iobase = TS_Pn(n, 0);
204 1.1 ross pcp->pc_csr = S_PAGE(TS_Pn(n, P_CSRBASE));
205 1.1 ross if (!pcp->pc_initted) {
206 1.1 ross tsp_bus_io_init(&pcp->pc_iot, pcp);
207 1.1 ross tsp_bus_mem_init(&pcp->pc_memt, pcp);
208 1.3 thorpej
209 1.3 thorpej alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
210 1.3 thorpej alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
211 1.3 thorpej
212 1.3 thorpej alpha_bus_get_window = tsp_bus_get_window;
213 1.1 ross }
214 1.1 ross pcp->pc_mallocsafe = mallocsafe;
215 1.1 ross tsp_pci_init(&pcp->pc_pc, pcp);
216 1.1 ross pcp->pc_initted = 1;
217 1.1 ross return pcp;
218 1.1 ross }
219 1.1 ross
220 1.1 ross static int
221 1.16 dsl tsp_bus_get_window(int type, int window, struct alpha_bus_space_translation *abst)
222 1.3 thorpej {
223 1.3 thorpej struct tsp_config *tsp = &tsp_configuration[tsp_console_hose];
224 1.3 thorpej bus_space_tag_t st;
225 1.4 thorpej int error;
226 1.3 thorpej
227 1.3 thorpej switch (type) {
228 1.3 thorpej case ALPHA_BUS_TYPE_PCI_IO:
229 1.3 thorpej st = &tsp->pc_iot;
230 1.3 thorpej break;
231 1.3 thorpej
232 1.3 thorpej case ALPHA_BUS_TYPE_PCI_MEM:
233 1.3 thorpej st = &tsp->pc_memt;
234 1.3 thorpej break;
235 1.3 thorpej
236 1.3 thorpej default:
237 1.3 thorpej panic("tsp_bus_get_window");
238 1.3 thorpej }
239 1.3 thorpej
240 1.4 thorpej error = alpha_bus_space_get_window(st, window, abst);
241 1.4 thorpej if (error)
242 1.4 thorpej return (error);
243 1.4 thorpej
244 1.4 thorpej abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start);
245 1.4 thorpej abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end);
246 1.4 thorpej
247 1.4 thorpej return (0);
248 1.1 ross }
249