tsc.c revision 1.23
1 /* $NetBSD: tsc.c,v 1.23 2014/02/21 12:23:30 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include "opt_dec_6600.h" 35 36 #include <sys/cdefs.h> 37 38 __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.23 2014/02/21 12:23:30 jdc Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <machine/autoconf.h> 46 #include <machine/rpb.h> 47 #include <machine/sysarch.h> 48 49 #include <dev/isa/isareg.h> 50 #include <dev/isa/isavar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <alpha/pci/tsreg.h> 54 #include <alpha/pci/tsvar.h> 55 56 #ifdef DEC_6600 57 #include <alpha/pci/pci_6600.h> 58 #endif 59 60 #define tsc() { Generate ctags(1) key. } 61 62 static int tscmatch(device_t, cfdata_t, void *); 63 static void tscattach(device_t, device_t, void *); 64 65 CFATTACH_DECL_NEW(tsc, 0, tscmatch, tscattach, NULL, NULL); 66 67 extern struct cfdriver tsc_cd; 68 69 struct tsp_config tsp_configuration[4]; 70 71 static int tscprint(void *, const char *pnp); 72 73 static int tspmatch(device_t, cfdata_t, void *); 74 static void tspattach(device_t, device_t, void *); 75 76 CFATTACH_DECL_NEW(tsp, 0, tspmatch, tspattach, NULL, NULL); 77 78 extern struct cfdriver tsp_cd; 79 80 static int tsp_bus_get_window(int, int, 81 struct alpha_bus_space_translation *); 82 83 static int tsciicprint(void *, const char *pnp); 84 85 static int tsciicmatch(device_t, cfdata_t, void *); 86 static void tsciicattach(device_t, device_t, void *); 87 88 CFATTACH_DECL_NEW(tsciic, sizeof(struct tsciic_softc), tsciicmatch, 89 tsciicattach, NULL, NULL); 90 91 extern struct cfdriver tsciic_cd; 92 93 /* There can be only one */ 94 static int tscfound; 95 96 /* Which hose is the display console connected to? */ 97 int tsp_console_hose; 98 99 static int 100 tscmatch(device_t parent, cfdata_t match, void *aux) 101 { 102 struct mainbus_attach_args *ma = aux; 103 104 switch (cputype) { 105 case ST_DEC_6600: 106 case ST_DEC_TITAN: 107 return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound; 108 default: 109 return 0; 110 } 111 } 112 113 static void 114 tscattach(device_t parent, device_t self, void * aux) 115 { 116 int i; 117 int nbus; 118 uint64_t csc, aar; 119 struct tsp_attach_args tsp; 120 struct tsciic_attach_args tsciic; 121 struct mainbus_attach_args *ma = aux; 122 int titan = cputype == ST_DEC_TITAN; 123 124 tscfound = 1; 125 126 csc = LDQP(TS_C_CSC); 127 128 nbus = 1 + (CSC_BC(csc) >= 2); 129 printf(": 2127%c Core Logic Chipset, Cchip rev %d\n" 130 "%s%d: %c Dchips, %d memory bus%s of %d bytes\n", 131 titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)), 132 ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)], 133 nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0)); 134 printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot); 135 for (i = 0; i < 4; ++i) { 136 aar = LDQP(TS_C_AAR0 + i * TS_STEP); 137 printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf, 138 aar & AAR_SPLIT ? " (split)" : ""); 139 } 140 printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf); 141 142 memset(&tsp, 0, sizeof tsp); 143 tsp.tsp_name = "tsp"; 144 tsp.tsp_slot = 0; 145 146 config_found(self, &tsp, tscprint); 147 if (titan) { 148 tsp.tsp_slot += 2; 149 config_found(self, &tsp, tscprint); 150 } 151 152 if (csc & CSC_P1P) { 153 tsp.tsp_slot = 1; 154 config_found(self, &tsp, tscprint); 155 if (titan) { 156 tsp.tsp_slot += 2; 157 config_found(self, &tsp, tscprint); 158 } 159 } 160 161 memset(&tsciic, 0, sizeof tsciic); 162 tsciic.tsciic_name = "tsciic"; 163 164 config_found(self, &tsciic, tsciicprint); 165 } 166 167 static int 168 tscprint(void *aux, const char *p) 169 { 170 struct tsp_attach_args *tsp = aux; 171 172 if (p) 173 aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p); 174 return UNCONF; 175 } 176 177 static int 178 tsciicprint(void *aux, const char *p) 179 { 180 struct tsciic_attach_args *tsciic = aux; 181 182 if (p) 183 aprint_normal("%s at %s\n", tsciic->tsciic_name, p); 184 else 185 aprint_normal("\n"); 186 return UNCONF; 187 } 188 189 #define tsp() { Generate ctags(1) key. } 190 191 static int 192 tspmatch(device_t parent, cfdata_t match, void *aux) 193 { 194 struct tsp_attach_args *t = aux; 195 196 switch (cputype) { 197 case ST_DEC_6600: 198 case ST_DEC_TITAN: 199 return strcmp(t->tsp_name, tsp_cd.cd_name) == 0; 200 default: 201 return 0; 202 } 203 } 204 205 static void 206 tspattach(device_t parent, device_t self, void *aux) 207 { 208 struct pcibus_attach_args pba; 209 struct tsp_attach_args *t = aux; 210 struct tsp_config *pcp; 211 212 printf("\n"); 213 pcp = tsp_init(1, t->tsp_slot); 214 215 tsp_dma_init(pcp); 216 217 /* 218 * Do PCI memory initialization that needs to be deferred until 219 * malloc is safe. On the Tsunami, we need to do this after 220 * DMA is initialized, as well. 221 */ 222 tsp_bus_mem_init2(&pcp->pc_memt, pcp); 223 224 pci_6600_pickintr(pcp); 225 226 pba.pba_iot = &pcp->pc_iot; 227 pba.pba_memt = &pcp->pc_memt; 228 pba.pba_dmat = 229 alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI); 230 pba.pba_dmat64 = NULL; 231 pba.pba_pc = &pcp->pc_pc; 232 pba.pba_bus = 0; 233 pba.pba_bridgetag = NULL; 234 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 235 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 236 config_found_ia(self, "pcibus", &pba, pcibusprint); 237 } 238 239 struct tsp_config * 240 tsp_init(int mallocsafe, int n) 241 /* n: Pchip number */ 242 { 243 struct tsp_config *pcp; 244 int titan = cputype == ST_DEC_TITAN; 245 246 KASSERT(n >= 0 && n < __arraycount(tsp_configuration)); 247 pcp = &tsp_configuration[n]; 248 pcp->pc_pslot = n; 249 pcp->pc_iobase = TS_Pn(n, 0); 250 pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE)); 251 if (n & 2) { 252 /* `A' port of PA Chip */ 253 pcp->pc_csr++; 254 } 255 if (titan) { 256 /* same address on G and A ports */ 257 pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r; 258 } else { 259 pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r; 260 } 261 262 if (!pcp->pc_initted) { 263 tsp_bus_io_init(&pcp->pc_iot, pcp); 264 tsp_bus_mem_init(&pcp->pc_memt, pcp); 265 266 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 267 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 268 269 alpha_bus_get_window = tsp_bus_get_window; 270 } 271 pcp->pc_mallocsafe = mallocsafe; 272 tsp_pci_init(&pcp->pc_pc, pcp); 273 pcp->pc_initted = 1; 274 return pcp; 275 } 276 277 static int 278 tsp_bus_get_window(int type, int window, 279 struct alpha_bus_space_translation *abst) 280 { 281 struct tsp_config *tsp = &tsp_configuration[tsp_console_hose]; 282 bus_space_tag_t st; 283 int error; 284 285 switch (type) { 286 case ALPHA_BUS_TYPE_PCI_IO: 287 st = &tsp->pc_iot; 288 break; 289 290 case ALPHA_BUS_TYPE_PCI_MEM: 291 st = &tsp->pc_memt; 292 break; 293 294 default: 295 panic("tsp_bus_get_window"); 296 } 297 298 error = alpha_bus_space_get_window(st, window, abst); 299 if (error) 300 return error; 301 302 abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start); 303 abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end); 304 305 return 0; 306 } 307 308 #define tsciic() { Generate ctags(1) key. } 309 310 static int 311 tsciicmatch(device_t parent, cfdata_t match, void *aux) 312 { 313 struct tsciic_attach_args *t = aux; 314 315 switch (cputype) { 316 case ST_DEC_6600: 317 case ST_DEC_TITAN: 318 return strcmp(t->tsciic_name, tsciic_cd.cd_name) == 0; 319 default: 320 return 0; 321 } 322 } 323 324 static void 325 tsciicattach(device_t parent, device_t self, void *aux) 326 { 327 tsciic_init(self); 328 } 329 330 void 331 tsc_print_dir(unsigned int indent, unsigned long dir) 332 { 333 char buf[60]; 334 335 snprintb(buf, 60, 336 "\177\20" 337 "b\77Internal Cchip asynchronous error\0" 338 "b\76Pchip 0 error\0" 339 "b\75Pchip 1 error\0" 340 "b\74Pchip 2 error\0" 341 "b\73Pchip 3 error\0", 342 dir); 343 IPRINTF(indent, "DIR = %s\n", buf); 344 } 345 346 void 347 tsc_print_misc(unsigned int indent, unsigned long misc) 348 { 349 unsigned long tmp = MISC_NXM_SRC(misc); 350 351 if (!MISC_NXM(misc)) 352 return; 353 354 IPRINTF(indent, "NXM address detected\n"); 355 IPRINTF(indent, "NXM source = %s %lu\n", 356 tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4); 357 } 358
Indexes created Thu Sep 25 16:09:42 GMT 2025