tsc.c revision 1.27
1 /* $NetBSD: tsc.c,v 1.27 2021/06/19 16:59:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.27 2021/06/19 16:59:07 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #include <machine/autoconf.h> 44 #include <machine/rpb.h> 45 #include <machine/sysarch.h> 46 47 #include <dev/isa/isareg.h> 48 #include <dev/isa/isavar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <alpha/pci/tsreg.h> 52 #include <alpha/pci/tsvar.h> 53 54 #include "tsciic.h" 55 56 #define tsc() { Generate ctags(1) key. } 57 58 static int tscmatch(device_t, cfdata_t, void *); 59 static void tscattach(device_t, device_t, void *); 60 61 CFATTACH_DECL_NEW(tsc, 0, tscmatch, tscattach, NULL, NULL); 62 63 extern struct cfdriver tsc_cd; 64 65 struct tsp_config tsp_configuration[4]; 66 67 static int tscprint(void *, const char *pnp); 68 69 static int tspmatch(device_t, cfdata_t, void *); 70 static void tspattach(device_t, device_t, void *); 71 72 CFATTACH_DECL_NEW(tsp, 0, tspmatch, tspattach, NULL, NULL); 73 74 extern struct cfdriver tsp_cd; 75 76 static int tsp_bus_get_window(int, int, 77 struct alpha_bus_space_translation *); 78 79 static int tsciicprint(void *, const char *pnp); 80 81 static int tsciicmatch(device_t, cfdata_t, void *); 82 static void tsciicattach(device_t, device_t, void *); 83 84 CFATTACH_DECL_NEW(tsciic, sizeof(struct tsciic_softc), tsciicmatch, 85 tsciicattach, NULL, NULL); 86 87 #if NTSCIIC 88 extern struct cfdriver tsciic_cd; 89 #endif 90 91 /* There can be only one */ 92 static int tscfound; 93 94 /* Which hose is the display console connected to? */ 95 int tsp_console_hose; 96 97 static int 98 tscmatch(device_t parent, cfdata_t match, void *aux) 99 { 100 struct mainbus_attach_args *ma = aux; 101 102 switch (cputype) { 103 case ST_DEC_6600: 104 case ST_DEC_TITAN: 105 return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound; 106 default: 107 return 0; 108 } 109 } 110 111 static void 112 tscattach(device_t parent, device_t self, void * aux) 113 { 114 int i; 115 int nbus; 116 uint64_t csc, aar; 117 struct tsp_attach_args tsp; 118 struct tsciic_attach_args tsciic; 119 struct mainbus_attach_args *ma = aux; 120 int titan = cputype == ST_DEC_TITAN; 121 122 tscfound = 1; 123 124 csc = LDQP(TS_C_CSC); 125 126 nbus = 1 + (CSC_BC(csc) >= 2); 127 printf(": 2127%c Core Logic Chipset, Cchip rev %d\n" 128 "%s%d: %c Dchips, %d memory bus%s of %d bytes\n", 129 titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)), 130 ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)], 131 nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0)); 132 printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot); 133 for (i = 0; i < 4; ++i) { 134 aar = LDQP(TS_C_AAR0 + i * TS_STEP); 135 printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf, 136 aar & AAR_SPLIT ? " (split)" : ""); 137 } 138 printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf); 139 140 memset(&tsp, 0, sizeof tsp); 141 tsp.tsp_name = "tsp"; 142 tsp.tsp_slot = 0; 143 144 config_found(self, &tsp, tscprint, CFARG_EOL); 145 if (titan) { 146 tsp.tsp_slot += 2; 147 config_found(self, &tsp, tscprint, CFARG_EOL); 148 } 149 150 if (csc & CSC_P1P) { 151 tsp.tsp_slot = 1; 152 config_found(self, &tsp, tscprint, CFARG_EOL); 153 if (titan) { 154 tsp.tsp_slot += 2; 155 config_found(self, &tsp, tscprint, CFARG_EOL); 156 } 157 } 158 159 memset(&tsciic, 0, sizeof tsciic); 160 tsciic.tsciic_name = "tsciic"; 161 162 config_found(self, &tsciic, tsciicprint, CFARG_EOL); 163 } 164 165 static int 166 tscprint(void *aux, const char *p) 167 { 168 struct tsp_attach_args *tsp = aux; 169 170 if (p) 171 aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p); 172 return UNCONF; 173 } 174 175 static int 176 tsciicprint(void *aux, const char *p) 177 { 178 struct tsciic_attach_args *tsciic = aux; 179 180 if (p) 181 aprint_normal("%s at %s\n", tsciic->tsciic_name, p); 182 else 183 aprint_normal("\n"); 184 return UNCONF; 185 } 186 187 #define tsp() { Generate ctags(1) key. } 188 189 static int 190 tspmatch(device_t parent, cfdata_t match, void *aux) 191 { 192 struct tsp_attach_args *t = aux; 193 194 switch (cputype) { 195 case ST_DEC_6600: 196 case ST_DEC_TITAN: 197 return strcmp(t->tsp_name, tsp_cd.cd_name) == 0; 198 default: 199 return 0; 200 } 201 } 202 203 static void 204 tspattach(device_t parent, device_t self, void *aux) 205 { 206 struct pcibus_attach_args pba; 207 struct tsp_attach_args *t = aux; 208 struct tsp_config *pcp; 209 210 printf("\n"); 211 pcp = tsp_init(1, t->tsp_slot); 212 213 tsp_dma_init(pcp); 214 215 /* 216 * Do PCI memory initialization that needs to be deferred until 217 * malloc is safe. On the Tsunami, we need to do this after 218 * DMA is initialized, as well. 219 */ 220 tsp_bus_mem_init2(&pcp->pc_memt, pcp); 221 222 alpha_pci_intr_init(pcp, &pcp->pc_iot, &pcp->pc_memt, &pcp->pc_pc); 223 224 pba.pba_iot = &pcp->pc_iot; 225 pba.pba_memt = &pcp->pc_memt; 226 pba.pba_dmat = 227 alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI); 228 pba.pba_dmat64 = &pcp->pc_dmat64_direct; 229 pba.pba_pc = &pcp->pc_pc; 230 pba.pba_bus = 0; 231 pba.pba_bridgetag = NULL; 232 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 233 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 234 config_found(self, &pba, pcibusprint, CFARG_EOL); 235 } 236 237 struct tsp_config * 238 tsp_init(int mallocsafe, int n) 239 /* n: Pchip number */ 240 { 241 struct tsp_config *pcp; 242 int titan = cputype == ST_DEC_TITAN; 243 244 KASSERT(n >= 0 && n < __arraycount(tsp_configuration)); 245 pcp = &tsp_configuration[n]; 246 pcp->pc_pslot = n; 247 pcp->pc_iobase = TS_Pn(n, 0); 248 pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE)); 249 if (n & 2) { 250 /* `A' port of PA Chip */ 251 pcp->pc_csr++; 252 } 253 if (titan) { 254 /* same address on G and A ports */ 255 pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r; 256 } else { 257 pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r; 258 } 259 260 if (!pcp->pc_initted) { 261 tsp_bus_io_init(&pcp->pc_iot, pcp); 262 tsp_bus_mem_init(&pcp->pc_memt, pcp); 263 264 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 265 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 266 267 alpha_bus_get_window = tsp_bus_get_window; 268 } 269 pcp->pc_mallocsafe = mallocsafe; 270 tsp_pci_init(&pcp->pc_pc, pcp); 271 pcp->pc_initted = 1; 272 return pcp; 273 } 274 275 static int 276 tsp_bus_get_window(int type, int window, 277 struct alpha_bus_space_translation *abst) 278 { 279 struct tsp_config *tsp = &tsp_configuration[tsp_console_hose]; 280 bus_space_tag_t st; 281 int error; 282 283 switch (type) { 284 case ALPHA_BUS_TYPE_PCI_IO: 285 st = &tsp->pc_iot; 286 break; 287 288 case ALPHA_BUS_TYPE_PCI_MEM: 289 st = &tsp->pc_memt; 290 break; 291 292 default: 293 panic("tsp_bus_get_window"); 294 } 295 296 error = alpha_bus_space_get_window(st, window, abst); 297 if (error) 298 return error; 299 300 abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start); 301 abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end); 302 303 return 0; 304 } 305 306 #define tsciic() { Generate ctags(1) key. } 307 308 static int 309 tsciicmatch(device_t parent, cfdata_t match, void *aux) 310 { 311 #if NTSCIIC 312 struct tsciic_attach_args *t = aux; 313 #endif 314 315 switch (cputype) { 316 case ST_DEC_6600: 317 case ST_DEC_TITAN: 318 #if NTSCIIC 319 return strcmp(t->tsciic_name, tsciic_cd.cd_name) == 0; 320 #endif 321 default: 322 return 0; 323 } 324 } 325 326 static void 327 tsciicattach(device_t parent, device_t self, void *aux) 328 { 329 #if NTSCIIC 330 tsciic_init(self); 331 #endif 332 } 333 334 void 335 tsc_print_dir(unsigned int indent, unsigned long dir) 336 { 337 char buf[60]; 338 339 snprintb(buf, 60, 340 "\177\20" 341 "b\77Internal Cchip asynchronous error\0" 342 "b\76Pchip 0 error\0" 343 "b\75Pchip 1 error\0" 344 "b\74Pchip 2 error\0" 345 "b\73Pchip 3 error\0", 346 dir); 347 IPRINTF(indent, "DIR = %s\n", buf); 348 } 349 350 void 351 tsc_print_misc(unsigned int indent, unsigned long misc) 352 { 353 unsigned long tmp = MISC_NXM_SRC(misc); 354 355 if (!MISC_NXM(misc)) 356 return; 357 358 IPRINTF(indent, "NXM address detected\n"); 359 IPRINTF(indent, "NXM source = %s %lu\n", 360 tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4); 361 } 362
Indexes created Fri Sep 26 20:09:58 GMT 2025