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tsreg.h revision 1.1 
      1 /* $NetBSD: tsreg.h,v 1.1 1999/06/29 06:46:47 ross Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Ross Harvey.
     17  * 4. The name of Ross Harvey may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
     21  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     22  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
     23  * ARE DISCLAIMED.  IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
     24  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     30  * SUCH DAMAGE.
     31  *
     32  */
     33 
     34 /*
     35  * 21272 Core Logic registers and constants.
     36  */
     37 
     38 #define	tsreg() { Generate ctags(1) key. }
     39 
     40 /*
     41  * Superpage pointer from physical address.
     42  */
     43 #define	S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
     44 
     45 /*
     46  * {LD,ST}QP: LoaD and STore Quad Physical
     47  */
     48 #define	LDQP(a)	(*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
     49 #define	STQP(a) LDQP(a)
     50 
     51 /*
     52  * Define extraction functions for bit fields via length and left,right bitno
     53  */
     54 #define	TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
     55 #define	TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
     56 
     57 /*
     58  * EV6 has a new superpage which can pass through 44 address bits.  (Umm, a
     59  * superduperpage?) But, the firmware doesn't turn it on, so we use the old
     60  * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
     61  * the needed I/O space access. This is just as well; it means we don't have
     62  * to worry about which GENERIC code might get called on other CPU models.
     63  *
     64  *	E.g., we want this:	      0x0801##a000##0000
     65  *	We use this:		      0x0101##a000##0000
     66  *	...mix in the old SP:	0xffff##fc00##0000##0000
     67  *	...after PA sign ext:	0xffff##ff00##a000##0000
     68  *	(PA<42:41> ignored)
     69  */
     70 
     71 /*
     72  * Cchip CSR Map
     73  */
     74 
     75 #define TS_C_CSC	0x101##a000##0000UL	/* Cchip System Configuration */
     76 
     77 #	define	CSC_P1P		(1L << 14)
     78 #	define	CSC_BC(r)	TSFIELD((r), 0, 2)
     79 #	define	CSC_AW		(1L << 8)
     80 
     81 #define TS_C_MTR	0x101##a000##0040UL
     82 
     83 #define TS_C_MISC	0x101##a000##0080UL	/* Miscellaneous Register */
     84 
     85 #	define	MISC_REV(r)	TSFIELD((r), 39, 8)
     86 
     87 #define TS_C_MPD	0x101##a000##00c0UL
     88 
     89 #define TS_C_AAR0	0x101##a000##0100UL
     90 #define TS_C_AAR1	0x101##a000##0140UL
     91 #define TS_C_AAR2	0x101##a000##0180UL
     92 #define TS_C_AAR3	0x101##a000##01c0UL
     93 
     94 #	define	AAR_ASIZ(r)	TSFIELD((r), 12, 4)
     95 #	define	AAR_SPLIT	(1L << 8)
     96 
     97 #define TS_C_DIM0	0x101##a000##0200UL
     98 #define TS_C_DIM1	0x101##a000##0240UL
     99 #define TS_C_DIR0	0x101##a000##0280UL
    100 #define TS_C_DIR1	0x101##a000##02c0UL
    101 #define TS_C_DRIR	0x101##a000##0300UL
    102 #define TS_C_PRBEN	0x101##a000##0340UL
    103 #define TS_C_IIC0	0x101##a000##0380UL
    104 #define TS_C_IIC1	0x101##a000##03c0UL
    105 #define TS_C_MPR0	0x101##a000##0400UL
    106 #define TS_C_MPR1	0x101##a000##0440UL
    107 #define TS_C_MPR2	0x101##a000##0480UL
    108 #define TS_C_MPR3	0x101##a000##04c0UL
    109 #define TS_C_MCTL	0x101##a000##0500UL
    110 
    111 #define TS_C_TTR	0x101##a000##0580UL
    112 #define TS_C_TDR	0x101##a000##05c0UL
    113 
    114 /*
    115  * Dchip CSR Map
    116  */
    117 
    118 #define TS_D_DSC	0x101##b000##0800UL
    119 #define TS_D_STR	0x101##b000##0840UL
    120 #define TS_D_DREV	0x101##b000##0880UL
    121 #define TS_D_DSC2	0x101##b000##08c0UL
    122 
    123 /*
    124  * Pchip CSR Offsets
    125  */
    126 
    127 #define P_WSBA0		0x0000
    128 #define P_WSBA1		0x0040
    129 #define P_WSBA2		0x0080
    130 #define P_WSBA3		0x00c0
    131 
    132 #	define	WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
    133 #	define	WSBA_SG	     2
    134 #	define	WSBA_ENA     1
    135 
    136 #define P_WSM0		0x0100
    137 #define P_WSM1		0x0140
    138 #define P_WSM2		0x0180
    139 #define P_WSM3		0x01c0
    140 
    141 #	define	WSM_AM(r)    TSFIELDBB((r), 31, 20)
    142 #	define	WSM_LEN(r)   ((WSM_AM(r) + 1) << 20)
    143 
    144 #define P_TBA0		0x0200
    145 #define P_TBA1		0x0240
    146 #define P_TBA2		0x0280
    147 #define P_TBA3		0x02c0
    148 
    149 #define P_PCTL		0x0300
    150 #define P_PLAT		0x0340
    151 	/* reserved	0x0380 */
    152 #define P_PERROR	0x03c0
    153 
    154 #define P_PERRMASK	0x0400
    155 #define P_PERRSET	0x0440
    156 #define P_TLBIV		0x0480
    157 #define P_TLBIA		0x04c0
    158 
    159 #define P_PMONCTL	0x0500
    160 #define P_PMONCNT	0x0540
    161 
    162 #define P_SPRST		0x0800
    163 
    164 #define	TS_STEP		0x40
    165 
    166 /*
    167  * Pchip I/O offsets
    168  */
    169 
    170 #define	P_CSRBASE	 0x001##8000##0000UL
    171 #define	P_PCI_MEM	 0
    172 #define	P_PCI_IO	 0x001##fc00##0000UL
    173 #define	P_PCI_CONFIG	 0x001##fe00##0000UL
    174 
    175 /*
    176  * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
    177  */
    178 
    179 #define	TS_P0(offs)	(0x100##0000##0000UL + (offs))
    180 #define	TS_P1(offs)	(0x102##0000##0000UL + (offs))
    181 #define	TS_Pn(n, offs)	(0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
    182 
    183 /*
    184  * Tsunami Generic Register Type
    185  */
    186 typedef struct _ts_gr {
    187 	volatile u_int64_t tsg_r;
    188 	long	tsg_deadspace[7];
    189 } TS_GR;
    190 
    191 /*
    192  * Tsunami Pchip
    193  */
    194 struct	ts_pchip {
    195 	TS_GR	tsp_wsba[4];	/* Window Space Base Address */
    196 
    197 	TS_GR	tsp_wsm[4];	/* Window Space Mask */
    198 
    199 	TS_GR	tsp_tba[4];	/* Translated Base Address */
    200 
    201 	TS_GR	tsp_pctl;	/* Pchip Control */
    202 	TS_GR	tsp_plat;	/* Pchip Latency */
    203 	TS_GR	tsp_resA;
    204 	TS_GR	tsp_error;	/* Pchip Error */
    205 
    206 	TS_GR	tsp_perrmask;	/* Pchip Error Mask */
    207 	TS_GR	tsp_perrset;	/* Pchip Error Set */
    208 	TS_GR	tsp_tlbiv;	/* Translation Buffer Invalidate Virtual */
    209 	TS_GR	tsp_tlbia;	/* Translation Buffer Invalidate All */
    210 
    211 	TS_GR	tsp_pmonctl;	/* PChip Monitor Control */
    212 	TS_GR	tsp_pmoncnt;	/* PChip Monitor Counters */
    213 	TS_GR	tsp_resB;
    214 	TS_GR	tsp_resC;
    215 
    216 	TS_GR	tsp_resD_K[8];
    217 
    218 	TS_GR	tsp_sprts;	/* ??? */
    219 };
    220