tsreg.h revision 1.8.6.1
1 /* $NetBSD: tsreg.h,v 1.8.6.1 2021/06/17 04:46:17 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 /* 35 * 21272 Core Logic registers and constants. 36 */ 37 38 #define tsreg() { Generate ctags(1) key. } 39 40 /* 41 * Superpage pointer from physical address. 42 */ 43 #define S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys)) 44 45 /* 46 * {LD,ST}QP: LoaD and STore Quad Physical 47 */ 48 #define LDQP(a) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(a)) 49 #define STQP(a) LDQP(a) 50 51 /* 52 * Define extraction functions for bit fields via length and left,right bitno 53 */ 54 #define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len)))) 55 #define TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1) 56 57 /* 58 * EV6 has a new superpage which can pass through 44 address bits. (Umm, a 59 * superduperpage?) But, the firmware doesn't turn it on, so we use the old 60 * one and let the HW sign extend va/pa<40> to get us the pa<43> that makes 61 * the needed I/O space access. This is just as well; it means we don't have 62 * to worry about which GENERIC code might get called on other CPU models. 63 * 64 * E.g., we want this: 0x0801##a000##0000 65 * We use this: 0x0101##a000##0000 66 * ...mix in the old SP: 0xffff##fc00##0000##0000 67 * ...after PA sign ext: 0xffff##ff00##a000##0000 68 * (PA<42:41> ignored) 69 */ 70 71 /* 72 * This hack allows us to map the I/O address space without using 73 * the KSEG sign extension hack. 74 */ 75 #define TS_PHYSADDR(x) \ 76 (((x) & ~0x0100##0000##0000) | 0x0800##0000##0000) 77 78 /* 79 * Cchip CSR Map 80 */ 81 82 #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */ 83 84 # define CSC_P1P (1L << 14) 85 # define CSC_BC(r) TSFIELD((r), 0, 2) 86 # define CSC_AW (1L << 8) 87 88 #define TS_C_MTR 0x101##a000##0040UL 89 90 #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */ 91 92 # define MISC_NXM(r) TSFIELD((r), 28, 1) 93 # define MISC_NXM_SRC(r) TSFIELD((r), 29, 3) 94 # define MISC_REV(r) TSFIELD((r), 39, 8) 95 96 #define TS_C_MPD 0x101##a000##00c0UL 97 98 # define MPD_DR 0x08 /* RO: Data receive */ 99 # define MPD_CKR 0x04 /* RO: Clock receive */ 100 # define MPD_DS 0x02 /* WO: Data send - Must be a 1 to receive */ 101 # define MPD_CKS 0x01 /* WO: Clock send */ 102 103 #define TS_C_AAR0 0x101##a000##0100UL 104 #define TS_C_AAR1 0x101##a000##0140UL 105 #define TS_C_AAR2 0x101##a000##0180UL 106 #define TS_C_AAR3 0x101##a000##01c0UL 107 108 # define AAR_ASIZ(r) TSFIELD((r), 12, 4) 109 # define AAR_SPLIT (1L << 8) 110 111 #define TS_C_DIM0 0x101##a000##0200UL 112 #define TS_C_DIM1 0x101##a000##0240UL 113 #define TS_C_DIR0 0x101##a000##0280UL 114 #define TS_C_DIR1 0x101##a000##02c0UL 115 #define TS_C_DRIR 0x101##a000##0300UL 116 #define TS_C_PRBEN 0x101##a000##0340UL 117 #define TS_C_IIC0 0x101##a000##0380UL 118 #define TS_C_IIC1 0x101##a000##03c0UL 119 #define TS_C_MPR0 0x101##a000##0400UL 120 #define TS_C_MPR1 0x101##a000##0440UL 121 #define TS_C_MPR2 0x101##a000##0480UL 122 #define TS_C_MPR3 0x101##a000##04c0UL 123 #define TS_C_MCTL 0x101##a000##0500UL 124 125 #define TS_C_TTR 0x101##a000##0580UL 126 #define TS_C_TDR 0x101##a000##05c0UL 127 #define TS_C_DIM2 0x101##a000##0600UL 128 #define TS_C_DIM3 0x101##a000##0640UL 129 #define TS_C_DIR2 0x101##a000##0680UL 130 #define TS_C_DIR3 0x101##a000##06c0UL 131 #define TS_C_IIC2 0x101##a000##0700UL 132 #define TS_C_IIC3 0x101##a000##0740UL 133 134 /* 135 * Dchip CSR Map 136 */ 137 138 #define TS_D_DSC 0x101##b000##0800UL 139 #define TS_D_STR 0x101##b000##0840UL 140 #define TS_D_DREV 0x101##b000##0880UL 141 #define TS_D_DSC2 0x101##b000##08c0UL 142 143 /* 144 * Pchip CSR Offsets 145 */ 146 147 #define P_WSBA0 0x0000 148 #define P_WSBA1 0x0040 149 #define P_WSBA2 0x0080 150 #define P_WSBA3 0x00c0 151 152 # define WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20) 153 # define WSBA_SG 2 154 # define WSBA_ENA 1 155 156 #define P_WSM0 0x0100 157 #define P_WSM1 0x0140 158 #define P_WSM2 0x0180 159 #define P_WSM3 0x01c0 160 161 # define WSM_AM(r) TSFIELDBB((r), 31, 20) 162 # define WSM_LEN(r) ((WSM_AM(r) + 1) << 20) 163 164 #define P_TBA0 0x0200 165 #define P_TBA1 0x0240 166 #define P_TBA2 0x0280 167 #define P_TBA3 0x02c0 168 169 #define P_PCTL 0x0300 170 171 #define PCTL_FDSC __BIT(0) /* fast discard enable */ 172 #define PCTL_FBTB __BIT(1) /* fast back-to-back enable */ 173 #define PCTL_THDIS __BIT(2) /* disable TLB anti-thrash (debug) */ 174 #define PCTL_CHAINDIS __BIT(3) /* disable chaining */ 175 #define PCTL_TGTLAT __BIT(4) /* target latency timers enable */ 176 #define PCTL_HOLE __BIT(5) /* 512KB->1M hole enable */ 177 #define PCTL_MWIN __BIT(6) /* monster window enable */ 178 #define PCTL_PRIGRP __BITS(8,14) /* arbiter priority group */ 179 #define PCTL_PPRI __BIT(15) /* arbiter priority group for Pchip */ 180 #define PCTL_ECCEN __BIT(18) /* ECC enable for DMA and SGTE */ 181 #define PCTL_PADM __BIT(19) /* PADbus mode */ 182 #define PCTL_CDQMAX __BITS(20,23) /* see manual */ 183 #define PCTL_REV __BITS(24,31) /* Pchip revision */ 184 #define PCTL_CRQMAX __BITS(32,35) /* see manual */ 185 #define PCTL_PTPMAX __BITS(36,39) /* see manual */ 186 #define PCTL_PCLKX __BITS(40,41) /* PCI clock freq multipler */ 187 #define PCTL_FDSDIS __BIT(42) /* fast DMA start and SGTE disable */ 188 #define PCTL_FDWDIS __BIT(43) /* fast DMA read cache block disable */ 189 #define PCTL_PTEVRFY __BIT(44) /* PTE verify for DMA read */ 190 #define PCTL_RPP __BIT(45) /* remote Pchip present */ 191 #define PCTL_PID __BITS(46,47) /* Pchip ID */ 192 193 #define P_PLAT 0x0340 194 /* reserved 0x0380 */ 195 #define P_PERROR 0x03c0 196 197 # define PER_ERR(r) TSFIELD((r), 0, 12) 198 # define PER_ECC(r) TSFIELD((r), 10, 2) 199 # define PER_SADR(r) TSFIELD((r), 16, 34) 200 # define PER_PADR(r) (TSFIELD((r), 18, 32) << 2) 201 # define PER_TRNS(r) TSFIELD((r), 16, 2) 202 # define PER_INV(r) TSFIELD((r), 51, 1) 203 # define PER_CMD(r) TSFIELD((r), 52, 4) 204 # define PER_SYN(r) TSFIELD((r), 56, 8) 205 206 #define P_PERRMASK 0x0400 207 #define P_PERRSET 0x0440 208 #define P_TLBIV 0x0480 209 #define P_TLBIA 0x04c0 210 211 #define P_PMONCTL 0x0500 212 #define P_PMONCNT 0x0540 213 214 #define P_SPRST 0x0800 215 216 #define TS_STEP 0x40 217 218 /* 219 * Pchip I/O offsets 220 */ 221 222 #define P_CSRBASE 0x001##8000##0000UL 223 #define P_PCI_MEM 0x800##0000##0000UL 224 #define P_PCI_IO 0x001##fc00##0000UL 225 #define P_PCI_CONFIG 0x001##fe00##0000UL 226 227 /* 228 * Construct EV6 I/O Space Address for Pchip 0 and Pchip 1. 229 */ 230 231 #define TS_P0(offs) (0x100##0000##0000UL + (offs)) 232 #define TS_P1(offs) (0x102##0000##0000UL + (offs)) 233 #define TS_Pn(n, offs) (0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs)) 234 235 /* 236 * Tsunami Generic Register Type 237 */ 238 typedef struct _ts_gr { 239 volatile uint64_t tsg_r; 240 long tsg_deadspace[7]; 241 } TS_GR; 242 243 /* 244 * Tsunami Pchip 245 */ 246 struct ts_pport { 247 TS_GR tsp_resA; 248 TS_GR tsp_error; /* Pchip Error */ 249 250 TS_GR tsp_perrmask; /* Pchip Error Mask */ 251 TS_GR tsp_perrset; /* Pchip Error Set */ 252 TS_GR tsp_tlbiv; /* Translation Buffer Invalidate Virtual */ 253 TS_GR tsp_tlbia; /* Translation Buffer Invalidate All */ 254 255 TS_GR tsp_pmonctl; /* PChip Monitor Control */ 256 TS_GR tsp_pmoncnt; /* PChip Monitor Counters */ 257 TS_GR tsp_resB; 258 TS_GR tsp_resC; 259 260 TS_GR tsp_resD_K[8]; 261 }; 262 263 struct ts_gport { 264 TS_GR tsp_resA[2]; 265 TS_GR tsp_serror; 266 TS_GR tsp_serrmask; 267 TS_GR tsp_serrset; 268 TS_GR tsp_resB; 269 TS_GR tsp_gperrmask; 270 TS_GR tsp_gperren; 271 TS_GR tsp_gperrset; 272 TS_GR tsp_resC; 273 TS_GR tsp_tlbiv; 274 TS_GR tsp_tlbia; 275 TS_GR tsp_resD[2]; 276 TS_GR tsp_sctl; 277 TS_GR tsp_resE[3]; 278 }; 279 280 struct ts_aport { 281 TS_GR tsp_resA[2]; 282 TS_GR tsp_agperror; 283 TS_GR tsp_agperrmask; 284 TS_GR tsp_agperrset; 285 TS_GR tsp_agplastwr; 286 TS_GR tsp_aperror; 287 TS_GR tsp_aperrmask; 288 TS_GR tsp_aperrset; 289 TS_GR tsp_resB; 290 TS_GR tsp_tlbiv; 291 TS_GR tsp_tlbia; 292 TS_GR tsp_resC[6]; 293 }; 294 295 struct ts_pchip { 296 TS_GR tsp_wsba[4]; /* Window Space Base Address */ 297 298 TS_GR tsp_wsm[4]; /* Window Space Mask */ 299 300 TS_GR tsp_tba[4]; /* Translated Base Address */ 301 302 TS_GR tsp_pctl; /* Pchip Control */ 303 TS_GR tsp_plat; /* Pchip Latency */ 304 305 union { 306 struct ts_pport p; 307 struct ts_gport g; 308 struct ts_aport a; 309 } port; 310 311 TS_GR tsp_sprts; /* ??? */ 312 TS_GR tsp_res[31]; 313 }; 314
Indexes created Mon Oct 27 20:09:55 GMT 2025