1 1.2 cgd /* $NetBSD: prom_swpal.S,v 1.2 1997/04/06 08:41:01 cgd Exp $ */ 2 1.1 cgd 3 1.1 cgd /* 4 1.1 cgd * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 1.1 cgd * All rights reserved. 6 1.1 cgd * 7 1.1 cgd * Author: Keith Bostic 8 1.1 cgd * 9 1.1 cgd * Permission to use, copy, modify and distribute this software and 10 1.1 cgd * its documentation is hereby granted, provided that both the copyright 11 1.1 cgd * notice and this permission notice appear in all copies of the 12 1.1 cgd * software, derivative works or modified versions, and any portions 13 1.1 cgd * thereof, and that both notices appear in supporting documentation. 14 1.1 cgd * 15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 1.1 cgd * 19 1.1 cgd * Carnegie Mellon requests users of this software to return to 20 1.1 cgd * 21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 1.1 cgd * School of Computer Science 23 1.1 cgd * Carnegie Mellon University 24 1.1 cgd * Pittsburgh PA 15213-3890 25 1.1 cgd * 26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the 27 1.1 cgd * rights to redistribute these changes. 28 1.1 cgd */ 29 1.1 cgd 30 1.1 cgd #include "../../include/asm.h" 31 1.1 cgd #include "../../include/prom.h" 32 1.1 cgd #include "../../include/rpb.h" 33 1.1 cgd 34 1.1 cgd /* Offsets from base of HWRPB. */ 35 1.1 cgd #define RPB_SELFREF 0x00 36 1.1 cgd #define RPB_SLOTSIZE 0x98 37 1.1 cgd #define RPB_PERCPU_OFF 0xA0 38 1.1 cgd 39 1.1 cgd /* Offsets in a boot PCB. */ 40 1.1 cgd #define PCB_KSP 0x00 41 1.1 cgd #define PCB_PTBR 0x10 42 1.1 cgd #define PCB_ASN 0x1c 43 1.1 cgd #define PCB_FEN 0x28 44 1.1 cgd 45 1.1 cgd /* Pal values. */ 46 1.1 cgd #define PAL_RESERVED 0 /* Reserved to Digital. */ 47 1.1 cgd #define PAL_VMS 1 /* VMS */ 48 1.1 cgd #define PAL_OSF 2 /* OSF */ 49 1.1 cgd 50 1.1 cgd /* 51 1.1 cgd * PAL code switch routine. 52 1.1 cgd */ 53 1.1 cgd #define D_RA (7*8) 54 1.1 cgd #define D_S0 (8*8) 55 1.1 cgd #define D_S1 (9*8) 56 1.1 cgd #define D_S2 (10*8) 57 1.1 cgd #define D_S3 (11*8) 58 1.1 cgd #define D_S4 (12*8) 59 1.1 cgd #define D_S5 (13*8) 60 1.1 cgd #define PALSW_FRAME_SIZE (14*8) 61 1.1 cgd #define PALSW_REGS IM_RA|IM_S0|IM_S1|IM_S2|IM_S3|IM_S4|IM_S5 62 1.1 cgd 63 1.1 cgd .comm ptbr_save,8 64 1.1 cgd 65 1.1 cgd .text 66 1.1 cgd .align 4 67 1.1 cgd 68 1.1 cgd NESTED(switch_palcode, 0, PALSW_FRAME_SIZE, ra, PALSW_REGS, 0) 69 1.1 cgd LDGP(pv) 70 1.1 cgd /* ldgp gp, 0(pv)*/ 71 1.1 cgd 72 1.1 cgd lda sp, -PALSW_FRAME_SIZE(sp) 73 1.1 cgd stq ra, D_RA(sp) 74 1.1 cgd stq s0, D_S0(sp) 75 1.1 cgd stq s1, D_S1(sp) 76 1.1 cgd stq s2, D_S2(sp) 77 1.1 cgd stq s3, D_S3(sp) 78 1.1 cgd stq s4, D_S4(sp) 79 1.1 cgd stq s5, D_S5(sp) 80 1.1 cgd 81 1.1 cgd stq pv, 0(sp) 82 1.1 cgd stq gp, 8(sp) 83 1.1 cgd 84 1.1 cgd ldiq s0, HWRPB_ADDR /* s0 HWRPB_ADDR */ 85 1.1 cgd ldq s1, RPB_SLOTSIZE(s0) 86 1.1 cgd call_pal PAL_VMS_mfpr_whami 87 1.1 cgd mulq s1, v0, s1 /* s1 per_cpu offset from base */ 88 1.1 cgd ldq s2, RPB_PERCPU_OFF(s0) 89 1.1 cgd addq s0, s2, s2 90 1.1 cgd addq s2, s1, s2 /* s2 PCB (virtual) */ 91 1.1 cgd 92 1.1 cgd call_pal PAL_VMS_mfpr_ptbr 93 1.1 cgd stq v0, PCB_PTBR(s2) 94 1.1 cgd stq v0, ptbr_save /* save PTBR for the kernel */ 95 1.1 cgd stl zero, PCB_ASN(s2) 96 1.1 cgd stq zero, PCB_FEN(s2) 97 1.1 cgd stq sp, PCB_KSP(s2) 98 1.1 cgd 99 1.1 cgd ldq t0, RPB_SELFREF(s0) /* HWRBP base (physical) */ 100 1.1 cgd ldq t1, RPB_PERCPU_OFF(s0) 101 1.1 cgd addq t0, t1, t0 102 1.1 cgd addq t0, s1, t0 /* PCB base (phys) */ 103 1.1 cgd stq t0, 16(sp) 104 1.1 cgd 105 1.1 cgd call_pal PAL_VMS_mfpr_vptb 106 1.1 cgd mov v0, a3 107 1.1 cgd ldiq a0, PAL_OSF 108 1.1 cgd lda a1, contin 109 1.1 cgd ldq a2, 16(sp) 110 1.1 cgd 111 1.1 cgd call_pal PAL_swppal /* a0, a1, a2, a3 */ 112 1.1 cgd 113 1.1 cgd contin: ldq pv, 0(sp) 114 1.1 cgd ldq gp, 8(sp) 115 1.1 cgd 116 1.1 cgd ldq ra, D_RA(sp) 117 1.1 cgd ldq s0, D_S0(sp) 118 1.1 cgd ldq s1, D_S1(sp) 119 1.1 cgd ldq s2, D_S2(sp) 120 1.1 cgd ldq s3, D_S3(sp) 121 1.1 cgd ldq s4, D_S4(sp) 122 1.1 cgd ldq s5, D_S5(sp) 123 1.1 cgd lda sp, PALSW_FRAME_SIZE(sp) 124 1.1 cgd RET 125 1.1 cgd END(switch_palcode) 126 1.1 cgd 127 1.1 cgd #undef D_RA 128 1.1 cgd #undef D_S0 129 1.1 cgd #undef D_S1 130 1.1 cgd #undef D_S2 131 1.1 cgd #undef D_S3 132 1.1 cgd #undef D_S4 133 1.1 cgd #undef D_S5 134 1.1 cgd #undef PALSW_FRAME_SIZE 135 1.1 cgd #undef PALSW_REGS 136
Indexes created Thu Oct 02 01:09:59 GMT 2025