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ioasic.c revision 1.32.2.1
      1  1.32.2.1   thorpej /* $NetBSD: ioasic.c,v 1.32.2.1 2000/07/18 06:25:25 thorpej Exp $ */
      2      1.17   thorpej 
      3      1.17   thorpej /*-
      4      1.17   thorpej  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
      5      1.17   thorpej  * All rights reserved.
      6      1.17   thorpej  *
      7      1.17   thorpej  * This code is derived from software contributed to The NetBSD Foundation
      8      1.17   thorpej  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9      1.17   thorpej  * NASA Ames Research Center.
     10      1.17   thorpej  *
     11      1.17   thorpej  * Redistribution and use in source and binary forms, with or without
     12      1.17   thorpej  * modification, are permitted provided that the following conditions
     13      1.17   thorpej  * are met:
     14      1.17   thorpej  * 1. Redistributions of source code must retain the above copyright
     15      1.17   thorpej  *    notice, this list of conditions and the following disclaimer.
     16      1.17   thorpej  * 2. Redistributions in binary form must reproduce the above copyright
     17      1.17   thorpej  *    notice, this list of conditions and the following disclaimer in the
     18      1.17   thorpej  *    documentation and/or other materials provided with the distribution.
     19      1.17   thorpej  * 3. All advertising materials mentioning features or use of this software
     20      1.17   thorpej  *    must display the following acknowledgement:
     21      1.17   thorpej  *	This product includes software developed by the NetBSD
     22      1.17   thorpej  *	Foundation, Inc. and its contributors.
     23      1.17   thorpej  * 4. Neither the name of The NetBSD Foundation nor the names of its
     24      1.17   thorpej  *    contributors may be used to endorse or promote products derived
     25      1.17   thorpej  *    from this software without specific prior written permission.
     26      1.17   thorpej  *
     27      1.17   thorpej  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     28      1.17   thorpej  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     29      1.17   thorpej  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     30      1.17   thorpej  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     31      1.17   thorpej  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32      1.17   thorpej  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33      1.17   thorpej  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34      1.17   thorpej  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35      1.17   thorpej  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36      1.17   thorpej  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37      1.17   thorpej  * POSSIBILITY OF SUCH DAMAGE.
     38      1.17   thorpej  */
     39       1.1       cgd 
     40       1.1       cgd /*
     41       1.4       cgd  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
     42       1.1       cgd  * All rights reserved.
     43       1.1       cgd  *
     44       1.1       cgd  * Author: Keith Bostic, Chris G. Demetriou
     45       1.1       cgd  *
     46       1.1       cgd  * Permission to use, copy, modify and distribute this software and
     47       1.1       cgd  * its documentation is hereby granted, provided that both the copyright
     48       1.1       cgd  * notice and this permission notice appear in all copies of the
     49       1.1       cgd  * software, derivative works or modified versions, and any portions
     50       1.1       cgd  * thereof, and that both notices appear in supporting documentation.
     51       1.1       cgd  *
     52       1.1       cgd  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     53       1.1       cgd  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     54       1.1       cgd  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     55       1.1       cgd  *
     56       1.1       cgd  * Carnegie Mellon requests users of this software to return to
     57       1.1       cgd  *
     58       1.1       cgd  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     59       1.1       cgd  *  School of Computer Science
     60       1.1       cgd  *  Carnegie Mellon University
     61       1.1       cgd  *  Pittsburgh PA 15213-3890
     62       1.1       cgd  *
     63       1.1       cgd  * any improvements or extensions that they make and grant Carnegie the
     64       1.1       cgd  * rights to redistribute these changes.
     65       1.1       cgd  */
     66      1.12       cgd 
     67      1.15   thorpej #include "opt_dec_3000_300.h"
     68      1.15   thorpej 
     69      1.13       cgd #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     70      1.13       cgd 
     71  1.32.2.1   thorpej __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.32.2.1 2000/07/18 06:25:25 thorpej Exp $");
     72       1.1       cgd 
     73       1.1       cgd #include <sys/param.h>
     74       1.1       cgd #include <sys/kernel.h>
     75       1.1       cgd #include <sys/systm.h>
     76       1.1       cgd #include <sys/device.h>
     77      1.32   thorpej #include <sys/malloc.h>
     78       1.1       cgd 
     79       1.1       cgd #include <machine/autoconf.h>
     80      1.17   thorpej #include <machine/bus.h>
     81       1.1       cgd #include <machine/pte.h>
     82       1.1       cgd #include <machine/rpb.h>
     83       1.1       cgd 
     84       1.1       cgd #include <dev/tc/tcvar.h>
     85      1.28  nisimura #include <dev/tc/ioasicreg.h>
     86       1.1       cgd #include <dev/tc/ioasicvar.h>
     87       1.1       cgd 
     88       1.1       cgd /* Definition of the driver for autoconfig. */
     89      1.10       cgd int	ioasicmatch __P((struct device *, struct cfdata *, void *));
     90       1.1       cgd void	ioasicattach __P((struct device *, struct device *, void *));
     91       1.2   thorpej 
     92       1.2   thorpej struct cfattach ioasic_ca = {
     93       1.3       cgd 	sizeof(struct ioasic_softc), ioasicmatch, ioasicattach,
     94       1.2   thorpej };
     95       1.1       cgd 
     96       1.1       cgd int	ioasic_intr __P((void *));
     97       1.1       cgd int	ioasic_intrnull __P((void *));
     98       1.1       cgd 
     99       1.1       cgd #define	C(x)	((void *)(x))
    100       1.1       cgd 
    101       1.1       cgd #define	IOASIC_DEV_LANCE	0
    102       1.1       cgd #define	IOASIC_DEV_SCC0		1
    103       1.1       cgd #define	IOASIC_DEV_SCC1		2
    104       1.1       cgd #define	IOASIC_DEV_ISDN		3
    105       1.1       cgd 
    106       1.1       cgd #define	IOASIC_DEV_BOGUS	-1
    107       1.1       cgd 
    108       1.1       cgd #define	IOASIC_NCOOKIES		4
    109       1.1       cgd 
    110      1.21  jonathan struct ioasic_dev ioasic_devs[] = {
    111       1.3       cgd 	/* XXX lance name */
    112      1.19   thorpej 	{ "lance",    IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE),
    113      1.19   thorpej 	  IOASIC_INTR_LANCE, },
    114      1.19   thorpej 	{ "z8530   ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0),
    115      1.19   thorpej 	  IOASIC_INTR_SCC_0, },
    116      1.19   thorpej 	{ "z8530   ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1),
    117      1.19   thorpej 	  IOASIC_INTR_SCC_1, },
    118      1.19   thorpej 	{ "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS),
    119      1.19   thorpej 	  0, },
    120      1.19   thorpej 	{ "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN),
    121      1.30  gmcgarry 	  IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD,  },
    122       1.1       cgd };
    123       1.1       cgd int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
    124       1.1       cgd 
    125       1.1       cgd struct ioasicintr {
    126       1.1       cgd 	int	(*iai_func) __P((void *));
    127       1.1       cgd 	void	*iai_arg;
    128      1.32   thorpej 	struct evcnt iai_evcnt;
    129       1.1       cgd } ioasicintrs[IOASIC_NCOOKIES];
    130       1.1       cgd 
    131       1.1       cgd tc_addr_t ioasic_base;		/* XXX XXX XXX */
    132       1.1       cgd 
    133       1.1       cgd /* There can be only one. */
    134       1.1       cgd int ioasicfound;
    135       1.1       cgd 
    136       1.1       cgd int
    137       1.1       cgd ioasicmatch(parent, cfdata, aux)
    138       1.1       cgd 	struct device *parent;
    139      1.10       cgd 	struct cfdata *cfdata;
    140       1.1       cgd 	void *aux;
    141       1.1       cgd {
    142       1.3       cgd 	struct tc_attach_args *ta = aux;
    143       1.1       cgd 
    144       1.1       cgd 	/* Make sure that we're looking for this type of device. */
    145       1.3       cgd 	if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN))
    146       1.1       cgd 		return (0);
    147       1.1       cgd 
    148       1.1       cgd 	/* Check that it can actually exist. */
    149       1.1       cgd 	if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300))
    150       1.1       cgd 		panic("ioasicmatch: how did we get here?");
    151       1.1       cgd 
    152       1.1       cgd 	if (ioasicfound)
    153       1.1       cgd 		return (0);
    154       1.1       cgd 
    155       1.1       cgd 	return (1);
    156       1.1       cgd }
    157       1.1       cgd 
    158       1.1       cgd void
    159       1.1       cgd ioasicattach(parent, self, aux)
    160       1.1       cgd 	struct device *parent, *self;
    161       1.1       cgd 	void *aux;
    162       1.1       cgd {
    163       1.1       cgd 	struct ioasic_softc *sc = (struct ioasic_softc *)self;
    164       1.3       cgd 	struct tc_attach_args *ta = aux;
    165      1.27       mrg #ifdef DEC_3000_300
    166      1.27       mrg 	u_long ssr;
    167      1.27       mrg #endif
    168      1.27       mrg 	u_long i, imsk;
    169      1.32   thorpej 	const struct evcnt *pevcnt;
    170      1.32   thorpej 	char *cp;
    171       1.1       cgd 
    172       1.1       cgd 	ioasicfound = 1;
    173       1.1       cgd 
    174      1.25  nisimura 	sc->sc_bst = ta->ta_memt;
    175      1.25  nisimura 	if (bus_space_map(ta->ta_memt, ta->ta_addr,
    176      1.25  nisimura 			0x400000, 0, &sc->sc_bsh)) {
    177      1.25  nisimura 		printf("%s: unable to map device\n", sc->sc_dv.dv_xname);
    178      1.25  nisimura 		return;
    179      1.25  nisimura 	}
    180      1.25  nisimura 	sc->sc_dmat = ta->ta_dmat;
    181      1.25  nisimura 
    182      1.25  nisimura 	ioasic_base = sc->sc_base = ta->ta_addr; /* XXX XXX XXX */
    183       1.1       cgd 
    184       1.1       cgd #ifdef DEC_3000_300
    185       1.1       cgd 	if (cputype == ST_DEC_3000_300) {
    186      1.25  nisimura 		ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
    187      1.25  nisimura 		ssr |= IOASIC_CSR_FASTMODE;
    188      1.25  nisimura 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
    189       1.9  christos 		printf(": slow mode\n");
    190       1.1       cgd 	} else
    191       1.1       cgd #endif
    192       1.9  christos 		printf(": fast mode\n");
    193       1.1       cgd 
    194       1.1       cgd 	/*
    195       1.1       cgd 	 * Turn off all device interrupt bits.
    196       1.1       cgd 	 * (This does _not_ include 3000/300 TC option slot bits.
    197       1.1       cgd 	 */
    198      1.25  nisimura 	imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
    199       1.1       cgd 	for (i = 0; i < ioasic_ndevs; i++)
    200      1.25  nisimura 		imsk &= ~ioasic_devs[i].iad_intrbits;
    201      1.25  nisimura 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
    202       1.1       cgd 
    203       1.1       cgd 	/*
    204       1.1       cgd 	 * Set up interrupt handlers.
    205       1.1       cgd 	 */
    206      1.32   thorpej 	pevcnt = tc_intr_evcnt(parent, ta->ta_cookie);
    207       1.1       cgd 	for (i = 0; i < IOASIC_NCOOKIES; i++) {
    208       1.1       cgd 		ioasicintrs[i].iai_func = ioasic_intrnull;
    209       1.1       cgd 		ioasicintrs[i].iai_arg = (void *)i;
    210      1.32   thorpej 
    211      1.32   thorpej 		cp = malloc(12, M_DEVBUF, M_NOWAIT);
    212      1.32   thorpej 		if (cp == NULL)
    213      1.32   thorpej 			panic("ioasicattach");
    214      1.32   thorpej 		sprintf(cp, "slot %lu", i);
    215      1.32   thorpej 		evcnt_attach_dynamic(&ioasicintrs[i].iai_evcnt,
    216      1.32   thorpej 		    EVCNT_TYPE_INTR, pevcnt, self->dv_xname, cp);
    217       1.1       cgd 	}
    218      1.29  nisimura 	tc_intr_establish(parent, ta->ta_cookie, TC_IPL_NONE, ioasic_intr, sc);
    219       1.1       cgd 
    220      1.26  nisimura 	/*
    221       1.1       cgd 	 * Try to configure each device.
    222       1.1       cgd 	 */
    223      1.26  nisimura 	ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs);
    224       1.1       cgd }
    225       1.1       cgd 
    226       1.1       cgd void
    227       1.1       cgd ioasic_intr_establish(ioa, cookie, level, func, arg)
    228       1.1       cgd 	struct device *ioa;
    229       1.1       cgd 	void *cookie, *arg;
    230       1.1       cgd 	tc_intrlevel_t level;
    231       1.1       cgd 	int (*func) __P((void *));
    232       1.1       cgd {
    233      1.25  nisimura 	struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0];
    234      1.25  nisimura 	u_long dev, i, imsk;
    235       1.1       cgd 
    236       1.1       cgd 	dev = (u_long)cookie;
    237       1.1       cgd #ifdef DIAGNOSTIC
    238       1.1       cgd 	/* XXX check cookie. */
    239       1.1       cgd #endif
    240       1.1       cgd 
    241       1.1       cgd 	if (ioasicintrs[dev].iai_func != ioasic_intrnull)
    242      1.20   thorpej 		panic("ioasic_intr_establish: cookie %lu twice", dev);
    243       1.1       cgd 
    244       1.1       cgd 	ioasicintrs[dev].iai_func = func;
    245       1.1       cgd 	ioasicintrs[dev].iai_arg = arg;
    246       1.1       cgd 
    247       1.1       cgd 	/* Enable interrupts for the device. */
    248       1.1       cgd 	for (i = 0; i < ioasic_ndevs; i++)
    249       1.1       cgd 		if (ioasic_devs[i].iad_cookie == cookie)
    250       1.1       cgd 			break;
    251       1.1       cgd 	if (i == ioasic_ndevs)
    252       1.1       cgd 		panic("ioasic_intr_establish: invalid cookie.");
    253      1.25  nisimura 
    254      1.25  nisimura 	imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
    255      1.25  nisimura         imsk |= ioasic_devs[i].iad_intrbits;
    256      1.25  nisimura         bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
    257       1.1       cgd }
    258       1.1       cgd 
    259       1.1       cgd void
    260       1.1       cgd ioasic_intr_disestablish(ioa, cookie)
    261       1.1       cgd 	struct device *ioa;
    262       1.1       cgd 	void *cookie;
    263       1.1       cgd {
    264      1.25  nisimura 	struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0];
    265      1.25  nisimura 	u_long dev, i, imsk;
    266       1.1       cgd 
    267       1.1       cgd 	dev = (u_long)cookie;
    268       1.1       cgd #ifdef DIAGNOSTIC
    269       1.1       cgd 	/* XXX check cookie. */
    270       1.1       cgd #endif
    271       1.1       cgd 
    272       1.1       cgd 	if (ioasicintrs[dev].iai_func == ioasic_intrnull)
    273      1.20   thorpej 		panic("ioasic_intr_disestablish: cookie %lu missing intr", dev);
    274       1.1       cgd 
    275       1.1       cgd 	/* Enable interrupts for the device. */
    276       1.1       cgd 	for (i = 0; i < ioasic_ndevs; i++)
    277       1.1       cgd 		if (ioasic_devs[i].iad_cookie == cookie)
    278       1.1       cgd 			break;
    279       1.1       cgd 	if (i == ioasic_ndevs)
    280       1.1       cgd 		panic("ioasic_intr_disestablish: invalid cookie.");
    281      1.25  nisimura 
    282      1.25  nisimura 	imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
    283      1.25  nisimura 	imsk &= ~ioasic_devs[i].iad_intrbits;
    284      1.25  nisimura 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
    285       1.1       cgd 
    286       1.1       cgd 	ioasicintrs[dev].iai_func = ioasic_intrnull;
    287       1.1       cgd 	ioasicintrs[dev].iai_arg = (void *)dev;
    288       1.1       cgd }
    289       1.1       cgd 
    290       1.1       cgd int
    291       1.1       cgd ioasic_intrnull(val)
    292       1.1       cgd 	void *val;
    293       1.1       cgd {
    294       1.1       cgd 
    295       1.1       cgd 	panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n",
    296       1.1       cgd 	    (u_long)val);
    297       1.1       cgd }
    298       1.1       cgd 
    299       1.1       cgd /*
    300      1.26  nisimura  * ASIC interrupt handler.
    301       1.1       cgd  */
    302       1.1       cgd int
    303       1.1       cgd ioasic_intr(val)
    304       1.1       cgd 	void *val;
    305       1.1       cgd {
    306       1.1       cgd 	register struct ioasic_softc *sc = val;
    307       1.6       cgd 	register int ifound;
    308       1.1       cgd 	int gifound;
    309  1.32.2.1   thorpej 	u_int32_t sir, osir;
    310       1.1       cgd 
    311       1.1       cgd 	gifound = 0;
    312       1.1       cgd 	do {
    313       1.1       cgd 		ifound = 0;
    314       1.1       cgd 		tc_syncbus();
    315       1.1       cgd 
    316  1.32.2.1   thorpej 		osir = sir =
    317  1.32.2.1   thorpej 		    bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR);
    318       1.1       cgd 
    319      1.32   thorpej #define	INCRINTRCNT(slot)	ioasicintrs[slot].iai_evcnt.ev_count++
    320       1.5       cgd 
    321       1.1       cgd 		/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
    322  1.32.2.1   thorpej #define	CHECKINTR(slot, bits, clear)					\
    323      1.31      matt 		if (sir & (bits)) {					\
    324       1.1       cgd 			ifound = 1;					\
    325       1.5       cgd 			INCRINTRCNT(slot);				\
    326       1.1       cgd 			(*ioasicintrs[slot].iai_func)			\
    327       1.1       cgd 			    (ioasicintrs[slot].iai_arg);		\
    328  1.32.2.1   thorpej 			if (clear)					\
    329  1.32.2.1   thorpej 				sir &= ~(bits);				\
    330       1.1       cgd 		}
    331  1.32.2.1   thorpej 		CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0, 0);
    332  1.32.2.1   thorpej 		CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1, 0);
    333  1.32.2.1   thorpej 		CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE, 0);
    334  1.32.2.1   thorpej 		CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN_TXLOAD |
    335  1.32.2.1   thorpej 		    IOASIC_INTR_ISDN_RXLOAD | IOASIC_INTR_ISDN_OVRUN, 1);
    336  1.32.2.1   thorpej 
    337  1.32.2.1   thorpej 		if (sir != osir)
    338  1.32.2.1   thorpej 			bus_space_write_4(sc->sc_bst, sc->sc_bsh,
    339  1.32.2.1   thorpej 			    IOASIC_INTR, sir);
    340       1.1       cgd 
    341       1.1       cgd 		gifound |= ifound;
    342       1.1       cgd 	} while (ifound);
    343       1.1       cgd 
    344       1.1       cgd 	return (gifound);
    345       1.1       cgd }
    346