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ioasic.c revision 1.14 
      1 /* $NetBSD: ioasic.c,v 1.14 1997/09/02 13:20:12 thorpej Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Keith Bostic, Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     31 
     32 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.14 1997/09/02 13:20:12 thorpej Exp $");
     33 
     34 #include <sys/param.h>
     35 #include <sys/kernel.h>
     36 #include <sys/systm.h>
     37 #include <sys/device.h>
     38 
     39 #include <machine/autoconf.h>
     40 #include <machine/pte.h>
     41 #include <machine/rpb.h>
     42 #ifndef EVCNT_COUNTERS
     43 #include <machine/intrcnt.h>
     44 #endif
     45 
     46 #include <dev/tc/tcvar.h>
     47 #include <alpha/tc/ioasicreg.h>
     48 #include <dev/tc/ioasicvar.h>
     49 
     50 struct ioasic_softc {
     51 	struct	device sc_dv;
     52 
     53 	tc_addr_t sc_base;
     54 	void	*sc_cookie;
     55 };
     56 
     57 /* Definition of the driver for autoconfig. */
     58 int	ioasicmatch __P((struct device *, struct cfdata *, void *));
     59 void	ioasicattach __P((struct device *, struct device *, void *));
     60 int     ioasicprint(void *, const char *);
     61 
     62 struct cfattach ioasic_ca = {
     63 	sizeof(struct ioasic_softc), ioasicmatch, ioasicattach,
     64 };
     65 
     66 struct cfdriver ioasic_cd = {
     67 	NULL, "ioasic", DV_DULL,
     68 };
     69 
     70 int	ioasic_intr __P((void *));
     71 int	ioasic_intrnull __P((void *));
     72 
     73 #define	C(x)	((void *)(x))
     74 
     75 #define	IOASIC_DEV_LANCE	0
     76 #define	IOASIC_DEV_SCC0		1
     77 #define	IOASIC_DEV_SCC1		2
     78 #define	IOASIC_DEV_ISDN		3
     79 
     80 #define	IOASIC_DEV_BOGUS	-1
     81 
     82 #define	IOASIC_NCOOKIES		4
     83 
     84 struct ioasic_dev {
     85 	char		*iad_modname;
     86 	tc_offset_t	iad_offset;
     87 	void		*iad_cookie;
     88 	u_int32_t	iad_intrbits;
     89 } ioasic_devs[] = {
     90 	/* XXX lance name */
     91 	{ "lance",    0x000c0000, C(IOASIC_DEV_LANCE), IOASIC_INTR_LANCE, },
     92 	{ "z8530   ", 0x00100000, C(IOASIC_DEV_SCC0),  IOASIC_INTR_SCC_0, },
     93 	{ "z8530   ", 0x00180000, C(IOASIC_DEV_SCC1),  IOASIC_INTR_SCC_1, },
     94 	{ "TOY_RTC ", 0x00200000, C(IOASIC_DEV_BOGUS), 0,                 },
     95 	{ "AMD79c30", 0x00240000, C(IOASIC_DEV_ISDN),  IOASIC_INTR_ISDN,  },
     96 };
     97 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
     98 
     99 struct ioasicintr {
    100 	int	(*iai_func) __P((void *));
    101 	void	*iai_arg;
    102 } ioasicintrs[IOASIC_NCOOKIES];
    103 
    104 tc_addr_t ioasic_base;		/* XXX XXX XXX */
    105 
    106 /* There can be only one. */
    107 int ioasicfound;
    108 
    109 extern int cputype;
    110 
    111 int
    112 ioasicmatch(parent, cfdata, aux)
    113 	struct device *parent;
    114 	struct cfdata *cfdata;
    115 	void *aux;
    116 {
    117 	struct tc_attach_args *ta = aux;
    118 
    119 	/* Make sure that we're looking for this type of device. */
    120 	if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN))
    121 		return (0);
    122 
    123 	/* Check that it can actually exist. */
    124 	if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300))
    125 		panic("ioasicmatch: how did we get here?");
    126 
    127 	if (ioasicfound)
    128 		return (0);
    129 
    130 	return (1);
    131 }
    132 
    133 void
    134 ioasicattach(parent, self, aux)
    135 	struct device *parent, *self;
    136 	void *aux;
    137 {
    138 	struct ioasic_softc *sc = (struct ioasic_softc *)self;
    139 	struct tc_attach_args *ta = aux;
    140 	struct ioasicdev_attach_args ioasicdev;
    141 	u_long i;
    142 
    143 	ioasicfound = 1;
    144 
    145 	sc->sc_base = ta->ta_addr;
    146 	ioasic_base = sc->sc_base;			/* XXX XXX XXX */
    147 	sc->sc_cookie = ta->ta_cookie;
    148 
    149 #ifdef DEC_3000_300
    150 	if (cputype == ST_DEC_3000_300) {
    151 		*(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |=
    152 		    IOASIC_CSR_FASTMODE;
    153 		tc_mb();
    154 		printf(": slow mode\n");
    155 	} else
    156 #endif
    157 		printf(": fast mode\n");
    158 
    159 	/*
    160 	 * Turn off all device interrupt bits.
    161 	 * (This does _not_ include 3000/300 TC option slot bits.
    162 	 */
    163 	for (i = 0; i < ioasic_ndevs; i++)
    164 		*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
    165 			~ioasic_devs[i].iad_intrbits;
    166 	tc_mb();
    167 
    168 	/*
    169 	 * Set up interrupt handlers.
    170 	 */
    171 	for (i = 0; i < IOASIC_NCOOKIES; i++) {
    172 		ioasicintrs[i].iai_func = ioasic_intrnull;
    173 		ioasicintrs[i].iai_arg = (void *)i;
    174 	}
    175 	tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc);
    176 
    177         /*
    178 	 * Try to configure each device.
    179 	 */
    180         for (i = 0; i < ioasic_ndevs; i++) {
    181 		strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname,
    182 			TC_ROM_LLEN);
    183 		ioasicdev.iada_modname[TC_ROM_LLEN] = '\0';
    184 		ioasicdev.iada_offset = ioasic_devs[i].iad_offset;
    185 		ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset;
    186 		ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie;
    187 
    188                 /* Tell the autoconfig machinery we've found the hardware. */
    189                 config_found(self, &ioasicdev, ioasicprint);
    190         }
    191 }
    192 
    193 int
    194 ioasicprint(aux, pnp)
    195 	void *aux;
    196 	const char *pnp;
    197 {
    198 	struct ioasicdev_attach_args *d = aux;
    199 
    200         if (pnp)
    201                 printf("%s at %s", d->iada_modname, pnp);
    202         printf(" offset 0x%lx", (long)d->iada_offset);
    203         return (UNCONF);
    204 }
    205 
    206 int
    207 ioasic_submatch(match, d)
    208 	struct cfdata *match;
    209 	struct ioasicdev_attach_args *d;
    210 {
    211 
    212 	return ((match->ioasiccf_offset == d->iada_offset) ||
    213 		(match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN));
    214 }
    215 
    216 void
    217 ioasic_intr_establish(ioa, cookie, level, func, arg)
    218 	struct device *ioa;
    219 	void *cookie, *arg;
    220 	tc_intrlevel_t level;
    221 	int (*func) __P((void *));
    222 {
    223 	u_long dev, i;
    224 
    225 	dev = (u_long)cookie;
    226 #ifdef DIAGNOSTIC
    227 	/* XXX check cookie. */
    228 #endif
    229 
    230 	if (ioasicintrs[dev].iai_func != ioasic_intrnull)
    231 		panic("ioasic_intr_establish: cookie %d twice", dev);
    232 
    233 	ioasicintrs[dev].iai_func = func;
    234 	ioasicintrs[dev].iai_arg = arg;
    235 
    236 	/* Enable interrupts for the device. */
    237 	for (i = 0; i < ioasic_ndevs; i++)
    238 		if (ioasic_devs[i].iad_cookie == cookie)
    239 			break;
    240 	if (i == ioasic_ndevs)
    241 		panic("ioasic_intr_establish: invalid cookie.");
    242 	*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |=
    243 		ioasic_devs[i].iad_intrbits;
    244 	tc_mb();
    245 }
    246 
    247 void
    248 ioasic_intr_disestablish(ioa, cookie)
    249 	struct device *ioa;
    250 	void *cookie;
    251 {
    252 	u_long dev, i;
    253 
    254 	dev = (u_long)cookie;
    255 #ifdef DIAGNOSTIC
    256 	/* XXX check cookie. */
    257 #endif
    258 
    259 	if (ioasicintrs[dev].iai_func == ioasic_intrnull)
    260 		panic("ioasic_intr_disestablish: cookie %d missing intr", dev);
    261 
    262 	/* Enable interrupts for the device. */
    263 	for (i = 0; i < ioasic_ndevs; i++)
    264 		if (ioasic_devs[i].iad_cookie == cookie)
    265 			break;
    266 	if (i == ioasic_ndevs)
    267 		panic("ioasic_intr_disestablish: invalid cookie.");
    268 	*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
    269 		~ioasic_devs[i].iad_intrbits;
    270 	tc_mb();
    271 
    272 	ioasicintrs[dev].iai_func = ioasic_intrnull;
    273 	ioasicintrs[dev].iai_arg = (void *)dev;
    274 }
    275 
    276 int
    277 ioasic_intrnull(val)
    278 	void *val;
    279 {
    280 
    281 	panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n",
    282 	    (u_long)val);
    283 }
    284 
    285 /*
    286  * asic_intr --
    287  *	ASIC interrupt handler.
    288  */
    289 int
    290 ioasic_intr(val)
    291 	void *val;
    292 {
    293 	register struct ioasic_softc *sc = val;
    294 	register int ifound;
    295 	int gifound;
    296 	u_int32_t sir;
    297 	volatile u_int32_t *sirp;
    298 
    299 	sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base);
    300 
    301 	gifound = 0;
    302 	do {
    303 		ifound = 0;
    304 		tc_syncbus();
    305 
    306 		sir = *sirp;
    307 
    308 #ifdef EVCNT_COUNTERS
    309 	/* No interrupt counting via evcnt counters */
    310 	XXX BREAK HERE XXX
    311 #else /* !EVCNT_COUNTERS */
    312 #define	INCRINTRCNT(slot)	intrcnt[INTRCNT_IOASIC + slot]++
    313 #endif /* EVCNT_COUNTERS */
    314 
    315 		/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
    316 #define	CHECKINTR(slot, bits)						\
    317 		if (sir & bits) {					\
    318 			ifound = 1;					\
    319 			INCRINTRCNT(slot);				\
    320 			(*ioasicintrs[slot].iai_func)			\
    321 			    (ioasicintrs[slot].iai_arg);		\
    322 		}
    323 		CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0);
    324 		CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1);
    325 		CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE);
    326 		CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN);
    327 
    328 		gifound |= ifound;
    329 	} while (ifound);
    330 
    331 	return (gifound);
    332 }
    333 
    334 /* XXX */
    335 char *
    336 ioasic_lance_ether_address()
    337 {
    338 
    339 	return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base);
    340 }
    341 
    342 void
    343 ioasic_lance_dma_setup(v)
    344 	void *v;
    345 {
    346 	volatile u_int32_t *ldp;
    347 	tc_addr_t tca;
    348 
    349 	tca = (tc_addr_t)v;
    350 
    351 	ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base);
    352 	*ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f);
    353 	tc_wmb();
    354 
    355 	*(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |=
    356 	    IOASIC_CSR_DMAEN_LANCE;
    357 	tc_mb();
    358 }
    359