ioasic.c revision 1.15
1 /* $NetBSD: ioasic.c,v 1.15 1997/09/02 13:26:42 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include "opt_dec_3000_300.h" 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.15 1997/09/02 13:26:42 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/pte.h> 43 #include <machine/rpb.h> 44 #ifndef EVCNT_COUNTERS 45 #include <machine/intrcnt.h> 46 #endif 47 48 #include <dev/tc/tcvar.h> 49 #include <alpha/tc/ioasicreg.h> 50 #include <dev/tc/ioasicvar.h> 51 52 struct ioasic_softc { 53 struct device sc_dv; 54 55 tc_addr_t sc_base; 56 void *sc_cookie; 57 }; 58 59 /* Definition of the driver for autoconfig. */ 60 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 61 void ioasicattach __P((struct device *, struct device *, void *)); 62 int ioasicprint(void *, const char *); 63 64 struct cfattach ioasic_ca = { 65 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 66 }; 67 68 struct cfdriver ioasic_cd = { 69 NULL, "ioasic", DV_DULL, 70 }; 71 72 int ioasic_intr __P((void *)); 73 int ioasic_intrnull __P((void *)); 74 75 #define C(x) ((void *)(x)) 76 77 #define IOASIC_DEV_LANCE 0 78 #define IOASIC_DEV_SCC0 1 79 #define IOASIC_DEV_SCC1 2 80 #define IOASIC_DEV_ISDN 3 81 82 #define IOASIC_DEV_BOGUS -1 83 84 #define IOASIC_NCOOKIES 4 85 86 struct ioasic_dev { 87 char *iad_modname; 88 tc_offset_t iad_offset; 89 void *iad_cookie; 90 u_int32_t iad_intrbits; 91 } ioasic_devs[] = { 92 /* XXX lance name */ 93 { "lance", 0x000c0000, C(IOASIC_DEV_LANCE), IOASIC_INTR_LANCE, }, 94 { "z8530 ", 0x00100000, C(IOASIC_DEV_SCC0), IOASIC_INTR_SCC_0, }, 95 { "z8530 ", 0x00180000, C(IOASIC_DEV_SCC1), IOASIC_INTR_SCC_1, }, 96 { "TOY_RTC ", 0x00200000, C(IOASIC_DEV_BOGUS), 0, }, 97 { "AMD79c30", 0x00240000, C(IOASIC_DEV_ISDN), IOASIC_INTR_ISDN, }, 98 }; 99 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 100 101 struct ioasicintr { 102 int (*iai_func) __P((void *)); 103 void *iai_arg; 104 } ioasicintrs[IOASIC_NCOOKIES]; 105 106 tc_addr_t ioasic_base; /* XXX XXX XXX */ 107 108 /* There can be only one. */ 109 int ioasicfound; 110 111 extern int cputype; 112 113 int 114 ioasicmatch(parent, cfdata, aux) 115 struct device *parent; 116 struct cfdata *cfdata; 117 void *aux; 118 { 119 struct tc_attach_args *ta = aux; 120 121 /* Make sure that we're looking for this type of device. */ 122 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 123 return (0); 124 125 /* Check that it can actually exist. */ 126 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 127 panic("ioasicmatch: how did we get here?"); 128 129 if (ioasicfound) 130 return (0); 131 132 return (1); 133 } 134 135 void 136 ioasicattach(parent, self, aux) 137 struct device *parent, *self; 138 void *aux; 139 { 140 struct ioasic_softc *sc = (struct ioasic_softc *)self; 141 struct tc_attach_args *ta = aux; 142 struct ioasicdev_attach_args ioasicdev; 143 u_long i; 144 145 ioasicfound = 1; 146 147 sc->sc_base = ta->ta_addr; 148 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 149 sc->sc_cookie = ta->ta_cookie; 150 151 #ifdef DEC_3000_300 152 if (cputype == ST_DEC_3000_300) { 153 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 154 IOASIC_CSR_FASTMODE; 155 tc_mb(); 156 printf(": slow mode\n"); 157 } else 158 #endif 159 printf(": fast mode\n"); 160 161 /* 162 * Turn off all device interrupt bits. 163 * (This does _not_ include 3000/300 TC option slot bits. 164 */ 165 for (i = 0; i < ioasic_ndevs; i++) 166 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 167 ~ioasic_devs[i].iad_intrbits; 168 tc_mb(); 169 170 /* 171 * Set up interrupt handlers. 172 */ 173 for (i = 0; i < IOASIC_NCOOKIES; i++) { 174 ioasicintrs[i].iai_func = ioasic_intrnull; 175 ioasicintrs[i].iai_arg = (void *)i; 176 } 177 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 178 179 /* 180 * Try to configure each device. 181 */ 182 for (i = 0; i < ioasic_ndevs; i++) { 183 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 184 TC_ROM_LLEN); 185 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 186 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 187 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 188 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 189 190 /* Tell the autoconfig machinery we've found the hardware. */ 191 config_found(self, &ioasicdev, ioasicprint); 192 } 193 } 194 195 int 196 ioasicprint(aux, pnp) 197 void *aux; 198 const char *pnp; 199 { 200 struct ioasicdev_attach_args *d = aux; 201 202 if (pnp) 203 printf("%s at %s", d->iada_modname, pnp); 204 printf(" offset 0x%lx", (long)d->iada_offset); 205 return (UNCONF); 206 } 207 208 int 209 ioasic_submatch(match, d) 210 struct cfdata *match; 211 struct ioasicdev_attach_args *d; 212 { 213 214 return ((match->ioasiccf_offset == d->iada_offset) || 215 (match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN)); 216 } 217 218 void 219 ioasic_intr_establish(ioa, cookie, level, func, arg) 220 struct device *ioa; 221 void *cookie, *arg; 222 tc_intrlevel_t level; 223 int (*func) __P((void *)); 224 { 225 u_long dev, i; 226 227 dev = (u_long)cookie; 228 #ifdef DIAGNOSTIC 229 /* XXX check cookie. */ 230 #endif 231 232 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 233 panic("ioasic_intr_establish: cookie %d twice", dev); 234 235 ioasicintrs[dev].iai_func = func; 236 ioasicintrs[dev].iai_arg = arg; 237 238 /* Enable interrupts for the device. */ 239 for (i = 0; i < ioasic_ndevs; i++) 240 if (ioasic_devs[i].iad_cookie == cookie) 241 break; 242 if (i == ioasic_ndevs) 243 panic("ioasic_intr_establish: invalid cookie."); 244 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 245 ioasic_devs[i].iad_intrbits; 246 tc_mb(); 247 } 248 249 void 250 ioasic_intr_disestablish(ioa, cookie) 251 struct device *ioa; 252 void *cookie; 253 { 254 u_long dev, i; 255 256 dev = (u_long)cookie; 257 #ifdef DIAGNOSTIC 258 /* XXX check cookie. */ 259 #endif 260 261 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 262 panic("ioasic_intr_disestablish: cookie %d missing intr", dev); 263 264 /* Enable interrupts for the device. */ 265 for (i = 0; i < ioasic_ndevs; i++) 266 if (ioasic_devs[i].iad_cookie == cookie) 267 break; 268 if (i == ioasic_ndevs) 269 panic("ioasic_intr_disestablish: invalid cookie."); 270 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 271 ~ioasic_devs[i].iad_intrbits; 272 tc_mb(); 273 274 ioasicintrs[dev].iai_func = ioasic_intrnull; 275 ioasicintrs[dev].iai_arg = (void *)dev; 276 } 277 278 int 279 ioasic_intrnull(val) 280 void *val; 281 { 282 283 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 284 (u_long)val); 285 } 286 287 /* 288 * asic_intr -- 289 * ASIC interrupt handler. 290 */ 291 int 292 ioasic_intr(val) 293 void *val; 294 { 295 register struct ioasic_softc *sc = val; 296 register int ifound; 297 int gifound; 298 u_int32_t sir; 299 volatile u_int32_t *sirp; 300 301 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 302 303 gifound = 0; 304 do { 305 ifound = 0; 306 tc_syncbus(); 307 308 sir = *sirp; 309 310 #ifdef EVCNT_COUNTERS 311 /* No interrupt counting via evcnt counters */ 312 XXX BREAK HERE XXX 313 #else /* !EVCNT_COUNTERS */ 314 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 315 #endif /* EVCNT_COUNTERS */ 316 317 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 318 #define CHECKINTR(slot, bits) \ 319 if (sir & bits) { \ 320 ifound = 1; \ 321 INCRINTRCNT(slot); \ 322 (*ioasicintrs[slot].iai_func) \ 323 (ioasicintrs[slot].iai_arg); \ 324 } 325 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 326 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 327 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 328 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 329 330 gifound |= ifound; 331 } while (ifound); 332 333 return (gifound); 334 } 335 336 /* XXX */ 337 char * 338 ioasic_lance_ether_address() 339 { 340 341 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 342 } 343 344 void 345 ioasic_lance_dma_setup(v) 346 void *v; 347 { 348 volatile u_int32_t *ldp; 349 tc_addr_t tca; 350 351 tca = (tc_addr_t)v; 352 353 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 354 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 355 tc_wmb(); 356 357 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 358 IOASIC_CSR_DMAEN_LANCE; 359 tc_mb(); 360 } 361
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