ioasic.c revision 1.17
1 /* $NetBSD: ioasic.c,v 1.17 1998/01/19 02:56:05 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.17 1998/01/19 02:56:05 thorpej Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <alpha/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 struct ioasic_softc { 91 struct device sc_dv; 92 93 tc_addr_t sc_base; 94 void *sc_cookie; 95 96 bus_dma_tag_t sc_dmat; 97 bus_dmamap_t sc_lance_dmam; 98 }; 99 100 /* Definition of the driver for autoconfig. */ 101 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 102 void ioasicattach __P((struct device *, struct device *, void *)); 103 int ioasicprint(void *, const char *); 104 105 struct cfattach ioasic_ca = { 106 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 107 }; 108 109 int ioasic_intr __P((void *)); 110 int ioasic_intrnull __P((void *)); 111 112 #define C(x) ((void *)(x)) 113 114 #define IOASIC_DEV_LANCE 0 115 #define IOASIC_DEV_SCC0 1 116 #define IOASIC_DEV_SCC1 2 117 #define IOASIC_DEV_ISDN 3 118 119 #define IOASIC_DEV_BOGUS -1 120 121 #define IOASIC_NCOOKIES 4 122 123 struct ioasic_dev { 124 char *iad_modname; 125 tc_offset_t iad_offset; 126 void *iad_cookie; 127 u_int32_t iad_intrbits; 128 } ioasic_devs[] = { 129 /* XXX lance name */ 130 { "lance", 0x000c0000, C(IOASIC_DEV_LANCE), IOASIC_INTR_LANCE, }, 131 { "z8530 ", 0x00100000, C(IOASIC_DEV_SCC0), IOASIC_INTR_SCC_0, }, 132 { "z8530 ", 0x00180000, C(IOASIC_DEV_SCC1), IOASIC_INTR_SCC_1, }, 133 { "TOY_RTC ", 0x00200000, C(IOASIC_DEV_BOGUS), 0, }, 134 { "AMD79c30", 0x00240000, C(IOASIC_DEV_ISDN), IOASIC_INTR_ISDN, }, 135 }; 136 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 137 138 struct ioasicintr { 139 int (*iai_func) __P((void *)); 140 void *iai_arg; 141 } ioasicintrs[IOASIC_NCOOKIES]; 142 143 tc_addr_t ioasic_base; /* XXX XXX XXX */ 144 145 /* There can be only one. */ 146 int ioasicfound; 147 148 extern int cputype; 149 150 /* 151 * DMA area for IOASIC LANCE. 152 * XXX Should be done differently, but this is better than it used to be. 153 */ 154 #define LE_IOASIC_MEMSIZE (128*1024) 155 #define LE_IOASIC_MEMALIGN (128*1024) 156 caddr_t le_iomem; 157 158 void ioasic_lance_dma_setup __P((struct ioasic_softc *)); 159 160 int 161 ioasicmatch(parent, cfdata, aux) 162 struct device *parent; 163 struct cfdata *cfdata; 164 void *aux; 165 { 166 struct tc_attach_args *ta = aux; 167 168 /* Make sure that we're looking for this type of device. */ 169 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 170 return (0); 171 172 /* Check that it can actually exist. */ 173 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 174 panic("ioasicmatch: how did we get here?"); 175 176 if (ioasicfound) 177 return (0); 178 179 return (1); 180 } 181 182 void 183 ioasicattach(parent, self, aux) 184 struct device *parent, *self; 185 void *aux; 186 { 187 struct ioasic_softc *sc = (struct ioasic_softc *)self; 188 struct tc_attach_args *ta = aux; 189 struct ioasicdev_attach_args ioasicdev; 190 u_long i; 191 192 ioasicfound = 1; 193 194 sc->sc_base = ta->ta_addr; 195 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 196 sc->sc_cookie = ta->ta_cookie; 197 sc->sc_dmat = ta->ta_dmat; 198 199 #ifdef DEC_3000_300 200 if (cputype == ST_DEC_3000_300) { 201 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 202 IOASIC_CSR_FASTMODE; 203 tc_mb(); 204 printf(": slow mode\n"); 205 } else 206 #endif 207 printf(": fast mode\n"); 208 209 /* 210 * Turn off all device interrupt bits. 211 * (This does _not_ include 3000/300 TC option slot bits. 212 */ 213 for (i = 0; i < ioasic_ndevs; i++) 214 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 215 ~ioasic_devs[i].iad_intrbits; 216 tc_mb(); 217 218 /* 219 * Set up interrupt handlers. 220 */ 221 for (i = 0; i < IOASIC_NCOOKIES; i++) { 222 ioasicintrs[i].iai_func = ioasic_intrnull; 223 ioasicintrs[i].iai_arg = (void *)i; 224 } 225 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 226 227 /* 228 * Set up the LANCE DMA area. 229 */ 230 ioasic_lance_dma_setup(sc); 231 232 /* 233 * Try to configure each device. 234 */ 235 for (i = 0; i < ioasic_ndevs; i++) { 236 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 237 TC_ROM_LLEN); 238 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 239 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 240 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 241 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 242 243 /* Tell the autoconfig machinery we've found the hardware. */ 244 config_found(self, &ioasicdev, ioasicprint); 245 } 246 } 247 248 int 249 ioasicprint(aux, pnp) 250 void *aux; 251 const char *pnp; 252 { 253 struct ioasicdev_attach_args *d = aux; 254 255 if (pnp) 256 printf("%s at %s", d->iada_modname, pnp); 257 printf(" offset 0x%lx", (long)d->iada_offset); 258 return (UNCONF); 259 } 260 261 int 262 ioasic_submatch(match, d) 263 struct cfdata *match; 264 struct ioasicdev_attach_args *d; 265 { 266 267 return ((match->ioasiccf_offset == d->iada_offset) || 268 (match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN)); 269 } 270 271 void 272 ioasic_intr_establish(ioa, cookie, level, func, arg) 273 struct device *ioa; 274 void *cookie, *arg; 275 tc_intrlevel_t level; 276 int (*func) __P((void *)); 277 { 278 u_long dev, i; 279 280 dev = (u_long)cookie; 281 #ifdef DIAGNOSTIC 282 /* XXX check cookie. */ 283 #endif 284 285 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 286 panic("ioasic_intr_establish: cookie %d twice", dev); 287 288 ioasicintrs[dev].iai_func = func; 289 ioasicintrs[dev].iai_arg = arg; 290 291 /* Enable interrupts for the device. */ 292 for (i = 0; i < ioasic_ndevs; i++) 293 if (ioasic_devs[i].iad_cookie == cookie) 294 break; 295 if (i == ioasic_ndevs) 296 panic("ioasic_intr_establish: invalid cookie."); 297 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 298 ioasic_devs[i].iad_intrbits; 299 tc_mb(); 300 } 301 302 void 303 ioasic_intr_disestablish(ioa, cookie) 304 struct device *ioa; 305 void *cookie; 306 { 307 u_long dev, i; 308 309 dev = (u_long)cookie; 310 #ifdef DIAGNOSTIC 311 /* XXX check cookie. */ 312 #endif 313 314 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 315 panic("ioasic_intr_disestablish: cookie %d missing intr", dev); 316 317 /* Enable interrupts for the device. */ 318 for (i = 0; i < ioasic_ndevs; i++) 319 if (ioasic_devs[i].iad_cookie == cookie) 320 break; 321 if (i == ioasic_ndevs) 322 panic("ioasic_intr_disestablish: invalid cookie."); 323 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 324 ~ioasic_devs[i].iad_intrbits; 325 tc_mb(); 326 327 ioasicintrs[dev].iai_func = ioasic_intrnull; 328 ioasicintrs[dev].iai_arg = (void *)dev; 329 } 330 331 int 332 ioasic_intrnull(val) 333 void *val; 334 { 335 336 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 337 (u_long)val); 338 } 339 340 /* 341 * asic_intr -- 342 * ASIC interrupt handler. 343 */ 344 int 345 ioasic_intr(val) 346 void *val; 347 { 348 register struct ioasic_softc *sc = val; 349 register int ifound; 350 int gifound; 351 u_int32_t sir; 352 volatile u_int32_t *sirp; 353 354 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 355 356 gifound = 0; 357 do { 358 ifound = 0; 359 tc_syncbus(); 360 361 sir = *sirp; 362 363 #ifdef EVCNT_COUNTERS 364 /* No interrupt counting via evcnt counters */ 365 XXX BREAK HERE XXX 366 #else /* !EVCNT_COUNTERS */ 367 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 368 #endif /* EVCNT_COUNTERS */ 369 370 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 371 #define CHECKINTR(slot, bits) \ 372 if (sir & bits) { \ 373 ifound = 1; \ 374 INCRINTRCNT(slot); \ 375 (*ioasicintrs[slot].iai_func) \ 376 (ioasicintrs[slot].iai_arg); \ 377 } 378 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 379 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 380 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 381 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 382 383 gifound |= ifound; 384 } while (ifound); 385 386 return (gifound); 387 } 388 389 /* XXX */ 390 char * 391 ioasic_lance_ether_address() 392 { 393 394 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 395 } 396 397 void 398 ioasic_lance_dma_setup(sc) 399 struct ioasic_softc *sc; 400 { 401 bus_dma_tag_t dmat = sc->sc_dmat; 402 bus_dma_segment_t seg; 403 volatile u_int32_t *ldp; 404 tc_addr_t tca; 405 int rseg; 406 407 /* 408 * Allocate a DMA area for the chip. 409 */ 410 if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, 411 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 412 printf("%s: can't allocate DMA area for LANCE\n", 413 sc->sc_dv.dv_xname); 414 return; 415 } 416 if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, 417 &le_iomem, BUS_DMA_NOWAIT|BUS_DMAMEM_NOSYNC)) { 418 printf("%s: can't map DMA area for LANCE\n", 419 sc->sc_dv.dv_xname); 420 bus_dmamem_free(dmat, &seg, rseg); 421 return; 422 } 423 424 /* 425 * Create and load the DMA map for the DMA area. 426 */ 427 if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, 428 LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) { 429 printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname); 430 goto bad; 431 } 432 if (bus_dmamap_load(dmat, sc->sc_lance_dmam, 433 le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { 434 printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname); 435 goto bad; 436 } 437 438 tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr; 439 if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) { 440 printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname); 441 bus_dmamap_unload(dmat, sc->sc_lance_dmam); 442 goto bad; 443 } 444 445 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 446 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 447 tc_wmb(); 448 449 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 450 IOASIC_CSR_DMAEN_LANCE; 451 tc_mb(); 452 return; 453 454 bad: 455 bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); 456 bus_dmamem_free(dmat, &seg, rseg); 457 le_iomem = 0; 458 } 459
Indexes created Tue Sep 30 06:09:59 GMT 2025