ioasic.c revision 1.20
1 /* $NetBSD: ioasic.c,v 1.20 1999/02/12 01:50:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.20 1999/02/12 01:50:30 thorpej Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <alpha/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 struct ioasic_softc { 91 struct device sc_dv; 92 93 tc_addr_t sc_base; 94 void *sc_cookie; 95 96 bus_dma_tag_t sc_dmat; 97 bus_dmamap_t sc_lance_dmam; 98 }; 99 100 /* Definition of the driver for autoconfig. */ 101 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 102 void ioasicattach __P((struct device *, struct device *, void *)); 103 int ioasicprint(void *, const char *); 104 105 struct cfattach ioasic_ca = { 106 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 107 }; 108 109 int ioasic_intr __P((void *)); 110 int ioasic_intrnull __P((void *)); 111 112 #define C(x) ((void *)(x)) 113 114 #define IOASIC_DEV_LANCE 0 115 #define IOASIC_DEV_SCC0 1 116 #define IOASIC_DEV_SCC1 2 117 #define IOASIC_DEV_ISDN 3 118 119 #define IOASIC_DEV_BOGUS -1 120 121 #define IOASIC_NCOOKIES 4 122 123 struct ioasic_dev { 124 char *iad_modname; 125 tc_offset_t iad_offset; 126 void *iad_cookie; 127 u_int32_t iad_intrbits; 128 } ioasic_devs[] = { 129 /* XXX lance name */ 130 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 131 IOASIC_INTR_LANCE, }, 132 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 133 IOASIC_INTR_SCC_0, }, 134 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 135 IOASIC_INTR_SCC_1, }, 136 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 137 0, }, 138 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 139 IOASIC_INTR_ISDN, }, 140 }; 141 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 142 143 struct ioasicintr { 144 int (*iai_func) __P((void *)); 145 void *iai_arg; 146 } ioasicintrs[IOASIC_NCOOKIES]; 147 148 tc_addr_t ioasic_base; /* XXX XXX XXX */ 149 150 /* There can be only one. */ 151 int ioasicfound; 152 153 extern int cputype; 154 155 /* 156 * DMA area for IOASIC LANCE. 157 * XXX Should be done differently, but this is better than it used to be. 158 */ 159 #define LE_IOASIC_MEMSIZE (128*1024) 160 #define LE_IOASIC_MEMALIGN (128*1024) 161 caddr_t le_iomem; 162 163 void ioasic_lance_dma_setup __P((struct ioasic_softc *)); 164 165 int 166 ioasicmatch(parent, cfdata, aux) 167 struct device *parent; 168 struct cfdata *cfdata; 169 void *aux; 170 { 171 struct tc_attach_args *ta = aux; 172 173 /* Make sure that we're looking for this type of device. */ 174 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 175 return (0); 176 177 /* Check that it can actually exist. */ 178 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 179 panic("ioasicmatch: how did we get here?"); 180 181 if (ioasicfound) 182 return (0); 183 184 return (1); 185 } 186 187 void 188 ioasicattach(parent, self, aux) 189 struct device *parent, *self; 190 void *aux; 191 { 192 struct ioasic_softc *sc = (struct ioasic_softc *)self; 193 struct tc_attach_args *ta = aux; 194 struct ioasicdev_attach_args ioasicdev; 195 u_long i; 196 197 ioasicfound = 1; 198 199 sc->sc_base = ta->ta_addr; 200 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 201 sc->sc_cookie = ta->ta_cookie; 202 sc->sc_dmat = ta->ta_dmat; 203 204 #ifdef DEC_3000_300 205 if (cputype == ST_DEC_3000_300) { 206 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 207 IOASIC_CSR_FASTMODE; 208 tc_mb(); 209 printf(": slow mode\n"); 210 } else 211 #endif 212 printf(": fast mode\n"); 213 214 /* 215 * Turn off all device interrupt bits. 216 * (This does _not_ include 3000/300 TC option slot bits. 217 */ 218 for (i = 0; i < ioasic_ndevs; i++) 219 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 220 ~ioasic_devs[i].iad_intrbits; 221 tc_mb(); 222 223 /* 224 * Set up interrupt handlers. 225 */ 226 for (i = 0; i < IOASIC_NCOOKIES; i++) { 227 ioasicintrs[i].iai_func = ioasic_intrnull; 228 ioasicintrs[i].iai_arg = (void *)i; 229 } 230 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 231 232 /* 233 * Set up the LANCE DMA area. 234 */ 235 ioasic_lance_dma_setup(sc); 236 237 /* 238 * Try to configure each device. 239 */ 240 for (i = 0; i < ioasic_ndevs; i++) { 241 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 242 TC_ROM_LLEN); 243 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 244 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 245 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 246 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 247 248 /* Tell the autoconfig machinery we've found the hardware. */ 249 config_found(self, &ioasicdev, ioasicprint); 250 } 251 } 252 253 int 254 ioasicprint(aux, pnp) 255 void *aux; 256 const char *pnp; 257 { 258 struct ioasicdev_attach_args *d = aux; 259 260 if (pnp) 261 printf("%s at %s", d->iada_modname, pnp); 262 printf(" offset 0x%lx", (long)d->iada_offset); 263 return (UNCONF); 264 } 265 266 int 267 ioasic_submatch(match, d) 268 struct cfdata *match; 269 struct ioasicdev_attach_args *d; 270 { 271 272 return ((match->ioasiccf_offset == d->iada_offset) || 273 (match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN)); 274 } 275 276 void 277 ioasic_intr_establish(ioa, cookie, level, func, arg) 278 struct device *ioa; 279 void *cookie, *arg; 280 tc_intrlevel_t level; 281 int (*func) __P((void *)); 282 { 283 u_long dev, i; 284 285 dev = (u_long)cookie; 286 #ifdef DIAGNOSTIC 287 /* XXX check cookie. */ 288 #endif 289 290 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 291 panic("ioasic_intr_establish: cookie %lu twice", dev); 292 293 ioasicintrs[dev].iai_func = func; 294 ioasicintrs[dev].iai_arg = arg; 295 296 /* Enable interrupts for the device. */ 297 for (i = 0; i < ioasic_ndevs; i++) 298 if (ioasic_devs[i].iad_cookie == cookie) 299 break; 300 if (i == ioasic_ndevs) 301 panic("ioasic_intr_establish: invalid cookie."); 302 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 303 ioasic_devs[i].iad_intrbits; 304 tc_mb(); 305 } 306 307 void 308 ioasic_intr_disestablish(ioa, cookie) 309 struct device *ioa; 310 void *cookie; 311 { 312 u_long dev, i; 313 314 dev = (u_long)cookie; 315 #ifdef DIAGNOSTIC 316 /* XXX check cookie. */ 317 #endif 318 319 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 320 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 321 322 /* Enable interrupts for the device. */ 323 for (i = 0; i < ioasic_ndevs; i++) 324 if (ioasic_devs[i].iad_cookie == cookie) 325 break; 326 if (i == ioasic_ndevs) 327 panic("ioasic_intr_disestablish: invalid cookie."); 328 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 329 ~ioasic_devs[i].iad_intrbits; 330 tc_mb(); 331 332 ioasicintrs[dev].iai_func = ioasic_intrnull; 333 ioasicintrs[dev].iai_arg = (void *)dev; 334 } 335 336 int 337 ioasic_intrnull(val) 338 void *val; 339 { 340 341 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 342 (u_long)val); 343 } 344 345 /* 346 * asic_intr -- 347 * ASIC interrupt handler. 348 */ 349 int 350 ioasic_intr(val) 351 void *val; 352 { 353 register struct ioasic_softc *sc = val; 354 register int ifound; 355 int gifound; 356 u_int32_t sir; 357 volatile u_int32_t *sirp; 358 359 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 360 361 gifound = 0; 362 do { 363 ifound = 0; 364 tc_syncbus(); 365 366 sir = *sirp; 367 368 #ifdef EVCNT_COUNTERS 369 /* No interrupt counting via evcnt counters */ 370 XXX BREAK HERE XXX 371 #else /* !EVCNT_COUNTERS */ 372 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 373 #endif /* EVCNT_COUNTERS */ 374 375 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 376 #define CHECKINTR(slot, bits) \ 377 if (sir & bits) { \ 378 ifound = 1; \ 379 INCRINTRCNT(slot); \ 380 (*ioasicintrs[slot].iai_func) \ 381 (ioasicintrs[slot].iai_arg); \ 382 } 383 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 384 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 385 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 386 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 387 388 gifound |= ifound; 389 } while (ifound); 390 391 return (gifound); 392 } 393 394 /* XXX */ 395 char * 396 ioasic_lance_ether_address() 397 { 398 399 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 400 } 401 402 void 403 ioasic_lance_dma_setup(sc) 404 struct ioasic_softc *sc; 405 { 406 bus_dma_tag_t dmat = sc->sc_dmat; 407 bus_dma_segment_t seg; 408 volatile u_int32_t *ldp; 409 tc_addr_t tca; 410 int rseg; 411 412 /* 413 * Allocate a DMA area for the chip. 414 */ 415 if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, 416 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 417 printf("%s: can't allocate DMA area for LANCE\n", 418 sc->sc_dv.dv_xname); 419 return; 420 } 421 if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, 422 &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 423 printf("%s: can't map DMA area for LANCE\n", 424 sc->sc_dv.dv_xname); 425 bus_dmamem_free(dmat, &seg, rseg); 426 return; 427 } 428 429 /* 430 * Create and load the DMA map for the DMA area. 431 */ 432 if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, 433 LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) { 434 printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname); 435 goto bad; 436 } 437 if (bus_dmamap_load(dmat, sc->sc_lance_dmam, 438 le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { 439 printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname); 440 goto bad; 441 } 442 443 tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr; 444 if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) { 445 printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname); 446 bus_dmamap_unload(dmat, sc->sc_lance_dmam); 447 goto bad; 448 } 449 450 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 451 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 452 tc_wmb(); 453 454 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 455 IOASIC_CSR_DMAEN_LANCE; 456 tc_mb(); 457 return; 458 459 bad: 460 bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); 461 bus_dmamem_free(dmat, &seg, rseg); 462 le_iomem = 0; 463 } 464
Indexes created Tue Sep 30 07:10:03 GMT 2025