ioasic.c revision 1.22
1 /* $NetBSD: ioasic.c,v 1.22 1999/03/17 17:50:06 ross Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.22 1999/03/17 17:50:06 ross Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <alpha/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 /* Definition of the driver for autoconfig. */ 91 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 92 void ioasicattach __P((struct device *, struct device *, void *)); 93 int ioasicprint(void *, const char *); 94 95 struct cfattach ioasic_ca = { 96 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 97 }; 98 99 int ioasic_intr __P((void *)); 100 int ioasic_intrnull __P((void *)); 101 102 #define C(x) ((void *)(x)) 103 104 #define IOASIC_DEV_LANCE 0 105 #define IOASIC_DEV_SCC0 1 106 #define IOASIC_DEV_SCC1 2 107 #define IOASIC_DEV_ISDN 3 108 109 #define IOASIC_DEV_BOGUS -1 110 111 #define IOASIC_NCOOKIES 4 112 113 struct ioasic_dev ioasic_devs[] = { 114 /* XXX lance name */ 115 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 116 IOASIC_INTR_LANCE, }, 117 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 118 IOASIC_INTR_SCC_0, }, 119 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 120 IOASIC_INTR_SCC_1, }, 121 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 122 0, }, 123 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 124 IOASIC_INTR_ISDN, }, 125 }; 126 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 127 128 struct ioasicintr { 129 int (*iai_func) __P((void *)); 130 void *iai_arg; 131 } ioasicintrs[IOASIC_NCOOKIES]; 132 133 tc_addr_t ioasic_base; /* XXX XXX XXX */ 134 135 /* There can be only one. */ 136 int ioasicfound; 137 138 extern int cputype; 139 140 /* 141 * DMA area for IOASIC LANCE. 142 * XXX Should be done differently, but this is better than it used to be. 143 */ 144 #define LE_IOASIC_MEMSIZE (128*1024) 145 #define LE_IOASIC_MEMALIGN (128*1024) 146 caddr_t le_iomem; 147 148 void ioasic_lance_dma_setup __P((struct ioasic_softc *)); 149 150 int 151 ioasicmatch(parent, cfdata, aux) 152 struct device *parent; 153 struct cfdata *cfdata; 154 void *aux; 155 { 156 struct tc_attach_args *ta = aux; 157 158 /* Make sure that we're looking for this type of device. */ 159 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 160 return (0); 161 162 /* Check that it can actually exist. */ 163 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 164 panic("ioasicmatch: how did we get here?"); 165 166 if (ioasicfound) 167 return (0); 168 169 return (1); 170 } 171 172 void 173 ioasicattach(parent, self, aux) 174 struct device *parent, *self; 175 void *aux; 176 { 177 struct ioasic_softc *sc = (struct ioasic_softc *)self; 178 struct tc_attach_args *ta = aux; 179 struct ioasicdev_attach_args ioasicdev; 180 u_long i; 181 182 ioasicfound = 1; 183 184 sc->sc_base = ta->ta_addr; 185 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 186 sc->sc_cookie = ta->ta_cookie; 187 sc->sc_dmat = ta->ta_dmat; 188 189 #ifdef DEC_3000_300 190 if (cputype == ST_DEC_3000_300) { 191 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 192 IOASIC_CSR_FASTMODE; 193 tc_mb(); 194 printf(": slow mode\n"); 195 } else 196 #endif 197 printf(": fast mode\n"); 198 199 /* 200 * Turn off all device interrupt bits. 201 * (This does _not_ include 3000/300 TC option slot bits. 202 */ 203 for (i = 0; i < ioasic_ndevs; i++) 204 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 205 ~ioasic_devs[i].iad_intrbits; 206 tc_mb(); 207 208 /* 209 * Set up interrupt handlers. 210 */ 211 for (i = 0; i < IOASIC_NCOOKIES; i++) { 212 ioasicintrs[i].iai_func = ioasic_intrnull; 213 ioasicintrs[i].iai_arg = (void *)i; 214 } 215 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 216 217 /* 218 * Set up the LANCE DMA area. 219 */ 220 ioasic_lance_dma_setup(sc); 221 222 /* 223 * Try to configure each device. 224 */ 225 for (i = 0; i < ioasic_ndevs; i++) { 226 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 227 TC_ROM_LLEN); 228 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 229 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 230 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 231 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 232 233 /* Tell the autoconfig machinery we've found the hardware. */ 234 config_found(self, &ioasicdev, ioasicprint); 235 } 236 } 237 238 void 239 ioasic_intr_establish(ioa, cookie, level, func, arg) 240 struct device *ioa; 241 void *cookie, *arg; 242 tc_intrlevel_t level; 243 int (*func) __P((void *)); 244 { 245 u_long dev, i; 246 247 dev = (u_long)cookie; 248 #ifdef DIAGNOSTIC 249 /* XXX check cookie. */ 250 #endif 251 252 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 253 panic("ioasic_intr_establish: cookie %lu twice", dev); 254 255 ioasicintrs[dev].iai_func = func; 256 ioasicintrs[dev].iai_arg = arg; 257 258 /* Enable interrupts for the device. */ 259 for (i = 0; i < ioasic_ndevs; i++) 260 if (ioasic_devs[i].iad_cookie == cookie) 261 break; 262 if (i == ioasic_ndevs) 263 panic("ioasic_intr_establish: invalid cookie."); 264 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 265 ioasic_devs[i].iad_intrbits; 266 tc_mb(); 267 } 268 269 void 270 ioasic_intr_disestablish(ioa, cookie) 271 struct device *ioa; 272 void *cookie; 273 { 274 u_long dev, i; 275 276 dev = (u_long)cookie; 277 #ifdef DIAGNOSTIC 278 /* XXX check cookie. */ 279 #endif 280 281 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 282 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 283 284 /* Enable interrupts for the device. */ 285 for (i = 0; i < ioasic_ndevs; i++) 286 if (ioasic_devs[i].iad_cookie == cookie) 287 break; 288 if (i == ioasic_ndevs) 289 panic("ioasic_intr_disestablish: invalid cookie."); 290 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 291 ~ioasic_devs[i].iad_intrbits; 292 tc_mb(); 293 294 ioasicintrs[dev].iai_func = ioasic_intrnull; 295 ioasicintrs[dev].iai_arg = (void *)dev; 296 } 297 298 int 299 ioasic_intrnull(val) 300 void *val; 301 { 302 303 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 304 (u_long)val); 305 } 306 307 /* 308 * asic_intr -- 309 * ASIC interrupt handler. 310 */ 311 int 312 ioasic_intr(val) 313 void *val; 314 { 315 register struct ioasic_softc *sc = val; 316 register int ifound; 317 int gifound; 318 u_int32_t sir; 319 volatile u_int32_t *sirp; 320 321 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 322 323 gifound = 0; 324 do { 325 ifound = 0; 326 tc_syncbus(); 327 328 sir = *sirp; 329 330 #ifdef EVCNT_COUNTERS 331 /* No interrupt counting via evcnt counters */ 332 XXX BREAK HERE XXX 333 #else /* !EVCNT_COUNTERS */ 334 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 335 #endif /* EVCNT_COUNTERS */ 336 337 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 338 #define CHECKINTR(slot, bits) \ 339 if (sir & bits) { \ 340 ifound = 1; \ 341 INCRINTRCNT(slot); \ 342 (*ioasicintrs[slot].iai_func) \ 343 (ioasicintrs[slot].iai_arg); \ 344 } 345 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 346 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 347 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 348 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 349 350 gifound |= ifound; 351 } while (ifound); 352 353 return (gifound); 354 } 355 356 /* XXX */ 357 char * 358 ioasic_lance_ether_address() 359 { 360 361 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 362 } 363 364 void 365 ioasic_lance_dma_setup(sc) 366 struct ioasic_softc *sc; 367 { 368 bus_dma_tag_t dmat = sc->sc_dmat; 369 bus_dma_segment_t seg; 370 volatile u_int32_t *ldp; 371 tc_addr_t tca; 372 int rseg; 373 374 /* 375 * Allocate a DMA area for the chip. 376 */ 377 if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, 378 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 379 printf("%s: can't allocate DMA area for LANCE\n", 380 sc->sc_dv.dv_xname); 381 return; 382 } 383 if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, 384 &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 385 printf("%s: can't map DMA area for LANCE\n", 386 sc->sc_dv.dv_xname); 387 bus_dmamem_free(dmat, &seg, rseg); 388 return; 389 } 390 391 /* 392 * Create and load the DMA map for the DMA area. 393 */ 394 if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, 395 LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) { 396 printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname); 397 goto bad; 398 } 399 if (bus_dmamap_load(dmat, sc->sc_lance_dmam, 400 le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { 401 printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname); 402 goto bad; 403 } 404 405 tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr; 406 if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) { 407 printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname); 408 bus_dmamap_unload(dmat, sc->sc_lance_dmam); 409 goto bad; 410 } 411 412 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 413 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 414 tc_wmb(); 415 416 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 417 IOASIC_CSR_DMAEN_LANCE; 418 tc_mb(); 419 return; 420 421 bad: 422 bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); 423 bus_dmamem_free(dmat, &seg, rseg); 424 le_iomem = 0; 425 } 426
Indexes created Mon Oct 27 04:09:48 GMT 2025