ioasic.c revision 1.23
1 /* $NetBSD: ioasic.c,v 1.23 1999/03/17 18:28:11 ross Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.23 1999/03/17 18:28:11 ross Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <alpha/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 /* Definition of the driver for autoconfig. */ 91 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 92 void ioasicattach __P((struct device *, struct device *, void *)); 93 94 struct cfattach ioasic_ca = { 95 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 96 }; 97 98 int ioasic_intr __P((void *)); 99 int ioasic_intrnull __P((void *)); 100 101 #define C(x) ((void *)(x)) 102 103 #define IOASIC_DEV_LANCE 0 104 #define IOASIC_DEV_SCC0 1 105 #define IOASIC_DEV_SCC1 2 106 #define IOASIC_DEV_ISDN 3 107 108 #define IOASIC_DEV_BOGUS -1 109 110 #define IOASIC_NCOOKIES 4 111 112 struct ioasic_dev ioasic_devs[] = { 113 /* XXX lance name */ 114 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 115 IOASIC_INTR_LANCE, }, 116 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 117 IOASIC_INTR_SCC_0, }, 118 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 119 IOASIC_INTR_SCC_1, }, 120 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 121 0, }, 122 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 123 IOASIC_INTR_ISDN, }, 124 }; 125 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 126 127 struct ioasicintr { 128 int (*iai_func) __P((void *)); 129 void *iai_arg; 130 } ioasicintrs[IOASIC_NCOOKIES]; 131 132 tc_addr_t ioasic_base; /* XXX XXX XXX */ 133 134 /* There can be only one. */ 135 int ioasicfound; 136 137 extern int cputype; 138 139 /* 140 * DMA area for IOASIC LANCE. 141 * XXX Should be done differently, but this is better than it used to be. 142 */ 143 #define LE_IOASIC_MEMSIZE (128*1024) 144 #define LE_IOASIC_MEMALIGN (128*1024) 145 caddr_t le_iomem; 146 147 void ioasic_lance_dma_setup __P((struct ioasic_softc *)); 148 149 int 150 ioasicmatch(parent, cfdata, aux) 151 struct device *parent; 152 struct cfdata *cfdata; 153 void *aux; 154 { 155 struct tc_attach_args *ta = aux; 156 157 /* Make sure that we're looking for this type of device. */ 158 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 159 return (0); 160 161 /* Check that it can actually exist. */ 162 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 163 panic("ioasicmatch: how did we get here?"); 164 165 if (ioasicfound) 166 return (0); 167 168 return (1); 169 } 170 171 void 172 ioasicattach(parent, self, aux) 173 struct device *parent, *self; 174 void *aux; 175 { 176 struct ioasic_softc *sc = (struct ioasic_softc *)self; 177 struct tc_attach_args *ta = aux; 178 struct ioasicdev_attach_args ioasicdev; 179 u_long i; 180 181 ioasicfound = 1; 182 183 sc->sc_base = ta->ta_addr; 184 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 185 sc->sc_cookie = ta->ta_cookie; 186 sc->sc_dmat = ta->ta_dmat; 187 188 #ifdef DEC_3000_300 189 if (cputype == ST_DEC_3000_300) { 190 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 191 IOASIC_CSR_FASTMODE; 192 tc_mb(); 193 printf(": slow mode\n"); 194 } else 195 #endif 196 printf(": fast mode\n"); 197 198 /* 199 * Turn off all device interrupt bits. 200 * (This does _not_ include 3000/300 TC option slot bits. 201 */ 202 for (i = 0; i < ioasic_ndevs; i++) 203 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 204 ~ioasic_devs[i].iad_intrbits; 205 tc_mb(); 206 207 /* 208 * Set up interrupt handlers. 209 */ 210 for (i = 0; i < IOASIC_NCOOKIES; i++) { 211 ioasicintrs[i].iai_func = ioasic_intrnull; 212 ioasicintrs[i].iai_arg = (void *)i; 213 } 214 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 215 216 /* 217 * Set up the LANCE DMA area. 218 */ 219 ioasic_lance_dma_setup(sc); 220 221 /* 222 * Try to configure each device. 223 */ 224 for (i = 0; i < ioasic_ndevs; i++) { 225 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 226 TC_ROM_LLEN); 227 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 228 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 229 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 230 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 231 232 /* Tell the autoconfig machinery we've found the hardware. */ 233 config_found(self, &ioasicdev, ioasicprint); 234 } 235 } 236 237 void 238 ioasic_intr_establish(ioa, cookie, level, func, arg) 239 struct device *ioa; 240 void *cookie, *arg; 241 tc_intrlevel_t level; 242 int (*func) __P((void *)); 243 { 244 u_long dev, i; 245 246 dev = (u_long)cookie; 247 #ifdef DIAGNOSTIC 248 /* XXX check cookie. */ 249 #endif 250 251 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 252 panic("ioasic_intr_establish: cookie %lu twice", dev); 253 254 ioasicintrs[dev].iai_func = func; 255 ioasicintrs[dev].iai_arg = arg; 256 257 /* Enable interrupts for the device. */ 258 for (i = 0; i < ioasic_ndevs; i++) 259 if (ioasic_devs[i].iad_cookie == cookie) 260 break; 261 if (i == ioasic_ndevs) 262 panic("ioasic_intr_establish: invalid cookie."); 263 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 264 ioasic_devs[i].iad_intrbits; 265 tc_mb(); 266 } 267 268 void 269 ioasic_intr_disestablish(ioa, cookie) 270 struct device *ioa; 271 void *cookie; 272 { 273 u_long dev, i; 274 275 dev = (u_long)cookie; 276 #ifdef DIAGNOSTIC 277 /* XXX check cookie. */ 278 #endif 279 280 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 281 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 282 283 /* Enable interrupts for the device. */ 284 for (i = 0; i < ioasic_ndevs; i++) 285 if (ioasic_devs[i].iad_cookie == cookie) 286 break; 287 if (i == ioasic_ndevs) 288 panic("ioasic_intr_disestablish: invalid cookie."); 289 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 290 ~ioasic_devs[i].iad_intrbits; 291 tc_mb(); 292 293 ioasicintrs[dev].iai_func = ioasic_intrnull; 294 ioasicintrs[dev].iai_arg = (void *)dev; 295 } 296 297 int 298 ioasic_intrnull(val) 299 void *val; 300 { 301 302 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 303 (u_long)val); 304 } 305 306 /* 307 * asic_intr -- 308 * ASIC interrupt handler. 309 */ 310 int 311 ioasic_intr(val) 312 void *val; 313 { 314 register struct ioasic_softc *sc = val; 315 register int ifound; 316 int gifound; 317 u_int32_t sir; 318 volatile u_int32_t *sirp; 319 320 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 321 322 gifound = 0; 323 do { 324 ifound = 0; 325 tc_syncbus(); 326 327 sir = *sirp; 328 329 #ifdef EVCNT_COUNTERS 330 /* No interrupt counting via evcnt counters */ 331 XXX BREAK HERE XXX 332 #else /* !EVCNT_COUNTERS */ 333 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 334 #endif /* EVCNT_COUNTERS */ 335 336 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 337 #define CHECKINTR(slot, bits) \ 338 if (sir & bits) { \ 339 ifound = 1; \ 340 INCRINTRCNT(slot); \ 341 (*ioasicintrs[slot].iai_func) \ 342 (ioasicintrs[slot].iai_arg); \ 343 } 344 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 345 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 346 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 347 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 348 349 gifound |= ifound; 350 } while (ifound); 351 352 return (gifound); 353 } 354 355 /* XXX */ 356 char * 357 ioasic_lance_ether_address() 358 { 359 360 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 361 } 362 363 void 364 ioasic_lance_dma_setup(sc) 365 struct ioasic_softc *sc; 366 { 367 bus_dma_tag_t dmat = sc->sc_dmat; 368 bus_dma_segment_t seg; 369 volatile u_int32_t *ldp; 370 tc_addr_t tca; 371 int rseg; 372 373 /* 374 * Allocate a DMA area for the chip. 375 */ 376 if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, 377 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 378 printf("%s: can't allocate DMA area for LANCE\n", 379 sc->sc_dv.dv_xname); 380 return; 381 } 382 if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, 383 &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 384 printf("%s: can't map DMA area for LANCE\n", 385 sc->sc_dv.dv_xname); 386 bus_dmamem_free(dmat, &seg, rseg); 387 return; 388 } 389 390 /* 391 * Create and load the DMA map for the DMA area. 392 */ 393 if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, 394 LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) { 395 printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname); 396 goto bad; 397 } 398 if (bus_dmamap_load(dmat, sc->sc_lance_dmam, 399 le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { 400 printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname); 401 goto bad; 402 } 403 404 tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr; 405 if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) { 406 printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname); 407 bus_dmamap_unload(dmat, sc->sc_lance_dmam); 408 goto bad; 409 } 410 411 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 412 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 413 tc_wmb(); 414 415 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 416 IOASIC_CSR_DMAEN_LANCE; 417 tc_mb(); 418 return; 419 420 bad: 421 bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); 422 bus_dmamem_free(dmat, &seg, rseg); 423 le_iomem = 0; 424 } 425
Indexes created Mon Oct 27 04:09:48 GMT 2025