ioasic.c revision 1.24
1 /* $NetBSD: ioasic.c,v 1.24 1999/04/10 01:21:38 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.24 1999/04/10 01:21:38 cgd Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <alpha/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 /* Definition of the driver for autoconfig. */ 91 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 92 void ioasicattach __P((struct device *, struct device *, void *)); 93 94 struct cfattach ioasic_ca = { 95 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 96 }; 97 98 int ioasic_intr __P((void *)); 99 int ioasic_intrnull __P((void *)); 100 101 #define C(x) ((void *)(x)) 102 103 #define IOASIC_DEV_LANCE 0 104 #define IOASIC_DEV_SCC0 1 105 #define IOASIC_DEV_SCC1 2 106 #define IOASIC_DEV_ISDN 3 107 108 #define IOASIC_DEV_BOGUS -1 109 110 #define IOASIC_NCOOKIES 4 111 112 struct ioasic_dev ioasic_devs[] = { 113 /* XXX lance name */ 114 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 115 IOASIC_INTR_LANCE, }, 116 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 117 IOASIC_INTR_SCC_0, }, 118 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 119 IOASIC_INTR_SCC_1, }, 120 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 121 0, }, 122 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 123 IOASIC_INTR_ISDN, }, 124 }; 125 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 126 127 struct ioasicintr { 128 int (*iai_func) __P((void *)); 129 void *iai_arg; 130 } ioasicintrs[IOASIC_NCOOKIES]; 131 132 tc_addr_t ioasic_base; /* XXX XXX XXX */ 133 134 /* There can be only one. */ 135 int ioasicfound; 136 137 /* 138 * DMA area for IOASIC LANCE. 139 * XXX Should be done differently, but this is better than it used to be. 140 */ 141 #define LE_IOASIC_MEMSIZE (128*1024) 142 #define LE_IOASIC_MEMALIGN (128*1024) 143 caddr_t le_iomem; 144 145 void ioasic_lance_dma_setup __P((struct ioasic_softc *)); 146 147 int 148 ioasicmatch(parent, cfdata, aux) 149 struct device *parent; 150 struct cfdata *cfdata; 151 void *aux; 152 { 153 struct tc_attach_args *ta = aux; 154 155 /* Make sure that we're looking for this type of device. */ 156 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 157 return (0); 158 159 /* Check that it can actually exist. */ 160 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 161 panic("ioasicmatch: how did we get here?"); 162 163 if (ioasicfound) 164 return (0); 165 166 return (1); 167 } 168 169 void 170 ioasicattach(parent, self, aux) 171 struct device *parent, *self; 172 void *aux; 173 { 174 struct ioasic_softc *sc = (struct ioasic_softc *)self; 175 struct tc_attach_args *ta = aux; 176 struct ioasicdev_attach_args ioasicdev; 177 u_long i; 178 179 ioasicfound = 1; 180 181 sc->sc_base = ta->ta_addr; 182 ioasic_base = sc->sc_base; /* XXX XXX XXX */ 183 sc->sc_cookie = ta->ta_cookie; 184 sc->sc_dmat = ta->ta_dmat; 185 186 #ifdef DEC_3000_300 187 if (cputype == ST_DEC_3000_300) { 188 *(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |= 189 IOASIC_CSR_FASTMODE; 190 tc_mb(); 191 printf(": slow mode\n"); 192 } else 193 #endif 194 printf(": fast mode\n"); 195 196 /* 197 * Turn off all device interrupt bits. 198 * (This does _not_ include 3000/300 TC option slot bits. 199 */ 200 for (i = 0; i < ioasic_ndevs; i++) 201 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 202 ~ioasic_devs[i].iad_intrbits; 203 tc_mb(); 204 205 /* 206 * Set up interrupt handlers. 207 */ 208 for (i = 0; i < IOASIC_NCOOKIES; i++) { 209 ioasicintrs[i].iai_func = ioasic_intrnull; 210 ioasicintrs[i].iai_arg = (void *)i; 211 } 212 tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc); 213 214 /* 215 * Set up the LANCE DMA area. 216 */ 217 ioasic_lance_dma_setup(sc); 218 219 /* 220 * Try to configure each device. 221 */ 222 for (i = 0; i < ioasic_ndevs; i++) { 223 strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname, 224 TC_ROM_LLEN); 225 ioasicdev.iada_modname[TC_ROM_LLEN] = '\0'; 226 ioasicdev.iada_offset = ioasic_devs[i].iad_offset; 227 ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; 228 ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie; 229 230 /* Tell the autoconfig machinery we've found the hardware. */ 231 config_found(self, &ioasicdev, ioasicprint); 232 } 233 } 234 235 void 236 ioasic_intr_establish(ioa, cookie, level, func, arg) 237 struct device *ioa; 238 void *cookie, *arg; 239 tc_intrlevel_t level; 240 int (*func) __P((void *)); 241 { 242 u_long dev, i; 243 244 dev = (u_long)cookie; 245 #ifdef DIAGNOSTIC 246 /* XXX check cookie. */ 247 #endif 248 249 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 250 panic("ioasic_intr_establish: cookie %lu twice", dev); 251 252 ioasicintrs[dev].iai_func = func; 253 ioasicintrs[dev].iai_arg = arg; 254 255 /* Enable interrupts for the device. */ 256 for (i = 0; i < ioasic_ndevs; i++) 257 if (ioasic_devs[i].iad_cookie == cookie) 258 break; 259 if (i == ioasic_ndevs) 260 panic("ioasic_intr_establish: invalid cookie."); 261 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |= 262 ioasic_devs[i].iad_intrbits; 263 tc_mb(); 264 } 265 266 void 267 ioasic_intr_disestablish(ioa, cookie) 268 struct device *ioa; 269 void *cookie; 270 { 271 u_long dev, i; 272 273 dev = (u_long)cookie; 274 #ifdef DIAGNOSTIC 275 /* XXX check cookie. */ 276 #endif 277 278 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 279 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 280 281 /* Enable interrupts for the device. */ 282 for (i = 0; i < ioasic_ndevs; i++) 283 if (ioasic_devs[i].iad_cookie == cookie) 284 break; 285 if (i == ioasic_ndevs) 286 panic("ioasic_intr_disestablish: invalid cookie."); 287 *(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &= 288 ~ioasic_devs[i].iad_intrbits; 289 tc_mb(); 290 291 ioasicintrs[dev].iai_func = ioasic_intrnull; 292 ioasicintrs[dev].iai_arg = (void *)dev; 293 } 294 295 int 296 ioasic_intrnull(val) 297 void *val; 298 { 299 300 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 301 (u_long)val); 302 } 303 304 /* 305 * asic_intr -- 306 * ASIC interrupt handler. 307 */ 308 int 309 ioasic_intr(val) 310 void *val; 311 { 312 register struct ioasic_softc *sc = val; 313 register int ifound; 314 int gifound; 315 u_int32_t sir; 316 volatile u_int32_t *sirp; 317 318 sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base); 319 320 gifound = 0; 321 do { 322 ifound = 0; 323 tc_syncbus(); 324 325 sir = *sirp; 326 327 #ifdef EVCNT_COUNTERS 328 /* No interrupt counting via evcnt counters */ 329 XXX BREAK HERE XXX 330 #else /* !EVCNT_COUNTERS */ 331 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 332 #endif /* EVCNT_COUNTERS */ 333 334 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 335 #define CHECKINTR(slot, bits) \ 336 if (sir & bits) { \ 337 ifound = 1; \ 338 INCRINTRCNT(slot); \ 339 (*ioasicintrs[slot].iai_func) \ 340 (ioasicintrs[slot].iai_arg); \ 341 } 342 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 343 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 344 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 345 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN); 346 347 gifound |= ifound; 348 } while (ifound); 349 350 return (gifound); 351 } 352 353 /* XXX */ 354 char * 355 ioasic_lance_ether_address() 356 { 357 358 return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base); 359 } 360 361 void 362 ioasic_lance_dma_setup(sc) 363 struct ioasic_softc *sc; 364 { 365 bus_dma_tag_t dmat = sc->sc_dmat; 366 bus_dma_segment_t seg; 367 volatile u_int32_t *ldp; 368 tc_addr_t tca; 369 int rseg; 370 371 /* 372 * Allocate a DMA area for the chip. 373 */ 374 if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, 375 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 376 printf("%s: can't allocate DMA area for LANCE\n", 377 sc->sc_dv.dv_xname); 378 return; 379 } 380 if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, 381 &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 382 printf("%s: can't map DMA area for LANCE\n", 383 sc->sc_dv.dv_xname); 384 bus_dmamem_free(dmat, &seg, rseg); 385 return; 386 } 387 388 /* 389 * Create and load the DMA map for the DMA area. 390 */ 391 if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, 392 LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) { 393 printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname); 394 goto bad; 395 } 396 if (bus_dmamap_load(dmat, sc->sc_lance_dmam, 397 le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { 398 printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname); 399 goto bad; 400 } 401 402 tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr; 403 if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) { 404 printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname); 405 bus_dmamap_unload(dmat, sc->sc_lance_dmam); 406 goto bad; 407 } 408 409 ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base); 410 *ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f); 411 tc_wmb(); 412 413 *(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |= 414 IOASIC_CSR_DMAEN_LANCE; 415 tc_mb(); 416 return; 417 418 bad: 419 bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); 420 bus_dmamem_free(dmat, &seg, rseg); 421 le_iomem = 0; 422 } 423
Indexes created Wed Oct 22 13:09:56 GMT 2025