ioasic.c revision 1.30
1 /* $NetBSD: ioasic.c,v 1.30 2000/05/28 06:07:31 gmcgarry Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.30 2000/05/28 06:07:31 gmcgarry Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/autoconf.h> 79 #include <machine/bus.h> 80 #include <machine/pte.h> 81 #include <machine/rpb.h> 82 #ifndef EVCNT_COUNTERS 83 #include <machine/intrcnt.h> 84 #endif 85 86 #include <dev/tc/tcvar.h> 87 #include <dev/tc/ioasicreg.h> 88 #include <dev/tc/ioasicvar.h> 89 90 /* Definition of the driver for autoconfig. */ 91 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 92 void ioasicattach __P((struct device *, struct device *, void *)); 93 94 struct cfattach ioasic_ca = { 95 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 96 }; 97 98 int ioasic_intr __P((void *)); 99 int ioasic_intrnull __P((void *)); 100 101 #define C(x) ((void *)(x)) 102 103 #define IOASIC_DEV_LANCE 0 104 #define IOASIC_DEV_SCC0 1 105 #define IOASIC_DEV_SCC1 2 106 #define IOASIC_DEV_ISDN 3 107 108 #define IOASIC_DEV_BOGUS -1 109 110 #define IOASIC_NCOOKIES 4 111 112 struct ioasic_dev ioasic_devs[] = { 113 /* XXX lance name */ 114 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 115 IOASIC_INTR_LANCE, }, 116 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 117 IOASIC_INTR_SCC_0, }, 118 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 119 IOASIC_INTR_SCC_1, }, 120 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 121 0, }, 122 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 123 IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD, }, 124 }; 125 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 126 127 struct ioasicintr { 128 int (*iai_func) __P((void *)); 129 void *iai_arg; 130 } ioasicintrs[IOASIC_NCOOKIES]; 131 132 tc_addr_t ioasic_base; /* XXX XXX XXX */ 133 134 /* There can be only one. */ 135 int ioasicfound; 136 137 int 138 ioasicmatch(parent, cfdata, aux) 139 struct device *parent; 140 struct cfdata *cfdata; 141 void *aux; 142 { 143 struct tc_attach_args *ta = aux; 144 145 /* Make sure that we're looking for this type of device. */ 146 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 147 return (0); 148 149 /* Check that it can actually exist. */ 150 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 151 panic("ioasicmatch: how did we get here?"); 152 153 if (ioasicfound) 154 return (0); 155 156 return (1); 157 } 158 159 void 160 ioasicattach(parent, self, aux) 161 struct device *parent, *self; 162 void *aux; 163 { 164 struct ioasic_softc *sc = (struct ioasic_softc *)self; 165 struct tc_attach_args *ta = aux; 166 #ifdef DEC_3000_300 167 u_long ssr; 168 #endif 169 u_long i, imsk; 170 171 ioasicfound = 1; 172 173 sc->sc_bst = ta->ta_memt; 174 if (bus_space_map(ta->ta_memt, ta->ta_addr, 175 0x400000, 0, &sc->sc_bsh)) { 176 printf("%s: unable to map device\n", sc->sc_dv.dv_xname); 177 return; 178 } 179 sc->sc_dmat = ta->ta_dmat; 180 181 ioasic_base = sc->sc_base = ta->ta_addr; /* XXX XXX XXX */ 182 183 #ifdef DEC_3000_300 184 if (cputype == ST_DEC_3000_300) { 185 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 186 ssr |= IOASIC_CSR_FASTMODE; 187 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 188 printf(": slow mode\n"); 189 } else 190 #endif 191 printf(": fast mode\n"); 192 193 /* 194 * Turn off all device interrupt bits. 195 * (This does _not_ include 3000/300 TC option slot bits. 196 */ 197 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 198 for (i = 0; i < ioasic_ndevs; i++) 199 imsk &= ~ioasic_devs[i].iad_intrbits; 200 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 201 202 /* 203 * Set up interrupt handlers. 204 */ 205 for (i = 0; i < IOASIC_NCOOKIES; i++) { 206 ioasicintrs[i].iai_func = ioasic_intrnull; 207 ioasicintrs[i].iai_arg = (void *)i; 208 } 209 tc_intr_establish(parent, ta->ta_cookie, TC_IPL_NONE, ioasic_intr, sc); 210 211 /* 212 * Try to configure each device. 213 */ 214 ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs); 215 } 216 217 void 218 ioasic_intr_establish(ioa, cookie, level, func, arg) 219 struct device *ioa; 220 void *cookie, *arg; 221 tc_intrlevel_t level; 222 int (*func) __P((void *)); 223 { 224 struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0]; 225 u_long dev, i, imsk; 226 227 dev = (u_long)cookie; 228 #ifdef DIAGNOSTIC 229 /* XXX check cookie. */ 230 #endif 231 232 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 233 panic("ioasic_intr_establish: cookie %lu twice", dev); 234 235 ioasicintrs[dev].iai_func = func; 236 ioasicintrs[dev].iai_arg = arg; 237 238 /* Enable interrupts for the device. */ 239 for (i = 0; i < ioasic_ndevs; i++) 240 if (ioasic_devs[i].iad_cookie == cookie) 241 break; 242 if (i == ioasic_ndevs) 243 panic("ioasic_intr_establish: invalid cookie."); 244 245 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 246 imsk |= ioasic_devs[i].iad_intrbits; 247 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 248 } 249 250 void 251 ioasic_intr_disestablish(ioa, cookie) 252 struct device *ioa; 253 void *cookie; 254 { 255 struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0]; 256 u_long dev, i, imsk; 257 258 dev = (u_long)cookie; 259 #ifdef DIAGNOSTIC 260 /* XXX check cookie. */ 261 #endif 262 263 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 264 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 265 266 /* Enable interrupts for the device. */ 267 for (i = 0; i < ioasic_ndevs; i++) 268 if (ioasic_devs[i].iad_cookie == cookie) 269 break; 270 if (i == ioasic_ndevs) 271 panic("ioasic_intr_disestablish: invalid cookie."); 272 273 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 274 imsk &= ~ioasic_devs[i].iad_intrbits; 275 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 276 277 ioasicintrs[dev].iai_func = ioasic_intrnull; 278 ioasicintrs[dev].iai_arg = (void *)dev; 279 } 280 281 int 282 ioasic_intrnull(val) 283 void *val; 284 { 285 286 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 287 (u_long)val); 288 } 289 290 /* 291 * ASIC interrupt handler. 292 */ 293 int 294 ioasic_intr(val) 295 void *val; 296 { 297 register struct ioasic_softc *sc = val; 298 register int ifound; 299 int gifound; 300 u_int32_t sir; 301 302 gifound = 0; 303 do { 304 ifound = 0; 305 tc_syncbus(); 306 307 sir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR); 308 309 #ifdef EVCNT_COUNTERS 310 /* No interrupt counting via evcnt counters */ 311 XXX BREAK HERE XXX 312 #else /* !EVCNT_COUNTERS */ 313 #define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++ 314 #endif /* EVCNT_COUNTERS */ 315 316 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 317 #define CHECKINTR(slot, bits) \ 318 if (sir & bits) { \ 319 ifound = 1; \ 320 INCRINTRCNT(slot); \ 321 (*ioasicintrs[slot].iai_func) \ 322 (ioasicintrs[slot].iai_arg); \ 323 } 324 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 325 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 326 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 327 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD); 328 329 gifound |= ifound; 330 } while (ifound); 331 332 return (gifound); 333 } 334
Indexes created Tue Sep 30 11:09:46 GMT 2025