ioasic.c revision 1.32
1 /* $NetBSD: ioasic.c,v 1.32 2000/06/05 21:47:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Keith Bostic, Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include "opt_dec_3000_300.h" 68 69 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 70 71 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.32 2000/06/05 21:47:30 thorpej Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/kernel.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 79 #include <machine/autoconf.h> 80 #include <machine/bus.h> 81 #include <machine/pte.h> 82 #include <machine/rpb.h> 83 84 #include <dev/tc/tcvar.h> 85 #include <dev/tc/ioasicreg.h> 86 #include <dev/tc/ioasicvar.h> 87 88 /* Definition of the driver for autoconfig. */ 89 int ioasicmatch __P((struct device *, struct cfdata *, void *)); 90 void ioasicattach __P((struct device *, struct device *, void *)); 91 92 struct cfattach ioasic_ca = { 93 sizeof(struct ioasic_softc), ioasicmatch, ioasicattach, 94 }; 95 96 int ioasic_intr __P((void *)); 97 int ioasic_intrnull __P((void *)); 98 99 #define C(x) ((void *)(x)) 100 101 #define IOASIC_DEV_LANCE 0 102 #define IOASIC_DEV_SCC0 1 103 #define IOASIC_DEV_SCC1 2 104 #define IOASIC_DEV_ISDN 3 105 106 #define IOASIC_DEV_BOGUS -1 107 108 #define IOASIC_NCOOKIES 4 109 110 struct ioasic_dev ioasic_devs[] = { 111 /* XXX lance name */ 112 { "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 113 IOASIC_INTR_LANCE, }, 114 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 115 IOASIC_INTR_SCC_0, }, 116 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 117 IOASIC_INTR_SCC_1, }, 118 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 119 0, }, 120 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 121 IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD, }, 122 }; 123 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 124 125 struct ioasicintr { 126 int (*iai_func) __P((void *)); 127 void *iai_arg; 128 struct evcnt iai_evcnt; 129 } ioasicintrs[IOASIC_NCOOKIES]; 130 131 tc_addr_t ioasic_base; /* XXX XXX XXX */ 132 133 /* There can be only one. */ 134 int ioasicfound; 135 136 int 137 ioasicmatch(parent, cfdata, aux) 138 struct device *parent; 139 struct cfdata *cfdata; 140 void *aux; 141 { 142 struct tc_attach_args *ta = aux; 143 144 /* Make sure that we're looking for this type of device. */ 145 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 146 return (0); 147 148 /* Check that it can actually exist. */ 149 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 150 panic("ioasicmatch: how did we get here?"); 151 152 if (ioasicfound) 153 return (0); 154 155 return (1); 156 } 157 158 void 159 ioasicattach(parent, self, aux) 160 struct device *parent, *self; 161 void *aux; 162 { 163 struct ioasic_softc *sc = (struct ioasic_softc *)self; 164 struct tc_attach_args *ta = aux; 165 #ifdef DEC_3000_300 166 u_long ssr; 167 #endif 168 u_long i, imsk; 169 const struct evcnt *pevcnt; 170 char *cp; 171 172 ioasicfound = 1; 173 174 sc->sc_bst = ta->ta_memt; 175 if (bus_space_map(ta->ta_memt, ta->ta_addr, 176 0x400000, 0, &sc->sc_bsh)) { 177 printf("%s: unable to map device\n", sc->sc_dv.dv_xname); 178 return; 179 } 180 sc->sc_dmat = ta->ta_dmat; 181 182 ioasic_base = sc->sc_base = ta->ta_addr; /* XXX XXX XXX */ 183 184 #ifdef DEC_3000_300 185 if (cputype == ST_DEC_3000_300) { 186 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 187 ssr |= IOASIC_CSR_FASTMODE; 188 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 189 printf(": slow mode\n"); 190 } else 191 #endif 192 printf(": fast mode\n"); 193 194 /* 195 * Turn off all device interrupt bits. 196 * (This does _not_ include 3000/300 TC option slot bits. 197 */ 198 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 199 for (i = 0; i < ioasic_ndevs; i++) 200 imsk &= ~ioasic_devs[i].iad_intrbits; 201 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 202 203 /* 204 * Set up interrupt handlers. 205 */ 206 pevcnt = tc_intr_evcnt(parent, ta->ta_cookie); 207 for (i = 0; i < IOASIC_NCOOKIES; i++) { 208 ioasicintrs[i].iai_func = ioasic_intrnull; 209 ioasicintrs[i].iai_arg = (void *)i; 210 211 cp = malloc(12, M_DEVBUF, M_NOWAIT); 212 if (cp == NULL) 213 panic("ioasicattach"); 214 sprintf(cp, "slot %lu", i); 215 evcnt_attach_dynamic(&ioasicintrs[i].iai_evcnt, 216 EVCNT_TYPE_INTR, pevcnt, self->dv_xname, cp); 217 } 218 tc_intr_establish(parent, ta->ta_cookie, TC_IPL_NONE, ioasic_intr, sc); 219 220 /* 221 * Try to configure each device. 222 */ 223 ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs); 224 } 225 226 void 227 ioasic_intr_establish(ioa, cookie, level, func, arg) 228 struct device *ioa; 229 void *cookie, *arg; 230 tc_intrlevel_t level; 231 int (*func) __P((void *)); 232 { 233 struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0]; 234 u_long dev, i, imsk; 235 236 dev = (u_long)cookie; 237 #ifdef DIAGNOSTIC 238 /* XXX check cookie. */ 239 #endif 240 241 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 242 panic("ioasic_intr_establish: cookie %lu twice", dev); 243 244 ioasicintrs[dev].iai_func = func; 245 ioasicintrs[dev].iai_arg = arg; 246 247 /* Enable interrupts for the device. */ 248 for (i = 0; i < ioasic_ndevs; i++) 249 if (ioasic_devs[i].iad_cookie == cookie) 250 break; 251 if (i == ioasic_ndevs) 252 panic("ioasic_intr_establish: invalid cookie."); 253 254 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 255 imsk |= ioasic_devs[i].iad_intrbits; 256 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 257 } 258 259 void 260 ioasic_intr_disestablish(ioa, cookie) 261 struct device *ioa; 262 void *cookie; 263 { 264 struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0]; 265 u_long dev, i, imsk; 266 267 dev = (u_long)cookie; 268 #ifdef DIAGNOSTIC 269 /* XXX check cookie. */ 270 #endif 271 272 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 273 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 274 275 /* Enable interrupts for the device. */ 276 for (i = 0; i < ioasic_ndevs; i++) 277 if (ioasic_devs[i].iad_cookie == cookie) 278 break; 279 if (i == ioasic_ndevs) 280 panic("ioasic_intr_disestablish: invalid cookie."); 281 282 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 283 imsk &= ~ioasic_devs[i].iad_intrbits; 284 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 285 286 ioasicintrs[dev].iai_func = ioasic_intrnull; 287 ioasicintrs[dev].iai_arg = (void *)dev; 288 } 289 290 int 291 ioasic_intrnull(val) 292 void *val; 293 { 294 295 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n", 296 (u_long)val); 297 } 298 299 /* 300 * ASIC interrupt handler. 301 */ 302 int 303 ioasic_intr(val) 304 void *val; 305 { 306 register struct ioasic_softc *sc = val; 307 register int ifound; 308 int gifound; 309 u_int32_t sir; 310 311 gifound = 0; 312 do { 313 ifound = 0; 314 tc_syncbus(); 315 316 sir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR); 317 318 #define INCRINTRCNT(slot) ioasicintrs[slot].iai_evcnt.ev_count++ 319 320 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 321 #define CHECKINTR(slot, bits) \ 322 if (sir & (bits)) { \ 323 ifound = 1; \ 324 INCRINTRCNT(slot); \ 325 (*ioasicintrs[slot].iai_func) \ 326 (ioasicintrs[slot].iai_arg); \ 327 } 328 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0); 329 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1); 330 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE); 331 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD); 332 333 gifound |= ifound; 334 } while (ifound); 335 336 return (gifound); 337 } 338
Indexes created Tue Sep 30 07:10:03 GMT 2025