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ioasic.c revision 1.9 
      1 /*	$NetBSD: ioasic.c,v 1.9 1996/10/13 03:00:32 christos Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
      5  * All rights reserved.
      6  *
      7  * Author: Keith Bostic, Chris G. Demetriou
      8  *
      9  * Permission to use, copy, modify and distribute this software and
     10  * its documentation is hereby granted, provided that both the copyright
     11  * notice and this permission notice appear in all copies of the
     12  * software, derivative works or modified versions, and any portions
     13  * thereof, and that both notices appear in supporting documentation.
     14  *
     15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     18  *
     19  * Carnegie Mellon requests users of this software to return to
     20  *
     21  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     22  *  School of Computer Science
     23  *  Carnegie Mellon University
     24  *  Pittsburgh PA 15213-3890
     25  *
     26  * any improvements or extensions that they make and grant Carnegie the
     27  * rights to redistribute these changes.
     28  */
     29 
     30 #include <sys/param.h>
     31 #include <sys/kernel.h>
     32 #include <sys/systm.h>
     33 #include <sys/device.h>
     34 
     35 #include <machine/autoconf.h>
     36 #include <machine/pte.h>
     37 #include <machine/rpb.h>
     38 #ifndef EVCNT_COUNTERS
     39 #include <machine/intrcnt.h>
     40 #endif
     41 
     42 #include <dev/tc/tcvar.h>
     43 #include <alpha/tc/ioasicreg.h>
     44 #include <dev/tc/ioasicvar.h>
     45 
     46 struct ioasic_softc {
     47 	struct	device sc_dv;
     48 
     49 	tc_addr_t sc_base;
     50 	void	*sc_cookie;
     51 };
     52 
     53 /* Definition of the driver for autoconfig. */
     54 int	ioasicmatch __P((struct device *, void *, void *));
     55 void	ioasicattach __P((struct device *, struct device *, void *));
     56 int     ioasicprint(void *, const char *);
     57 
     58 struct cfattach ioasic_ca = {
     59 	sizeof(struct ioasic_softc), ioasicmatch, ioasicattach,
     60 };
     61 
     62 struct cfdriver ioasic_cd = {
     63 	NULL, "ioasic", DV_DULL,
     64 };
     65 
     66 int	ioasic_intr __P((void *));
     67 int	ioasic_intrnull __P((void *));
     68 
     69 #define	C(x)	((void *)(x))
     70 
     71 #define	IOASIC_DEV_LANCE	0
     72 #define	IOASIC_DEV_SCC0		1
     73 #define	IOASIC_DEV_SCC1		2
     74 #define	IOASIC_DEV_ISDN		3
     75 
     76 #define	IOASIC_DEV_BOGUS	-1
     77 
     78 #define	IOASIC_NCOOKIES		4
     79 
     80 struct ioasic_dev {
     81 	char		*iad_modname;
     82 	tc_offset_t	iad_offset;
     83 	void		*iad_cookie;
     84 	u_int32_t	iad_intrbits;
     85 } ioasic_devs[] = {
     86 	/* XXX lance name */
     87 	{ "lance",    0x000c0000, C(IOASIC_DEV_LANCE), IOASIC_INTR_LANCE, },
     88 	{ "z8530   ", 0x00100000, C(IOASIC_DEV_SCC0),  IOASIC_INTR_SCC_0, },
     89 	{ "z8530   ", 0x00180000, C(IOASIC_DEV_SCC1),  IOASIC_INTR_SCC_1, },
     90 	{ "TOY_RTC ", 0x00200000, C(IOASIC_DEV_BOGUS), 0,                 },
     91 	{ "AMD79c30", 0x00240000, C(IOASIC_DEV_ISDN),  IOASIC_INTR_ISDN,  },
     92 };
     93 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
     94 
     95 struct ioasicintr {
     96 	int	(*iai_func) __P((void *));
     97 	void	*iai_arg;
     98 } ioasicintrs[IOASIC_NCOOKIES];
     99 
    100 tc_addr_t ioasic_base;		/* XXX XXX XXX */
    101 
    102 /* There can be only one. */
    103 int ioasicfound;
    104 
    105 extern int cputype;
    106 
    107 int
    108 ioasicmatch(parent, cfdata, aux)
    109 	struct device *parent;
    110 	void *cfdata;
    111 	void *aux;
    112 {
    113 	struct tc_attach_args *ta = aux;
    114 
    115 	/* Make sure that we're looking for this type of device. */
    116 	if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN))
    117 		return (0);
    118 
    119 	/* Check that it can actually exist. */
    120 	if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300))
    121 		panic("ioasicmatch: how did we get here?");
    122 
    123 	if (ioasicfound)
    124 		return (0);
    125 
    126 	return (1);
    127 }
    128 
    129 void
    130 ioasicattach(parent, self, aux)
    131 	struct device *parent, *self;
    132 	void *aux;
    133 {
    134 	struct ioasic_softc *sc = (struct ioasic_softc *)self;
    135 	struct tc_attach_args *ta = aux;
    136 	struct ioasicdev_attach_args ioasicdev;
    137 	u_long i;
    138 
    139 	ioasicfound = 1;
    140 
    141 	sc->sc_base = ta->ta_addr;
    142 	ioasic_base = sc->sc_base;			/* XXX XXX XXX */
    143 	sc->sc_cookie = ta->ta_cookie;
    144 
    145 #ifdef DEC_3000_300
    146 	if (cputype == ST_DEC_3000_300) {
    147 		*(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |=
    148 		    IOASIC_CSR_FASTMODE;
    149 		tc_mb();
    150 		printf(": slow mode\n");
    151 	} else
    152 #endif
    153 		printf(": fast mode\n");
    154 
    155 	/*
    156 	 * Turn off all device interrupt bits.
    157 	 * (This does _not_ include 3000/300 TC option slot bits.
    158 	 */
    159 	for (i = 0; i < ioasic_ndevs; i++)
    160 		*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
    161 			~ioasic_devs[i].iad_intrbits;
    162 	tc_mb();
    163 
    164 	/*
    165 	 * Set up interrupt handlers.
    166 	 */
    167 	for (i = 0; i < IOASIC_NCOOKIES; i++) {
    168 		ioasicintrs[i].iai_func = ioasic_intrnull;
    169 		ioasicintrs[i].iai_arg = (void *)i;
    170 	}
    171 	tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc);
    172 
    173         /*
    174 	 * Try to configure each device.
    175 	 */
    176         for (i = 0; i < ioasic_ndevs; i++) {
    177 		strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname,
    178 			TC_ROM_LLEN);
    179 		ioasicdev.iada_modname[TC_ROM_LLEN] = '\0';
    180 		ioasicdev.iada_offset = ioasic_devs[i].iad_offset;
    181 		ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset;
    182 		ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie;
    183 
    184                 /* Tell the autoconfig machinery we've found the hardware. */
    185                 config_found(self, &ioasicdev, ioasicprint);
    186         }
    187 }
    188 
    189 int
    190 ioasicprint(aux, pnp)
    191 	void *aux;
    192 	const char *pnp;
    193 {
    194 	struct ioasicdev_attach_args *d = aux;
    195 
    196         if (pnp)
    197                 printf("%s at %s", d->iada_modname, pnp);
    198         printf(" offset 0x%lx", (long)d->iada_offset);
    199         return (UNCONF);
    200 }
    201 
    202 int
    203 ioasic_submatch(match, d)
    204 	struct cfdata *match;
    205 	struct ioasicdev_attach_args *d;
    206 {
    207 
    208 	return ((match->ioasiccf_offset == d->iada_offset) ||
    209 		(match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN));
    210 }
    211 
    212 void
    213 ioasic_intr_establish(ioa, cookie, level, func, arg)
    214 	struct device *ioa;
    215 	void *cookie, *arg;
    216 	tc_intrlevel_t level;
    217 	int (*func) __P((void *));
    218 {
    219 	u_long dev, i;
    220 
    221 	dev = (u_long)cookie;
    222 #ifdef DIAGNOSTIC
    223 	/* XXX check cookie. */
    224 #endif
    225 
    226 	if (ioasicintrs[dev].iai_func != ioasic_intrnull)
    227 		panic("ioasic_intr_establish: cookie %d twice", dev);
    228 
    229 	ioasicintrs[dev].iai_func = func;
    230 	ioasicintrs[dev].iai_arg = arg;
    231 
    232 	/* Enable interrupts for the device. */
    233 	for (i = 0; i < ioasic_ndevs; i++)
    234 		if (ioasic_devs[i].iad_cookie == cookie)
    235 			break;
    236 	if (i == ioasic_ndevs)
    237 		panic("ioasic_intr_establish: invalid cookie.");
    238 	*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |=
    239 		ioasic_devs[i].iad_intrbits;
    240 	tc_mb();
    241 }
    242 
    243 void
    244 ioasic_intr_disestablish(ioa, cookie)
    245 	struct device *ioa;
    246 	void *cookie;
    247 {
    248 	u_long dev, i;
    249 
    250 	dev = (u_long)cookie;
    251 #ifdef DIAGNOSTIC
    252 	/* XXX check cookie. */
    253 #endif
    254 
    255 	if (ioasicintrs[dev].iai_func == ioasic_intrnull)
    256 		panic("ioasic_intr_disestablish: cookie %d missing intr", dev);
    257 
    258 	/* Enable interrupts for the device. */
    259 	for (i = 0; i < ioasic_ndevs; i++)
    260 		if (ioasic_devs[i].iad_cookie == cookie)
    261 			break;
    262 	if (i == ioasic_ndevs)
    263 		panic("ioasic_intr_disestablish: invalid cookie.");
    264 	*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
    265 		~ioasic_devs[i].iad_intrbits;
    266 	tc_mb();
    267 
    268 	ioasicintrs[dev].iai_func = ioasic_intrnull;
    269 	ioasicintrs[dev].iai_arg = (void *)dev;
    270 }
    271 
    272 int
    273 ioasic_intrnull(val)
    274 	void *val;
    275 {
    276 
    277 	panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n",
    278 	    (u_long)val);
    279 }
    280 
    281 /*
    282  * asic_intr --
    283  *	ASIC interrupt handler.
    284  */
    285 int
    286 ioasic_intr(val)
    287 	void *val;
    288 {
    289 	register struct ioasic_softc *sc = val;
    290 	register int ifound;
    291 	int gifound;
    292 	u_int32_t sir;
    293 	volatile u_int32_t *sirp;
    294 
    295 	sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base);
    296 
    297 	gifound = 0;
    298 	do {
    299 		ifound = 0;
    300 		tc_syncbus();
    301 
    302 		sir = *sirp;
    303 
    304 #ifdef EVCNT_COUNTERS
    305 	/* No interrupt counting via evcnt counters */
    306 	XXX BREAK HERE XXX
    307 #else /* !EVCNT_COUNTERS */
    308 #define	INCRINTRCNT(slot)	intrcnt[INTRCNT_IOASIC + slot]++
    309 #endif /* EVCNT_COUNTERS */
    310 
    311 		/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
    312 #define	CHECKINTR(slot, bits)						\
    313 		if (sir & bits) {					\
    314 			ifound = 1;					\
    315 			INCRINTRCNT(slot);				\
    316 			(*ioasicintrs[slot].iai_func)			\
    317 			    (ioasicintrs[slot].iai_arg);		\
    318 		}
    319 		CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0);
    320 		CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1);
    321 		CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE);
    322 		CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN);
    323 
    324 		gifound |= ifound;
    325 	} while (ifound);
    326 
    327 	return (gifound);
    328 }
    329 
    330 /* XXX */
    331 char *
    332 ioasic_lance_ether_address()
    333 {
    334 
    335 	return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base);
    336 }
    337 
    338 void
    339 ioasic_lance_dma_setup(v)
    340 	void *v;
    341 {
    342 	volatile u_int32_t *ldp;
    343 	tc_addr_t tca;
    344 
    345 	tca = (tc_addr_t)v;
    346 
    347 	ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base);
    348 	*ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f);
    349 	tc_wmb();
    350 
    351 	*(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |=
    352 	    IOASIC_CSR_DMAEN_LANCE;
    353 	tc_mb();
    354 }
    355