tc_3000_300.c revision 1.25 1 1.25 thorpej /* $NetBSD: tc_3000_300.c,v 1.25 2000/06/05 21:47:30 thorpej Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.6 cgd * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.14 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.14 cgd
32 1.25 thorpej __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.25 2000/06/05 21:47:30 thorpej Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/param.h>
35 1.9 cgd #include <sys/systm.h>
36 1.1 cgd #include <sys/device.h>
37 1.25 thorpej #include <sys/malloc.h>
38 1.1 cgd
39 1.1 cgd #include <machine/autoconf.h>
40 1.1 cgd #include <machine/pte.h>
41 1.1 cgd
42 1.4 cgd #include <dev/tc/tcvar.h>
43 1.21 nisimura #include <dev/tc/ioasicreg.h>
44 1.4 cgd #include <alpha/tc/tc_conf.h>
45 1.1 cgd #include <alpha/tc/tc_3000_300.h>
46 1.17 briggs
47 1.19 drochner #include "wsdisplay.h"
48 1.17 briggs #include "sfb.h"
49 1.17 briggs
50 1.17 briggs #if NSFB > 0
51 1.23 nisimura extern int sfb_cnattach __P((tc_addr_t));
52 1.17 briggs #endif
53 1.1 cgd
54 1.4 cgd int tc_3000_300_intrnull __P((void *));
55 1.4 cgd
56 1.4 cgd #define C(x) ((void *)(u_long)x)
57 1.9 cgd #define KV(x) (ALPHA_PHYS_TO_K0SEG(x))
58 1.1 cgd
59 1.5 cgd /*
60 1.5 cgd * We have to read and modify the IOASIC registers directly, because
61 1.5 cgd * the TC option slot interrupt request and mask bits are stored there,
62 1.5 cgd * and the ioasic code isn't initted when we need to frob some interrupt
63 1.5 cgd * bits.
64 1.5 cgd */
65 1.5 cgd #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000)
66 1.5 cgd
67 1.4 cgd struct tc_slotdesc tc_3000_300_slots[] = {
68 1.4 cgd { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */
69 1.4 cgd { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */
70 1.22 nisimura { KV(0x140000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - unused */
71 1.22 nisimura { KV(0x160000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - unused */
72 1.22 nisimura { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 4 - TCDS ASIC */
73 1.22 nisimura { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 5 - IOCTL ASIC */
74 1.22 nisimura { KV(0x1c0000000), C(TC_3000_300_DEV_BOGUS), }, /* 6 - CXTurbo */
75 1.1 cgd };
76 1.4 cgd int tc_3000_300_nslots =
77 1.4 cgd sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]);
78 1.1 cgd
79 1.4 cgd struct tc_builtin tc_3000_300_builtins[] = {
80 1.22 nisimura { "PMAGB-BA", 6, 0x02000000, C(TC_3000_300_DEV_CXTURBO), },
81 1.22 nisimura { "FLAMG-IO", 5, 0x00000000, C(TC_3000_300_DEV_IOASIC), },
82 1.22 nisimura { "PMAZ-DS ", 4, 0x00000000, C(TC_3000_300_DEV_TCDS), },
83 1.1 cgd };
84 1.4 cgd int tc_3000_300_nbuiltins =
85 1.4 cgd sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]);
86 1.1 cgd
87 1.4 cgd struct tcintr {
88 1.4 cgd int (*tci_func) __P((void *));
89 1.4 cgd void *tci_arg;
90 1.25 thorpej struct evcnt tci_evcnt;
91 1.4 cgd } tc_3000_300_intr[TC_3000_300_NCOOKIES];
92 1.4 cgd
93 1.1 cgd void
94 1.1 cgd tc_3000_300_intr_setup()
95 1.1 cgd {
96 1.5 cgd volatile u_int32_t *imskp;
97 1.25 thorpej char *cp;
98 1.4 cgd u_long i;
99 1.1 cgd
100 1.4 cgd /*
101 1.5 cgd * Disable all interrupts that we can (can't disable builtins).
102 1.4 cgd */
103 1.21 nisimura imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
104 1.5 cgd *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1);
105 1.4 cgd
106 1.4 cgd /*
107 1.4 cgd * Set up interrupt handlers.
108 1.4 cgd */
109 1.4 cgd for (i = 0; i < TC_3000_300_NCOOKIES; i++) {
110 1.4 cgd tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull;
111 1.4 cgd tc_3000_300_intr[i].tci_arg = (void *)i;
112 1.25 thorpej
113 1.25 thorpej cp = malloc(12, M_DEVBUF, M_NOWAIT);
114 1.25 thorpej if (cp == NULL)
115 1.25 thorpej panic("tc_3000_300_intr_setup");
116 1.25 thorpej sprintf(cp, "slot %lu", i);
117 1.25 thorpej evcnt_attach_dynamic(&tc_3000_300_intr[i].tci_evcnt,
118 1.25 thorpej EVCNT_TYPE_INTR, NULL, "tc", cp);
119 1.2 cgd }
120 1.24 cgd }
121 1.24 cgd
122 1.24 cgd const struct evcnt *
123 1.24 cgd tc_3000_300_intr_evcnt(tcadev, cookie)
124 1.24 cgd struct device *tcadev;
125 1.24 cgd void *cookie;
126 1.24 cgd {
127 1.25 thorpej u_long dev = (u_long)cookie;
128 1.25 thorpej
129 1.25 thorpej #ifdef DIAGNOSTIC
130 1.25 thorpej /* XXX bounds-check cookie. */
131 1.25 thorpej #endif
132 1.24 cgd
133 1.25 thorpej return (&tc_3000_300_intr[dev].tci_evcnt);
134 1.1 cgd }
135 1.1 cgd
136 1.1 cgd void
137 1.4 cgd tc_3000_300_intr_establish(tcadev, cookie, level, func, arg)
138 1.4 cgd struct device *tcadev;
139 1.4 cgd void *cookie, *arg;
140 1.4 cgd tc_intrlevel_t level;
141 1.4 cgd int (*func) __P((void *));
142 1.1 cgd {
143 1.5 cgd volatile u_int32_t *imskp;
144 1.4 cgd u_long dev = (u_long)cookie;
145 1.1 cgd
146 1.1 cgd #ifdef DIAGNOSTIC
147 1.4 cgd /* XXX bounds-check cookie. */
148 1.1 cgd #endif
149 1.1 cgd
150 1.4 cgd if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull)
151 1.18 thorpej panic("tc_3000_300_intr_establish: cookie %lu twice", dev);
152 1.1 cgd
153 1.4 cgd tc_3000_300_intr[dev].tci_func = func;
154 1.4 cgd tc_3000_300_intr[dev].tci_arg = arg;
155 1.1 cgd
156 1.21 nisimura imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
157 1.4 cgd switch (dev) {
158 1.4 cgd case TC_3000_300_DEV_OPT0:
159 1.5 cgd *imskp |= IOASIC_INTR_300_OPT0;
160 1.4 cgd break;
161 1.4 cgd case TC_3000_300_DEV_OPT1:
162 1.5 cgd *imskp |= IOASIC_INTR_300_OPT1;
163 1.4 cgd break;
164 1.4 cgd default:
165 1.4 cgd /* interrupts for builtins always enabled */
166 1.4 cgd break;
167 1.4 cgd }
168 1.1 cgd }
169 1.1 cgd
170 1.1 cgd void
171 1.4 cgd tc_3000_300_intr_disestablish(tcadev, cookie)
172 1.4 cgd struct device *tcadev;
173 1.4 cgd void *cookie;
174 1.1 cgd {
175 1.5 cgd volatile u_int32_t *imskp;
176 1.4 cgd u_long dev = (u_long)cookie;
177 1.1 cgd
178 1.1 cgd #ifdef DIAGNOSTIC
179 1.4 cgd /* XXX bounds-check cookie. */
180 1.1 cgd #endif
181 1.1 cgd
182 1.4 cgd if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull)
183 1.18 thorpej panic("tc_3000_300_intr_disestablish: cookie %lu bad intr",
184 1.1 cgd dev);
185 1.1 cgd
186 1.21 nisimura imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
187 1.4 cgd switch (dev) {
188 1.4 cgd case TC_3000_300_DEV_OPT0:
189 1.5 cgd *imskp &= ~IOASIC_INTR_300_OPT0;
190 1.4 cgd break;
191 1.4 cgd case TC_3000_300_DEV_OPT1:
192 1.5 cgd *imskp &= ~IOASIC_INTR_300_OPT1;
193 1.4 cgd break;
194 1.4 cgd default:
195 1.4 cgd /* interrupts for builtins always enabled */
196 1.4 cgd break;
197 1.4 cgd }
198 1.1 cgd
199 1.4 cgd tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull;
200 1.4 cgd tc_3000_300_intr[dev].tci_arg = (void *)dev;
201 1.4 cgd }
202 1.4 cgd
203 1.4 cgd int
204 1.4 cgd tc_3000_300_intrnull(val)
205 1.4 cgd void *val;
206 1.4 cgd {
207 1.4 cgd
208 1.4 cgd panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n",
209 1.4 cgd (u_long)val);
210 1.1 cgd }
211 1.1 cgd
212 1.1 cgd void
213 1.1 cgd tc_3000_300_iointr(framep, vec)
214 1.2 cgd void *framep;
215 1.10 cgd unsigned long vec;
216 1.1 cgd {
217 1.7 cgd u_int32_t tcir, ioasicir, ioasicimr;
218 1.9 cgd int ifound;
219 1.1 cgd
220 1.1 cgd #ifdef DIAGNOSTIC
221 1.1 cgd int s;
222 1.1 cgd if (vec != 0x800)
223 1.10 cgd panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
224 1.1 cgd s = splhigh();
225 1.9 cgd if (s != ALPHA_PSL_IPL_IO)
226 1.9 cgd panic("INVALID ASSUMPTION: IPL %d, not %d", s,
227 1.9 cgd ALPHA_PSL_IPL_IO);
228 1.1 cgd splx(s);
229 1.1 cgd #endif
230 1.1 cgd
231 1.1 cgd do {
232 1.4 cgd tc_syncbus();
233 1.2 cgd
234 1.2 cgd /* find out what interrupts/errors occurred */
235 1.5 cgd tcir = *(volatile u_int32_t *)TC_3000_300_IR;
236 1.5 cgd ioasicir = *(volatile u_int32_t *)
237 1.21 nisimura (DEC_3000_300_IOASIC_ADDR + IOASIC_INTR);
238 1.7 cgd ioasicimr = *(volatile u_int32_t *)
239 1.21 nisimura (DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK);
240 1.4 cgd tc_mb();
241 1.2 cgd
242 1.7 cgd /* Ignore interrupts that aren't enabled out. */
243 1.7 cgd ioasicir &= ioasicimr;
244 1.7 cgd
245 1.2 cgd /* clear the interrupts/errors we found. */
246 1.5 cgd *(volatile u_int32_t *)TC_3000_300_IR = tcir;
247 1.4 cgd /* XXX can't clear TC option slot interrupts here? */
248 1.4 cgd tc_wmb();
249 1.1 cgd
250 1.1 cgd ifound = 0;
251 1.8 cgd
252 1.25 thorpej #define INCRINTRCNT(slot) tc_3000_300_intr[slot].tci_evcnt.ev_count++
253 1.8 cgd
254 1.4 cgd #define CHECKINTR(slot, flag) \
255 1.8 cgd if (flag) { \
256 1.1 cgd ifound = 1; \
257 1.8 cgd INCRINTRCNT(slot); \
258 1.4 cgd (*tc_3000_300_intr[slot].tci_func) \
259 1.4 cgd (tc_3000_300_intr[slot].tci_arg); \
260 1.1 cgd }
261 1.1 cgd /* Do them in order of priority; highest slot # first. */
262 1.5 cgd CHECKINTR(TC_3000_300_DEV_CXTURBO,
263 1.5 cgd tcir & TC_3000_300_IR_CXTURBO);
264 1.8 cgd CHECKINTR(TC_3000_300_DEV_IOASIC,
265 1.8 cgd (tcir & TC_3000_300_IR_IOASIC) &&
266 1.8 cgd (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0)));
267 1.5 cgd CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS);
268 1.5 cgd CHECKINTR(TC_3000_300_DEV_OPT1,
269 1.7 cgd ioasicir & IOASIC_INTR_300_OPT1);
270 1.7 cgd CHECKINTR(TC_3000_300_DEV_OPT0,
271 1.5 cgd ioasicir & IOASIC_INTR_300_OPT0);
272 1.1 cgd #undef CHECKINTR
273 1.1 cgd
274 1.1 cgd #ifdef DIAGNOSTIC
275 1.1 cgd #define PRINTINTR(msg, bits) \
276 1.5 cgd if (tcir & bits) \
277 1.12 christos printf(msg);
278 1.1 cgd PRINTINTR("BCache tag parity error\n",
279 1.1 cgd TC_3000_300_IR_BCTAGPARITY);
280 1.1 cgd PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN);
281 1.1 cgd PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT);
282 1.1 cgd PRINTINTR("Bcache parity error\n",
283 1.1 cgd TC_3000_300_IR_BCACHEPARITY);
284 1.1 cgd PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY);
285 1.1 cgd #undef PRINTINTR
286 1.1 cgd #endif
287 1.1 cgd } while (ifound);
288 1.16 briggs }
289 1.16 briggs
290 1.19 drochner #if NWSDISPLAY > 0
291 1.16 briggs /*
292 1.16 briggs * tc_3000_300_fb_cnattach --
293 1.16 briggs * Attempt to map the CTB output device to a slot and attach the
294 1.16 briggs * framebuffer as the output side of the console.
295 1.16 briggs */
296 1.16 briggs int
297 1.16 briggs tc_3000_300_fb_cnattach(turbo_slot)
298 1.16 briggs u_int64_t turbo_slot;
299 1.16 briggs {
300 1.16 briggs u_int32_t output_slot;
301 1.16 briggs
302 1.16 briggs output_slot = turbo_slot & 0xffffffff;
303 1.16 briggs
304 1.16 briggs if (output_slot >= tc_3000_300_nslots) {
305 1.20 drochner return EINVAL;
306 1.16 briggs }
307 1.16 briggs
308 1.16 briggs if (output_slot == 0) {
309 1.17 briggs #if NSFB > 0
310 1.16 briggs sfb_cnattach(KV(0x1c0000000) + 0x02000000);
311 1.20 drochner return 0;
312 1.17 briggs #else
313 1.20 drochner return ENXIO;
314 1.17 briggs #endif
315 1.16 briggs }
316 1.16 briggs
317 1.16 briggs return tc_fb_cnattach(tc_3000_300_slots[output_slot-1].tcs_addr);
318 1.1 cgd }
319 1.19 drochner #endif /* NWSDISPLAY */
320