tc_3000_300.c revision 1.14
1 /* $NetBSD: tc_3000_300.c,v 1.14 1997/04/07 23:40:57 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <machine/options.h> /* Config options headers */ 31 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 32 33 __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.14 1997/04/07 23:40:57 cgd Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 39 #include <machine/autoconf.h> 40 #include <machine/pte.h> 41 #ifndef EVCNT_COUNTERS 42 #include <machine/intrcnt.h> 43 #endif 44 45 #include <dev/tc/tcvar.h> 46 #include <alpha/tc/tc_conf.h> 47 #include <alpha/tc/tc_3000_300.h> 48 #include <alpha/tc/ioasicreg.h> 49 50 void tc_3000_300_intr_setup __P((void)); 51 void tc_3000_300_intr_establish __P((struct device *, void *, 52 tc_intrlevel_t, int (*)(void *), void *)); 53 void tc_3000_300_intr_disestablish __P((struct device *, void *)); 54 void tc_3000_300_iointr __P((void *, unsigned long)); 55 56 int tc_3000_300_intrnull __P((void *)); 57 58 #define C(x) ((void *)(u_long)x) 59 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 60 61 /* 62 * We have to read and modify the IOASIC registers directly, because 63 * the TC option slot interrupt request and mask bits are stored there, 64 * and the ioasic code isn't initted when we need to frob some interrupt 65 * bits. 66 */ 67 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 68 69 struct tc_slotdesc tc_3000_300_slots[] = { 70 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 71 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 72 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - TCDS ASIC */ 73 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - IOCTL ASIC */ 74 { KV(0x1c0000000), C(TC_3000_300_DEV_CXTURBO), }, /* 4 - CXTurbo */ 75 }; 76 int tc_3000_300_nslots = 77 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 78 79 struct tc_builtin tc_3000_300_builtins[] = { 80 { "PMAGB-BA", 4, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 81 { "FLAMG-IO", 3, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 82 { "PMAZ-DS ", 2, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 83 }; 84 int tc_3000_300_nbuiltins = 85 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 86 87 struct tcintr { 88 int (*tci_func) __P((void *)); 89 void *tci_arg; 90 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 91 92 void 93 tc_3000_300_intr_setup() 94 { 95 volatile u_int32_t *imskp; 96 u_long i; 97 98 /* 99 * Disable all interrupts that we can (can't disable builtins). 100 */ 101 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 102 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 103 104 /* 105 * Set up interrupt handlers. 106 */ 107 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 108 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 109 tc_3000_300_intr[i].tci_arg = (void *)i; 110 } 111 } 112 113 void 114 tc_3000_300_intr_establish(tcadev, cookie, level, func, arg) 115 struct device *tcadev; 116 void *cookie, *arg; 117 tc_intrlevel_t level; 118 int (*func) __P((void *)); 119 { 120 volatile u_int32_t *imskp; 121 u_long dev = (u_long)cookie; 122 123 #ifdef DIAGNOSTIC 124 /* XXX bounds-check cookie. */ 125 #endif 126 127 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 128 panic("tc_3000_300_intr_establish: cookie %d twice", dev); 129 130 tc_3000_300_intr[dev].tci_func = func; 131 tc_3000_300_intr[dev].tci_arg = arg; 132 133 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 134 switch (dev) { 135 case TC_3000_300_DEV_OPT0: 136 *imskp |= IOASIC_INTR_300_OPT0; 137 break; 138 case TC_3000_300_DEV_OPT1: 139 *imskp |= IOASIC_INTR_300_OPT1; 140 break; 141 default: 142 /* interrupts for builtins always enabled */ 143 break; 144 } 145 } 146 147 void 148 tc_3000_300_intr_disestablish(tcadev, cookie) 149 struct device *tcadev; 150 void *cookie; 151 { 152 volatile u_int32_t *imskp; 153 u_long dev = (u_long)cookie; 154 155 #ifdef DIAGNOSTIC 156 /* XXX bounds-check cookie. */ 157 #endif 158 159 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 160 panic("tc_3000_300_intr_disestablish: cookie %d bad intr", 161 dev); 162 163 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 164 switch (dev) { 165 case TC_3000_300_DEV_OPT0: 166 *imskp &= ~IOASIC_INTR_300_OPT0; 167 break; 168 case TC_3000_300_DEV_OPT1: 169 *imskp &= ~IOASIC_INTR_300_OPT1; 170 break; 171 default: 172 /* interrupts for builtins always enabled */ 173 break; 174 } 175 176 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 177 tc_3000_300_intr[dev].tci_arg = (void *)dev; 178 } 179 180 int 181 tc_3000_300_intrnull(val) 182 void *val; 183 { 184 185 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n", 186 (u_long)val); 187 } 188 189 void 190 tc_3000_300_iointr(framep, vec) 191 void *framep; 192 unsigned long vec; 193 { 194 u_int32_t tcir, ioasicir, ioasicimr; 195 int ifound; 196 197 #ifdef DIAGNOSTIC 198 int s; 199 if (vec != 0x800) 200 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 201 s = splhigh(); 202 if (s != ALPHA_PSL_IPL_IO) 203 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 204 ALPHA_PSL_IPL_IO); 205 splx(s); 206 #endif 207 208 do { 209 tc_syncbus(); 210 211 /* find out what interrupts/errors occurred */ 212 tcir = *(volatile u_int32_t *)TC_3000_300_IR; 213 ioasicir = *(volatile u_int32_t *) 214 IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR); 215 ioasicimr = *(volatile u_int32_t *) 216 IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 217 tc_mb(); 218 219 /* Ignore interrupts that aren't enabled out. */ 220 ioasicir &= ioasicimr; 221 222 /* clear the interrupts/errors we found. */ 223 *(volatile u_int32_t *)TC_3000_300_IR = tcir; 224 /* XXX can't clear TC option slot interrupts here? */ 225 tc_wmb(); 226 227 ifound = 0; 228 229 #ifdef EVCNT_COUNTERS 230 /* No interrupt counting via evcnt counters */ 231 XXX BREAK HERE XXX 232 #else /* !EVCNT_COUNTERS */ 233 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN16 + slot]++ 234 #endif /* EVCNT_COUNTERS */ 235 236 #define CHECKINTR(slot, flag) \ 237 if (flag) { \ 238 ifound = 1; \ 239 INCRINTRCNT(slot); \ 240 (*tc_3000_300_intr[slot].tci_func) \ 241 (tc_3000_300_intr[slot].tci_arg); \ 242 } 243 /* Do them in order of priority; highest slot # first. */ 244 CHECKINTR(TC_3000_300_DEV_CXTURBO, 245 tcir & TC_3000_300_IR_CXTURBO); 246 CHECKINTR(TC_3000_300_DEV_IOASIC, 247 (tcir & TC_3000_300_IR_IOASIC) && 248 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 249 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 250 CHECKINTR(TC_3000_300_DEV_OPT1, 251 ioasicir & IOASIC_INTR_300_OPT1); 252 CHECKINTR(TC_3000_300_DEV_OPT0, 253 ioasicir & IOASIC_INTR_300_OPT0); 254 #undef CHECKINTR 255 256 #ifdef DIAGNOSTIC 257 #define PRINTINTR(msg, bits) \ 258 if (tcir & bits) \ 259 printf(msg); 260 PRINTINTR("BCache tag parity error\n", 261 TC_3000_300_IR_BCTAGPARITY); 262 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 263 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 264 PRINTINTR("Bcache parity error\n", 265 TC_3000_300_IR_BCACHEPARITY); 266 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 267 #undef PRINTINTR 268 #endif 269 } while (ifound); 270 } 271
Indexes created Thu Oct 02 14:10:14 GMT 2025