tc_3000_300.c revision 1.24
1 /* $NetBSD: tc_3000_300.c,v 1.24 2000/06/04 19:14:28 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.24 2000/06/04 19:14:28 cgd Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/pte.h> 40 #ifndef EVCNT_COUNTERS 41 #include <machine/intrcnt.h> 42 #endif 43 44 #include <dev/tc/tcvar.h> 45 #include <dev/tc/ioasicreg.h> 46 #include <alpha/tc/tc_conf.h> 47 #include <alpha/tc/tc_3000_300.h> 48 49 #include "wsdisplay.h" 50 #include "sfb.h" 51 52 #if NSFB > 0 53 extern int sfb_cnattach __P((tc_addr_t)); 54 #endif 55 56 int tc_3000_300_intrnull __P((void *)); 57 58 #define C(x) ((void *)(u_long)x) 59 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 60 61 /* 62 * We have to read and modify the IOASIC registers directly, because 63 * the TC option slot interrupt request and mask bits are stored there, 64 * and the ioasic code isn't initted when we need to frob some interrupt 65 * bits. 66 */ 67 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 68 69 struct tc_slotdesc tc_3000_300_slots[] = { 70 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 71 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 72 { KV(0x140000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - unused */ 73 { KV(0x160000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - unused */ 74 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 4 - TCDS ASIC */ 75 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 5 - IOCTL ASIC */ 76 { KV(0x1c0000000), C(TC_3000_300_DEV_BOGUS), }, /* 6 - CXTurbo */ 77 }; 78 int tc_3000_300_nslots = 79 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 80 81 struct tc_builtin tc_3000_300_builtins[] = { 82 { "PMAGB-BA", 6, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 83 { "FLAMG-IO", 5, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 84 { "PMAZ-DS ", 4, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 85 }; 86 int tc_3000_300_nbuiltins = 87 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 88 89 struct tcintr { 90 int (*tci_func) __P((void *)); 91 void *tci_arg; 92 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 93 94 void 95 tc_3000_300_intr_setup() 96 { 97 volatile u_int32_t *imskp; 98 u_long i; 99 100 /* 101 * Disable all interrupts that we can (can't disable builtins). 102 */ 103 imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 104 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 105 106 /* 107 * Set up interrupt handlers. 108 */ 109 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 110 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 111 tc_3000_300_intr[i].tci_arg = (void *)i; 112 } 113 } 114 115 const struct evcnt * 116 tc_3000_300_intr_evcnt(tcadev, cookie) 117 struct device *tcadev; 118 void *cookie; 119 { 120 121 /* XXX for now, no evcnt parent reported */ 122 return (NULL); 123 } 124 125 void 126 tc_3000_300_intr_establish(tcadev, cookie, level, func, arg) 127 struct device *tcadev; 128 void *cookie, *arg; 129 tc_intrlevel_t level; 130 int (*func) __P((void *)); 131 { 132 volatile u_int32_t *imskp; 133 u_long dev = (u_long)cookie; 134 135 #ifdef DIAGNOSTIC 136 /* XXX bounds-check cookie. */ 137 #endif 138 139 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 140 panic("tc_3000_300_intr_establish: cookie %lu twice", dev); 141 142 tc_3000_300_intr[dev].tci_func = func; 143 tc_3000_300_intr[dev].tci_arg = arg; 144 145 imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 146 switch (dev) { 147 case TC_3000_300_DEV_OPT0: 148 *imskp |= IOASIC_INTR_300_OPT0; 149 break; 150 case TC_3000_300_DEV_OPT1: 151 *imskp |= IOASIC_INTR_300_OPT1; 152 break; 153 default: 154 /* interrupts for builtins always enabled */ 155 break; 156 } 157 } 158 159 void 160 tc_3000_300_intr_disestablish(tcadev, cookie) 161 struct device *tcadev; 162 void *cookie; 163 { 164 volatile u_int32_t *imskp; 165 u_long dev = (u_long)cookie; 166 167 #ifdef DIAGNOSTIC 168 /* XXX bounds-check cookie. */ 169 #endif 170 171 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 172 panic("tc_3000_300_intr_disestablish: cookie %lu bad intr", 173 dev); 174 175 imskp = (volatile u_int32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 176 switch (dev) { 177 case TC_3000_300_DEV_OPT0: 178 *imskp &= ~IOASIC_INTR_300_OPT0; 179 break; 180 case TC_3000_300_DEV_OPT1: 181 *imskp &= ~IOASIC_INTR_300_OPT1; 182 break; 183 default: 184 /* interrupts for builtins always enabled */ 185 break; 186 } 187 188 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 189 tc_3000_300_intr[dev].tci_arg = (void *)dev; 190 } 191 192 int 193 tc_3000_300_intrnull(val) 194 void *val; 195 { 196 197 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n", 198 (u_long)val); 199 } 200 201 void 202 tc_3000_300_iointr(framep, vec) 203 void *framep; 204 unsigned long vec; 205 { 206 u_int32_t tcir, ioasicir, ioasicimr; 207 int ifound; 208 209 #ifdef DIAGNOSTIC 210 int s; 211 if (vec != 0x800) 212 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 213 s = splhigh(); 214 if (s != ALPHA_PSL_IPL_IO) 215 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 216 ALPHA_PSL_IPL_IO); 217 splx(s); 218 #endif 219 220 do { 221 tc_syncbus(); 222 223 /* find out what interrupts/errors occurred */ 224 tcir = *(volatile u_int32_t *)TC_3000_300_IR; 225 ioasicir = *(volatile u_int32_t *) 226 (DEC_3000_300_IOASIC_ADDR + IOASIC_INTR); 227 ioasicimr = *(volatile u_int32_t *) 228 (DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 229 tc_mb(); 230 231 /* Ignore interrupts that aren't enabled out. */ 232 ioasicir &= ioasicimr; 233 234 /* clear the interrupts/errors we found. */ 235 *(volatile u_int32_t *)TC_3000_300_IR = tcir; 236 /* XXX can't clear TC option slot interrupts here? */ 237 tc_wmb(); 238 239 ifound = 0; 240 241 #ifdef EVCNT_COUNTERS 242 /* No interrupt counting via evcnt counters */ 243 XXX BREAK HERE XXX 244 #else /* !EVCNT_COUNTERS */ 245 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN16 + slot]++ 246 #endif /* EVCNT_COUNTERS */ 247 248 #define CHECKINTR(slot, flag) \ 249 if (flag) { \ 250 ifound = 1; \ 251 INCRINTRCNT(slot); \ 252 (*tc_3000_300_intr[slot].tci_func) \ 253 (tc_3000_300_intr[slot].tci_arg); \ 254 } 255 /* Do them in order of priority; highest slot # first. */ 256 CHECKINTR(TC_3000_300_DEV_CXTURBO, 257 tcir & TC_3000_300_IR_CXTURBO); 258 CHECKINTR(TC_3000_300_DEV_IOASIC, 259 (tcir & TC_3000_300_IR_IOASIC) && 260 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 261 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 262 CHECKINTR(TC_3000_300_DEV_OPT1, 263 ioasicir & IOASIC_INTR_300_OPT1); 264 CHECKINTR(TC_3000_300_DEV_OPT0, 265 ioasicir & IOASIC_INTR_300_OPT0); 266 #undef CHECKINTR 267 268 #ifdef DIAGNOSTIC 269 #define PRINTINTR(msg, bits) \ 270 if (tcir & bits) \ 271 printf(msg); 272 PRINTINTR("BCache tag parity error\n", 273 TC_3000_300_IR_BCTAGPARITY); 274 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 275 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 276 PRINTINTR("Bcache parity error\n", 277 TC_3000_300_IR_BCACHEPARITY); 278 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 279 #undef PRINTINTR 280 #endif 281 } while (ifound); 282 } 283 284 #if NWSDISPLAY > 0 285 /* 286 * tc_3000_300_fb_cnattach -- 287 * Attempt to map the CTB output device to a slot and attach the 288 * framebuffer as the output side of the console. 289 */ 290 int 291 tc_3000_300_fb_cnattach(turbo_slot) 292 u_int64_t turbo_slot; 293 { 294 u_int32_t output_slot; 295 296 output_slot = turbo_slot & 0xffffffff; 297 298 if (output_slot >= tc_3000_300_nslots) { 299 return EINVAL; 300 } 301 302 if (output_slot == 0) { 303 #if NSFB > 0 304 sfb_cnattach(KV(0x1c0000000) + 0x02000000); 305 return 0; 306 #else 307 return ENXIO; 308 #endif 309 } 310 311 return tc_fb_cnattach(tc_3000_300_slots[output_slot-1].tcs_addr); 312 } 313 #endif /* NWSDISPLAY */ 314
Indexes created Thu Oct 02 14:10:14 GMT 2025